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| To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Renesas Technology Home Page: http://www.renesas.com Renesas Technology Corp. Customer Support Dept. April 1, 2003 Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. 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Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein. Hitachi 16-Bit Single-Chip Microcomputer H8S/2626 Series, H8S/2623 Series H8S/2626F-ZTATTM, H8S/2623F-ZTATTM H8S/2626 Series H8S/2626 H8S/2625 H8S/2624 H8S/2623 H8S/2622 H8S/2621 HD6432626 HD6432625 HD6432624 HD6432623 HD6432622 HD6432621 H8S/2623 Series H8S/2626F-ZTATTM HD64F2626 H8S/2623F-ZTATTM HD64F2623 Hardware Manual ADE-602-164C Rev. 4.0 10/30/03 Hitachi, Ltd. The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products. General Precautions on the Handling of Products 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Address Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these address. Do not access these registers: the system's operation is not guaranteed if they are accessed. Preface The H8S/2626 Series and H8S/2623 Series are series of high-performance microcontrollers with a 32-bit H8S/2600 CPU core, and a set of on-chip supporting modules required for system configuration. The H8S/2600 CPU can execute basic instructions in one state, and is provided with sixteen 16-bit general registers with a 32-bit internal configuration, and a concise and optimized instruction set. The CPU can handle a 16 Mbyte linear address space (architecturally 4 Gbytes). Programs based on the high-level language C can also be run efficiently. The address space is divided into eight areas. The data bus width and access states can be selected for each of these areas, and various kinds of memory can be connected fast and easily. Single-power-supply flash memory (F-ZTATTM*), and mask ROM versions are available, providing a quick and flexible response to conditions from ramp-up through full-scale volume production, even for applications with frequently changing specifications. On-chip supporting functions include a 16-bit timer pulse unit (TPU), programmable pulse generator (PPG), watchdog timer (WDT), serial communication interface (SCI), Hitachi controller area network (HCAN), A/D converter, D/A converter (H8S/2626 Series only), and I/O ports. In addition, data transfer controller (DTC) is provided, enabling high-speed data transfer without CPU intervention. Use of the H8S/2626 Series or H8S/2623 Series enables easy implementation of compact, highperformance systems capable of processing large volumes of data. This manual describes the hardware of the H8S/2626 Series and H8S/2623 Series. Refer to the H8S/2600 Series and H8S/2000 Series Programming Manual for a detailed description of the instruction set. Note: * F-ZTAT (Flexible-ZTAT) is a trademark of Hitachi, Ltd. List of Items Revised or Added for This Version Section 1.1 Overview Page 4 5 1.2 Internal Block Diagram Figure 1-1 Internal Block Diagram (H8S/2623 Series) 6 NMI FWE* PF7/o PF6/AS PF5/RD PF4/HWR PF3/LWR/ADTRG/IRQ3 PF2/WAIT/BREQO PF1/BACK PF0/BREQ/IRQ2 Description Note * deleted from memory specifications Note * deleted from product lineup specifications Interrupt controller PC break controller (2 channels) Port F ROM (Mask ROM, flash memory) Note *1 deleted Note: * The FWE pin is used only in the flash memory version. Figure 1-2 Internal Block Diagram (H8S/2626 Series) 7 NMI FWE* PF7/o PF6/AS PF5/RD PF4/HWR PF3/LWR/ADTRG/IRQ3 PF2/WAIT/BREQO PF1/BACK PF0/BREQ/IRQ2 Interrupt controller PC break controller (2 channels) Port F ROM (mask ROM or flash memory) Note *1 deleted Note: * The FWE pin is used only in the flash memory version. 5.6.3 Operation (3) Operation Order Table 5-11 Interrupt Source Selection and Clearing Control (4) Notes on Use 121 DTC DTCE 0 1 DISEL * 0 1 Settings Interrupt Source Selection/Clearing Control DTC X O CPU X 2nd line changed as follows SCI and A/D converter interrupt sources are cleared when the DTC reads or writes to the prescribed register. Section 8.3.3 DTC Vector Table Table 8-4 Interrupt Sources, DTC Vector Addresses, and Corresponding Page 194 Description TGI5A (GR5A compare TPU 60 match/input capture) channel 5 TGI5B (GR5B compare match/input capture) Reserved -- 61 64 65 68 69 72 73 74 75 RXI0 (reception complete 0) SCI 81 H'0478 H'047A H'0480 H'0482 H'0488 H'048A H'0490 H'0492 H'0494 H'0496 H'04A2 H'04A4 DTCED5 DTCED4 DTCED3 DTCED2 DTCED1 DTCED0 DTCEE7 DTCEE6 DTCEE5 DTCEE4 DTCEE3 DTCEE2 TXI0 channel 0 82 (transmit data empty 0) 8.3.10 Number of DTC 203 Execution States 4th line changed as follows Number of execution states = I * (SI + 1) + (J * SJ + K * SK + L * SL) + M * SM For example, when the DTC vector address table is located in on-chip ROM, normal mode is set, and data is transferred from the on-chip ROM to an internal I/O register, the time required for the DTC operation is 14 states. The time from activation to the end of the data write is 11 states. 9.10.2 Register Configuration 275 Port F Data Register (PFDR) Bit : 7 -- Initial value : Read/Write : 0 R/W 6 PF6DR 0 R/W 5 PF5DR 0 R/W 4 PF4DR 0 R/W 3 PF3DR 0 R/W 2 PF2DR 0 R/W 1 PF1DR 0 R/W 0 PF0DR 0 R/W Explanation added to 8th line as follows Bit 7 in PFDR is reserved, and only 0 may be written to it. 12.2.2 Timer 402 Control/Status Register (TCSR) Bit 7--Overflow Flag (OVF) Explanation added to 8th line as follows In interval timer mode, to clear OVF flag in WOVI handling routine, read TCSR when OVF = 1, then write with 0 to OVF, as stated above. When WOVI is masked and OVF flag is poling, if contention between OVF flag set and TCSR read is occurred, OVF = 1 is read but OVF can not be cleared by writing with 0 to OVF. In this case, reading TCSR when OVF = 1 two times meet the requirements of OVF clear condition. Please read TCSR when OVF = 1 two times before writing with 0 to OVF. Section 12.5.6 OVF Flag Clearing in Interval Timer Mode Page 416 Description Newly added 12.5.6 OVF Flag Clearing in Interval Timer Mode When the OVF Flag setting conflicts with the OVF flag reading in interval timer mode, writing 0 to the OVF bit may not clear the flag even though the OVF bit has been read while it is 1. If there is a possibility that the OVF flag setting and reading will conflict, such as when the OVF flag is polled with the interval timer interrupt disabled, read the OVF bit while it is 1 at least twice before writing 0 to the OVF bit to clear the flag. 13.2.8 Bit Rate Register (BRR) Table 13-3 BRR Settings for Various Bit Rates (Asynchronous Mode) Table 13-4 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Table 13-5 Maximum Bit Rate for Each Frequency (Asynchronous Mode) Table 13-6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) Table 13-7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) 436 2 MHz, 2.097152 MHz, 2.4576 MHz, 3 MHz, and 3.6864 MHz columns of table deleted 439 2 MHz column of table deleted 441 2 MHz, 2.097152 MHz, 2.4576 MHz, 3 MHz, and 3.6864 MHz rows of table deleted 442 2 MHz, 2.097152 MHz, 2.4576 MHz, 3 MHz, and 3.6864 MHz rows of table deleted 442 2 MHz row of table deleted 15.2.2 General Status 525 Register (GSR) 7th line changed as follows The general status register (GSR) is an 8-bit readable register that indicates the status of the CAN bus. 9th line changed as follows Bits 7 to 4--Reserved: These bits always read 0. 15.2.3 Bit Configuration Register (BCR) -- 15.3.2 Initialization after Hardware Reset Detailed Description of One Bit of figure, HCAN bit rate calculation, BCR Setting Constraints, Setting Range for TSEG1 and TSEG2 in BCR of table Moved to Bit Rate and Bit Timing Settings Section 15.2.7 Transmit Acknowledge Register (TXACK) Page 532 Description TXACK Bit : 15 0 R/(W)* 7 0 R/(W)* 14 0 R/(W)* 6 0 R/(W)* 13 0 R/(W)* 5 0 R/(W)* 12 0 R/(W)* 4 0 R/(W)* 11 0 R/(W)* 3 0 R/(W)* 10 0 R/(W)* 2 0 R/(W)* 9 0 R/(W)* 1 0 R/(W)* 8 -- 0 R 0 0 R/(W)* TXACK7 TXACK6 TXACK5 TXACK4 TXACK3 TXACK2 TXACK1 Initial value : Read/Write : Bit : TXACK15 TXACK14 TXACK13 TXACK12 TXACK11 TXACK10 TXACK9 TXACK8 Initial value : Read/Write : Note added Note: * Can only be written with 1 for flag clearing. 15.2.8 Abort Acknowledge Register (ABACK) 533 ABACK Bit : 15 0 R/(W)* 7 0 R/(W)* 14 0 R/(W)* 6 0 R/(W)* 13 0 R/(W)* 5 0 R/(W)* 12 0 R/(W)* 4 0 R/(W)* 11 0 R/(W)* 3 0 R/(W)* 10 0 R/(W)* 2 0 R/(W)* 9 0 R/(W)* 1 0 R/(W)* 8 -- 0 R 0 0 R/(W)* ABACK7 ABACK6 ABACK5 ABACK4 ABACK3 ABACK2 ABACK1 Initial value : Read/Write : Bit : ABACK15 ABACK14 ABACK13 ABACK12 ABACK11 ABACK10 ABACK9 ABACK8 Initial value : Read/Write : Note added Note: * Can only be written with 1 for flag clearing. 15.2.9 Receive Complete Register (RXPR) 534 RXPR Bit : 15 RXPR7 Initial value : Read/Write : Bit : 0 R/(W)* 7 0 R/(W)* 14 RXPR6 0 R/(W)* 6 0 R/(W)* 13 RXPR5 0 R/(W)* 5 0 R/(W)* 12 RXPR4 0 R/(W)* 4 0 R/(W)* 11 RXPR3 0 R/(W)* 3 0 R/(W)* 10 RXPR2 0 R/(W)* 2 0 R/(W)* 9 RXPR1 0 R/(W)* 1 0 R/(W)* 8 RXPR0 0 R/(W)* 0 RXPR8 0 R/(W)* RXPR15 RXPR14 RXPR13 RXPR12 RXPR11 RXPR10 RXPR9 Initial value : Read/Write : Note added Note: * Can only be written with 1 for flag clearing. Section 15.2.10 Remote Request Register (RFPR) Page 535 Description RFPR Bit : 15 RFPR7 Initial value : Read/Write : Bit : 0 R/(W)* 7 0 R/(W)* 14 RFPR6 0 R/(W)* 6 0 R/(W)* 13 RFPR5 0 R/(W)* 5 0 R/(W)* 12 RFPR4 0 R/(W)* 4 0 R/(W)* 11 RFPR3 0 R/(W)* 3 0 R/(W)* 10 RFPR2 0 R/(W)* 2 0 R/(W)* 9 RFPR1 0 R/(W)* 1 0 R/(W)* 8 RFPR0 0 R/(W)* 0 RFPR8 0 R/(W)* RFPR15 RFPR14 RFPR13 RFPR12 RFPR11 RFPR10 RFPR9 Initial value : Read/Write : Note added Note: * Can only be written with 1 for flag clearing. 15.2.11 Interrupt Register (IRR) 536 IRR Bit : 15 IRR7 Initial value : Read/Write : Bit : 0 R/(W)* 14 IRR6 0 R/(W)* 13 IRR5 0 R/(W)* 12 IRR4 0 R/(W)* 11 IRR3 0 R/(W)* 10 IRR2 0 R 9 IRR1 0 R 8 IRR0 0 R/(W)* 7 -- 0 -- 6 -- 0 -- 5 -- 0 -- 4 IRR12 0 R/(W)* 3 -- 0 -- 2 -- 0 -- 1 IRR9 0 R 0 IRR8 0 R/(W)* Initial value : Read/Write : Note added Note: * Can only be written with 1 for flag clearing. 15.2.16 Unread Message Status Register (UMSR) 544 UMSR Bit: 15 UMSR7 14 UMSR6 13 UMSR5 12 UMSR4 11 UMSR3 10 UMSR2 9 UMSR1 8 UMSR0 Initial value: R/W: Bit: 0 R/(W)* 7 0 R/(W)* 6 0 R/(W)* 5 0 R/(W)* 4 0 R/(W)* 3 0 R/(W)* 2 0 R/(W)* 1 UMSR9 0 R/(W)* 0 UMSR8 UMSR15 UMSR14 UMSR13 UMSR12 UMSR11 UMSR10 Initial value: R/W: 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* Note added Note: * Can only be written with 1 for flag clearing. Section 15.3.2 Initialization after Hardware Reset Bit Rate and Bit Timing Settings Page 557 to 559 Description Bit Rate and Bit Timing Settings: As bit rate settings, a baud rate setting and bit timing setting must be made each time a CAN node begins communication. The baud rate and bit timing settings are made in the bit configuration register (BCR). a. Note BCR can be written to at all times, but should only be modified in configuration mode. Settings should be made so that all CAN controllers connected to the CAN bus have the same baud rate and bit width. Refer to table 15.3 for the range of values that can be used as settings (TSEG1, TSEG2, BRP, sample point, and SJW) for BCR. Table 15-3 BCR Register Value Setting Ranges Name Time segment 1 Time segment 2 Baud rate prescaler Sample point Re-synchronization jump width Abbreviation TSEG1 TSEG2 BRP SAM SJW Min. Value B'0000 B'000 B'000000 B'0 B'00 Max. Value B'1111 B'111 B'111111 B'1 B'11 b. * Value Setting Ranges The bit width consists of the total of the settable Time Quanta (TQ). TQ (number of system clocks) is determined by the baud rate prescaler (BRP). TQ = 2 x (BRP + 1) fCLK * The value of SJW is stipulated in the CAN specifications. 3 SJW 0 * The minimum value of TSEG1 is stipulated in the CAN specifications. TSEG1 > TSEG2 * The minimum value of TSEG2 is stipulated in the CAN specifications. TSEG2 SJW The following formula is used to calculate the baud rate. Bit rate [b/s] = fCLK 2 x (BRP + 1) x (3 + TSEG1 + TSEG2) Note: fCLK = f (system clock) The BCR values are used for BRP, TSEG1, and TSEG2. Example: With a 1 Mb/s baud rate and a 20 MHz input clock: 1 Mb/s = Item f CLK BRP TSEG1 TSEG2 20 MHz 2 x (0 + 1) x (3 + 4 + 3) Set Values 20 MHz 0 (B'000000) 4 (B'0100) 3 (B'011) Actual Values -- System clock x 2 5TQ 4TQ Section 15.3.2 Initialization after Hardware Reset Bit Rate and Bit Timing Settings Page 559, 560 Description 1-bit time 1-bit time (8-25 time quanta) SYNC_SEG PRSEG PHSEG1 PHSEG2 TSEG2 (time segment 2)* Quantum 2-8 1 Legend TSEG1 (time segment 1)* 2-16 SYNC_SEG: Segment for establishing synchronization of nodes on the CAN bus. (Normal bit edge transitions occur in this segment.) PRSEG: Segment for compensating for physical delay between networks. PHSEG1: Buffer segment for correcting phase drift (positive). (This segment is extended when synchronization (resynchronization) is established.) PHSEG2: Buffer segment for correcting phase drift (negative). (This segment is shortened when synchronization (resynchronization) is established.) Note: * The Time Quanta value for TSEG1 and TSEG2 is the TSEG value + 1. Figure 15-6 Detailed Description of One Bit HCAN bit rate calculation: Bit rate = fCLK 2 x (BRP + 1) x (3 + TSEG1 + TSEG2) Note: f CLK = o (system clock) The BCR values are used for BRP, TSEG1, and TSEG2. BCR Setting Constraints TSEG1 > TSEG2 SJW (SJW = 0 to 3) TSEG2 > B'001 (BRP = B'000000) TSEG2 > B'000 (BRP > B'000000) These constraints allow the setting range shown in table 15-3 for TSEG1 and TSEG2 in BCR. Table 15-4 Setting Range for TSEG1 and TSEG2 in BCR TSEG2 (BCR [14:12]) 001 TSEG1 (BCR [11:8]) 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 No Yes* Yes* Yes* Yes* Yes* Yes* Yes* Yes* Yes* Yes* Yes* Yes* 010 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 011 No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 100 No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 101 No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 110 No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes 111 No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Notes: The time quanta value for TSEG1 and TSEG2 is the TSEG value + 1. * Setting is enabled except when BRP [13:8] = B'000000. Section 15.5 Usage Notes 8. Using bit operation instructions 9. HTxD pin output in error passive state 10. Transition to HCAN sleep mode 11. Message transmission cancellation (TxCR) 12. TxCR in the bus off state Page 580 Description Newly added 8. Using bit operation instructions Start flags in HCAN are cleared by writing 1 to them; there is no need to use bit operation instructions to clear them. To clear a flag, use the MOV instruction to write a 1 to the bit to be cleared. 9. HTxD pin output in error passive state If the HRxD pin becomes fixed at 1 during message transmission or reception when the HCAN is in the error active state, the HTxD pin will output 0 continuously while in the error passive state. To stop continuous 0 output to the CAN bus, disable the HCAN by means of an error warning interrupt or by setting the HCAN module stop mode through detection of a fixed 1 state by the HxRD pin monitor. 10. Transition to HCAN sleep mode The HCAN stops (transmission/reception stops) when MCR0 is cleared to 0 immediately after an HCAN sleep mode transition effected by setting TXPR of the HCAN to 1 and setting MCR5 to 1. When a transition is made to the HCAN sleep mode by means of the above steps, a 10-cycle wait should be inserted after the TxPR setting. After an HCAN sleep mode transition, release the HCAN sleep mode by clearing MCR5 to 0. 11. Message transmission cancellation (TxCR) If all the following conditions are met when cancellation of a transmission message is performed by means of TxCR of the HCAN, the TxCR or TxPR bit indicating cancellation is not cleared even though internal transmission is canceled. When canceling a message using TxCR, 1 should be written continuously until TxCR or TxPR becomes 0. 12. TxCR in the bus off state If TxPR is set before the HCAN goes to the bus off state, and a transition is made to the bus off state with transmission incomplete, cancellation will be performed even if TxCR is set during the bus off period, and the message will be transmitted after a transition to the error active state. 19.11.2 Programmer Mode Operation Table 19-11 Settings for Various Operating Modes in Programmer Mode 656 Mode Read Output disable Command write Chip disable* 1 FWE H or L H or L H or L*3 H or L CE L L L H OE L H H X Pin Names WE H H L X I/O7- I/O0 Data output Hi-Z Data input Hi-Z A18-A0 Ain X Ain* 2 X Section 20.1.1 Block Diagram Figure 20-1 Block Diagram of Clock Pulse Generator Page 676 Description o SUB Clock selection circuit OSC1 OSC2 Subclock oscillator* Waveform shaping circuit* WDT1 count clock Legend: LPWRCR: Low-power control register SCKCR: System clock control register Note: * Supported only in the H8S/2626 Series, not available in the H8S/2623 Series. 20.3.1 Connecting a Crystal Resonator Table 20-2 Damping Resistance Value Table 20-3 Crystal Resonator Parameters 679 Frequency (MHz) Rd () 4 500 8 200 12 0 16 0 20 0 680 Frequency (MHz) RS max () C0 max (pF) 4 120 7 8 80 7 12 60 7 16 50 7 20 40 7 Figure 20-5 Points for Attention when Using PLL Oscillation Circuit 681 Figure replaced R1: 3 k PLLCAP Rp: 200 PLLVCC PLLVSS C1: 470 pF CPB: 0.1 F* PVCC1 to PVCC4 VCC VSS CB: 1000pF* CB: 300pF* (Values are preliminary recommended values.) Note: * CB and CPB are laminated ceramic capacitors. 4th line changed as follows Separate PLLVCC and PLLVSS from the other V CC/VSS and PVCC/PVSS lines at the board power supply source, and be sure to insert bypass capacitors CPB and CB close to the pins. 20.3.2 External Clock Input Table 20-4 External Clock Input Conditions 683 Vcc = 3.0 V to 3.6 V and PVcc = 3.0 V to 5.5 V portions deleted Section 21A.1 Overview Table 21A-1 LSI Internal States in Each Mode Page 688 Description DTC TPU PBC PPG Functioning Functioning Medium-speed Functioning operation Functioning Functioning (PBC mediumspeed operation) Halted (retained) Halted (retained) Halted (retained) Halted (retained) Halted (reset) Halted (reset) 21A.6.3 Setting 699 Oscillation Stabilization Time after Clearing Software Standby Mode Table 21A-4 Oscillation Stabilization Time Settings STS2 STS1 STS0 Standby Time 0 0 0 1 1 0 1 1 0 0 1 1 0 1 8192 states 16384 states 32768 states 65536 states 131072 states 262144 states Reserved 16 states* 20 16 12 10 8 6 4 MHz MHz MHz MHz MHz MHz MHz Unit 0.41 0.51 0.68 0.8 0.82 1.0 1.6 3.3 6.6 2.0 4.1 8.2 1.3 2.7 5.5 1.6 3.3 6.6 1.0 2.0 4.1 8.2 1.3 2.7 5.5 2.0 4.1 8.2 ms 10.9 16.4 10.9 13.1 16.4 21.8 32.8 13.1 16.4 21.8 26.2 32.8 43.6 65.6 -- 0.8 -- 1.0 -- 1.3 -- 1.6 -- 2.0 -- 1.7 -- 4.0 s Note amended Note: * Do not use this setting. Using an External Clock Newly added Using an External Clock: It is necessary to allow time for the PLL circuit to stabilize. Therefore, the standby time should be set to a value of 2 ms or greater. 21B.1 Overview 703 Note amended Note * Subclock functions are available in the H8S/2626 Series. See section 20.7, Subclock Oscillator, for the method of fixing pins OSC1 and OSC2 when not used. Table 21B-1 LSI Internal States in Each Mode 704 DTC Function- Medium- Function- Halted Halted Halted Halted Halted Halted ing speed ing (retained) (retained) (retained) (retained) (retained) (reset) operation Function- Function- Function- Halted Halted Halted Halted Halted Halted ing ing ing (retained) (retained) (retained) (retained) (retained) (reset) (PBC mediumspeed operation) (PBC subclock operation) TPU PBC PPG D/A2, 3 21B.5 Module Stop Mode Table 21B-4 MSTP Bits and Corresponding On-Chip Supporting Modules 718 Note *2 deleted from MSTPC5 Section Page Description 20 16 12 10 8 6 4 MHz MHz MHz MHz MHz MHz MHz Unit 0.41 0.51 0.68 0.8 0.82 1.0 1.6 3.3 6.6 2.0 4.1 8.2 1.3 2.7 5.5 1.6 3.3 6.6 1.0 2.0 4.1 8.2 1.3 2.7 5.5 2.0 4.1 8.2 ms 21B.6.3 Setting 720 Oscillation Stabilization Time after Clearing Software Standby Mode Table 21B-5 Oscillation Stabilization Time Settings STS2 STS1 STS0 Standby Time 0 0 0 1 1 0 1 1 0 0 1 1 0 1 8192 states 16384 states 32768 states 65536 states 131072 states 262144 states Reserved 16 states* 10.9 16.4 10.9 13.1 16.4 21.8 32.8 13.1 16.4 21.8 26.2 32.8 43.6 65.6 -- 0.8 -- 1.0 -- 1.3 -- 1.6 -- 2.0 -- 1.7 -- 4.0 s Note amended Note: * Do not use this setting. Using an External Clock Newly added Using an External Clock: It is necessary to allow time for the PLL circuit to stabilize. Therefore, the standby time should be set to a value of 2 ms or greater. 21B.13 Usage Notes 728 Newly added 21B.13 Usage Notes 1. When making a transition to sub-active mode or watch mode, set the DTC to enter module stop mode (write 1 to the relevant bits in MSTPCR), and then read the relevant bits to confirm that they are set to 1 before mode transition. Do not clear module stop mode (write 0 to the relevant bits in MSTPCR) until a transition from sub-active mode to high-speed mode or medium-speed mode has been performed. If a DTC activation source occurs in sub-active mode, the DTC will be activated only after module stop mode has been cleared and high-speed mode or medium-speed mode has been entered. 2. The on-chip peripheral modules (DTC and TPU) which halt operation in sub-active mode cannot clear an interrupt in sub-active mode. Therefore, if a transition is made to sub-active mode while an interrupt is requested, the CPU interrupt source cannot be cleared. Disable the interrupts of each on-chip peripheral module before executing a SLEEP instruction to enter sub-active mode or watch mode. Section 22.2 DC Characteristics Table 22-2 DC Characteristics Page 730 to 732 Description Conditions changed in 5th line as follows (Incorrect) Vref = 3.3 V to AV CC, VSS = AVSS = 0 V, (Correct) Vref = 4.5 V to AV CC, VSS = AVSS = 0 V, -- -- -- -- 1.0 1.0 A A Vin = 0.5 to PVCC - 0.5 V Input leakage RES | Iin | current STBY, NMI, HRxD, MD2 to MD0, FWE Port 4, 9 Three-state leakage current (off state) Port 1, A to F ITSI -- -- -- -- 1.0 1.0 A A Vin = 0.5 to AVCC - 0.5 V Vin = 0.5 to PVCC - 0.5 V MOS input Port A to E pull-up current -I P 30 -- 300 A Vin = 0 V Reference During A/D power supply and D/A current conversion Idle RAM standby voltage AlCC -- 2.5 4.0 mA Vref = 5.0 V -- VRAM 2.0 -- -- 5.0 -- A V Notes amended Notes: *1 If the A/D and D/A converter is not used, do not leave the AVCC, Vref , and AVSS pins open. Apply a voltage between 4.5 V and 5.5 V to the AVCC and Vref pins by connecting them to PV CC, for instance. Set Vref AVCC. *3 The values are for VRAM PVCC < 3.0 V, VIH min = V CC - 0.1 V, and VIL max = 0.1 V. 22.2 DC Characteristics Table 22-3 Permissible Output Currents 733 Conditions changed in 3rd line as follows (Incorrect) Vref = 3.3 V to AV CC, VSS = AVSS = 0 V, (Correct) Item Permissible output low current (per pin) Permissible output low current (total) All output pins Total of all output pins Vref = 4.5 V to AV CC, VSS = AVSS = 0 V, Symbol Min PVCC = 4.5 V to 5.5 V I OL PVCC = 4.5 V to 5.5 V IOL PVCC = 4.5 V to 5.5 V -I OH PVCC = 4.5 V to 5.5 V -IOH -- -- -- -- Typ -- -- -- -- Max 10 100 2.0 30 Unit mA mA mA mA Permissible output All output high current (per pin) pins Permissible output high current (total) Total of all output pins Section 22.3.1 Clock Timing Table 22-4 Clock Timing Page 734 Description Conditions changed in 5th line as follows (Incorrect) Vref = 3.3 V to AV CC, VSS = AVSS = 0 V, o = 32.768 kHz, 2 to 20 MHz (Correct) Vref = 4.5 V to AV CC, VSS = AVSS = 0 V, o = 32.768 kHz, 4 to 20 MHz Item Clock cycle time Clock high pulse width Symbol t cyc t CH Min 50 15 Max 250 -- Unit ns ns Test Conditions Figure 22-2 22.3.2 Control Signal Timing Table 22-5 Control Signal Timing 735 --Preliminary-- deleted Conditions changed in 5th line as follows (Incorrect) Vref = 3.3 V to AV CC, VSS = AVSS = 0 V, o = 32.768 kHz, 2 to 20 MHz (Correct) Vref = 4.5 V to AV CC, VSS = AVSS = 0 V, o = 32.768 kHz, 4 to 20 MHz 22.3.3 Bus Timing Table 22-6 Bus Timing 737 Conditions changed in 5th line as follows (Incorrect) Vref = 3.3 V to AV CC, VSS = AVSS = 0 V, o = 32.768 kHz, 2 to 20 MHz (Correct) Vref = 4.5 V to AV CC, VSS = AVSS = 0 V, o = 32.768 kHz, 4 to 20 MHz 22.3.4 Timing of OnChip Supporting Modules Table 22-7 Timing of On-Chip Supporting Modules 22.4 A/D Conversion Characteristics Table 22-8 A/D Conversion Characteristics 22.5 D/A Conversion Characteristics Table 22-9 D/A Conversion Characteristics 22.6 Flash Memory Characteristics Table 22-9 Flash Memory Characteristics 743 Conditions changed in 5th line as follows (Incorrect) Vref = 3.3 V to AV CC, VSS = AVSS = 0 V, o = 32.768 kHz, 2 to 20 MHz (Correct) Vref = 4.5 V to AV CC, VSS = AVSS = 0 V, o = 32.768 kHz, 4 to 20 MHz 747 Conditions changed in 5th line as follows (Incorrect) Vref = 4.5 V to AV CC, VSS = AVSS = 0 V, o = 2 to 20 MHz (Correct) Vref = 4.5 V to AV CC, VSS = AVSS = 0 V, o = 4 to 20 MHz 748 Conditions changed in 5th line as follows (Incorrect) Vref = 4.5 V to AV CC, VSS = AVSS = 0 V, o = 2 to 20 MHz (Correct) Vref = 4.5 V to AV CC, VSS = AVSS = 0 V, o = 4 to 20 MHz 749 Conditions changed in 5th line as follows (Incorrect) VCC= 3.0 V to 3.6 V, AVCC = 3.3 V to 5.5 V, VSS = AVSS = 0 V (Correct) VCC= 3.0 V to 3.6 V, AVCC = 4.5 V to 5.5 V, VSS = AVSS = 0 V Section Table A-1 Instruction Set 758, 759 A.1 Instruction List 753 to 774 Page Description Table amended Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 IHNZVC Advanced 12 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa -- Normal mode deleted Mnemonic DIVXU.B Rs,Rd Operation DIVXU Addressing Mode/ Instruction Length (Bytes) B 2 Rd16/Rs8Rd16 (RdH: remainder, -- -- [6] [7] -- -- RdL: quotient) (unsigned division) ERd32/Rs16ERd32 (Ed: remainder, -- -- [6] [7] -- -- Rd: quotient) (unsigned division) DIVXU.W Rs,ERd W 2 20 Operand Size 4 #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa divxs.B Rs,Rd Mnemonic -- DIVXS EXTS.W Rd DIVXS.W Rs,ERd EXTS.L ERd L 2 W W 2 4 B EXTS Condition Code Rd16/Rs8Rd16 (RdH: remainder, -- -- [8] [7] -- -- Operation IHNZVC RdL: 7> of Rd16) ( No. of States*1 13 Advanced 1 21 ( TAS B 4 TAS @ERd *3 ( MAC CLRMAC LDMAC STMAC @ERd-0CCR set, (1) ---- 1 0-- 4 Section A.1 Instruction List Table A-1 Instruction Set Page 775 Description Notes amended [6] [7] [8] [9] [10] [11] Set to 1 when the divisor is negative; otherwise cleared to 0. Set to 1 when the divisor is zero; otherwise cleared to 0. Set to 1 when the quotient is negative; otherwise cleared to 0. One additional state is required for execution when EXR is valid. MAC instruction results are indicated in the flags when the STMAC instruction is executed. A maximum of three additional states are required for execution of one of these instructions within three states after execution of a MAC instruction. For example, if there is a one-state instruction (such as NOP) between a MAC instruction and one of these instructions, that instruction will be two states longer. A.2 Instruction Codes Table A-2 Instruction Codes A.3 Operation Code Map Table A-3 Operation Code Map (1), (2) 785 Table amended MOVFPE MOVFPE @aa:16,Rd MOVTPE MOVTPE Rs,@aa:16 B B Cannot be used in the H8S/2626 Series or H8S/2623 Series. 791 Note added Note: * Cannot be used in the H8S/2626 Series and H8S/2623 Series. A.4 Number of States 800, Required for Instruction 801, Execution 804, Table A-5 Number of 805 Cycles in Instruction Execution A.5 Bus States during Instruction Execution 811, 813, 817 to 819 815, 818 Normal mode deleted Normal mode deleted Table amended Instruction 1 2 3 4 5 6 MOVFPE @aa:16,Rd*4 MOVTPE Rs,@aa:16*4 Cannot be used in the H8S/2626 Series or H8S/2623 Series. STMAC MACH,ERd R:W NEXT Section B.1 Address Page 840 Description Data Bus Width amended Address H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF95 H'FF96 H'FF97 H'FF98 H'FF99 H'FFA2 (Write) H'FFA3 (Read) H'FFA8 H'FFA9 H'FFAA H'FFAB H'FFAC H'FFB0 H'FFB3 H'FFB8 H'FFB9 H'FFBA H'FFBB H'FFBC H'FFBD H'FFBE ADCSR ADCR TCSR1*6 TCNT1* TCNT1* 6 Register Name ADDRA Bit 7 AD9 AD1 Bit 6 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE TRGS0 WT/IT Bit 5 AD7 -- AD7 -- AD7 -- AD7 -- ADST -- TME Bit 4 AD6 -- AD6 -- AD6 -- AD6 -- SCANCH3 -- PSS Bit 3 AD5 -- AD5 -- AD5 -- AD5 -- CH2 CKS1 RST/NMI Bit 2 AD4 -- AD4 -- AD4 -- AD4 -- CH1 CKS0 CKS2 Bit 1 AD3 -- AD3 -- AD3 -- AD3 -- CH0 -- CKS1 Bit 0 AD2 -- AD2 -- AD2 -- AD2 -- Module Name A/D converter Data Bus Width 16 ADDRB AD9 AD1 ADDRC AD9 AD1 ADDRD AD9 AD1 ADF TRGS1 OVF -- CKS0 WDT1 16 6 FLMCR1*3 FWE FLMCR2*3 FLER EBR1* EBR2* 3 SWE1 -- EB6 -- -- P16 P46 P96 -- PB6 PC6 PD6 PE6 PF6 ESU1 -- EB5 -- -- P15 P45 P95 PA5 PB5 PC5 PD5 PE5 PF5 PSU1 -- EB4 -- -- P14 P44 P94 PA4 PB4 PC4 PD4 PE4 PF4 EV1 -- EB3 EB11 -- P13 P43 P93 PA3 PB3 PC3 PD3 PE3 PF3 PV1 -- EB2 EB10 -- P12 P42 P92 PA2 PB2 PC2 PD2 PE2 PF2 E1 -- EB1 EB9 -- P11 P41 P91 PA1 PB1 PC1 PD1 PE1 PF1 P1 -- EB0 EB8 -- P10 P40 P90 PA0 PB0 PC0 PD0 PE0 PF0 ROM 8 EB7 -- PDWND P17 P47 P97 -- PB7 PC7 PD7 PE7 PF7 3 FLPWCR PORT1 PORT4 PORT9 PORTA PORTB PORTC PORTD PORTE PORTF I/O port 8 B.2 Functions 851 TXACK--Transmit Acknowledge Register TXACK Bit : 15 0 R/(W)* 7 0 R/(W)* 14 0 R/(W)* 6 0 R/(W)* 13 0 R/(W)* 5 0 R/(W)* 12 0 R/(W)* 4 0 R/(W)* 11 0 R/(W)* 3 0 R/(W)* H'F80A HCAN 10 0 R/(W)* 2 0 R/(W)* 9 0 R/(W)* 1 0 R/(W)* 8 -- 0 R 0 0 R/(W)* TXACK7 TXACK6 TXACK5 TXACK4 TXACK3 TXACK2 TXACK1 Initial value : Read/Write : Bit : TXACK15 TXACK14 TXACK13 TXACK12 TXACK11 TXACK10 TXACK9 TXACK8 Initial value : Read/Write : Note added Note: * Can only be written with 1 for flag clearing. Section B.2 Functions Page 851 Description ABACK--Abort Acknowledge Register H'F80C ABACK Bit : 15 0 R/(W)* 7 0 R/(W)* 14 0 R/(W)* 6 0 R/(W)* 13 0 R/(W)* 5 0 R/(W)* 12 0 R/(W)* 4 0 R/(W)* 11 0 R/(W)* 3 0 R/(W)* 10 0 R/(W)* 2 0 R/(W)* 9 0 R/(W)* 1 0 R/(W)* 8 -- 0 R 0 0 R/(W)* ABACK7 ABACK6 ABACK5 ABACK4 ABACK3 ABACK2 ABACK1 Initial value : Read/Write : Bit : HCAN ABACK15 ABACK14 ABACK13 ABACK12 ABACK11 ABACK10 ABACK9 ABACK8 Initial value : Read/Write : Note added Note: * Can only be written with 1 for flag clearing. 852 RXPR--Receive Complete Register RXPR Bit : 15 RXPR7 Initial value : Read/Write : Bit : 0 R/(W)* 7 0 R/(W)* 14 RXPR6 0 R/(W)* 6 0 R/(W)* 13 RXPR5 0 R/(W)* 5 0 R/(W)* 12 RXPR4 0 R/(W)* 4 0 R/(W)* 11 RXPR3 0 R/(W)* 3 0 R/(W)* 10 RXPR2 0 R/(W)* 2 0 R/(W)* 9 RXPR1 0 R/(W)* 1 0 R/(W)* 8 RXPR0 0 R/(W)* 0 RXPR8 0 R/(W)* H'F80E HCAN RXPR15 RXPR14 RXPR13 RXPR12 RXPR11 RXPR10 RXPR9 Initial value : Read/Write : Note added Note: * Can only be written with 1 for flag clearing. RFPR--Remote Request Register RFPR Bit : 15 RFPR7 Initial value : Read/Write : Bit : 0 R/(W)* 7 0 R/(W)* 14 RFPR6 0 R/(W)* 6 0 R/(W)* 13 RFPR5 0 R/(W)* 5 0 R/(W)* 12 RFPR4 0 R/(W)* 4 0 R/(W)* 11 RFPR3 0 R/(W)* 3 0 R/(W)* 10 RFPR2 0 R/(W)* 2 0 R/(W)* 9 RFPR1 0 R/(W)* 1 RFPR9 0 R/(W)* 8 RFPR0 0 R/(W)* 0 RFPR8 0 R/(W)* H'F810 HCAN RFPR15 RFPR14 RFPR13 RFPR12 RFPR11 RFPR10 Initial value : Read/Write : Note added Note: * Can only be written with 1 for flag clearing. Section B.2 Functions Page 853, 854 Description IRR--Interrupt Register IRR Bit : 15 IRR7 Initial value : Read/Write : Bit : 0 R/(W)* 14 IRR6 0 R/(W)* 13 IRR5 0 R/(W)* 12 IRR4 0 R/(W)* 11 IRR3 0 R/(W)* 10 IRR2 0 R 9 IRR1 0 R 8 IRR0 0 R/(W)* H'F812 HCAN 7 -- 0 -- 6 -- 0 -- 5 -- 0 -- 4 IRR12 0 R/(W)* 3 -- 0 -- 2 -- 0 -- 1 IRR9 0 R 0 IRR8 0 R/(W)* Initial value : Read/Write : Note added Note: * Can only be written with 1 for flag clearing. 858 UMSR Bit : 15 UMSR7 Initial value : Read/Write : Bit : 0 R/(W)* 7 0 R/(W)* 14 UMSR6 0 R/(W)* 6 0 R/(W)* 13 UMSR5 0 R/(W)* 5 0 R/(W)* 12 UMSR4 0 R/(W)* 4 0 R/(W)* 11 UMSR3 0 R/(W)* 3 0 R/(W)* 10 UMSR2 0 R/(W)* 2 0 R/(W)* 9 UMSR1 0 R/(W)* 1 0 R/(W)* 8 UMSR0 0 R/(W)* 0 UMSR8 0 R/(W)* UMSR15 UMSR14 UMSR13 UMSR12 UMSR11 UMSR10 UMSR9 Initial value : Read/Write : Note added Note: * Can only be written with 1 for flag clearing. 861 MC1--Message Control H'F828 HCAN (Incorrect) x = 0 (Correct) x = 1 862 MC2--Message Control H'F830 HCAN (Incorrect) x = 0 (Correct) x = 2 863 MC3--Message Control H'F838 HCAN (Incorrect) x = 0 (Correct) x = 3 864 MC4--Message Control H'F840 HCAN (Incorrect) x = 0 (Correct) x = 4 865 MC5--Message Control H'F848 HCAN (Incorrect) x = 0 (Correct) x = 5 866 C6--Message Control H'F850 HCAN (Incorrect) x = 0 (Correct) x = 6 867 MC7--Message Control H'F858 HCAN (Incorrect) x = 0 (Correct) x = 7 868 MC8--Message Control H'F860 HCAN (Incorrect) x = 0 (Correct) x = 8 869 MC9--Message Control H'F868 HCAN (Incorrect) x = 0 (Correct) x = 9 Section B.2 Functions Page 870 Description MC10--Message Control H'F870 HCAN (Incorrect) x = 0 (Correct) x = 10 871 MC11--Message Control H'F878 HCAN (Incorrect) x = 0 (Correct) x = 11 872 MC12--Message Control H'F880 HCAN (Incorrect) x = 0 (Correct) x = 12 873 MC13--Message Control H'F888 HCAN (Incorrect) x = 0 (Correct) x = 13 874 MC14--Message Control H'F890 HCAN (Incorrect) x = 0 (Correct) x = 14 875 MC15--Message Control H'F898 HCAN (Incorrect) x = 0 (Correct) x = 15 881 SCKCR--System Clock Control Register Generator, Power-Down Note amended Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) and direct transition are not available in the H8S/2623 Series, but are available in the H8S/2626 Series. 930 PFDR--Port F Data Register Bit : 7 -- Initial value : Read/Write : 0 R/W 6 PF6DR 0 R/W 5 PF5DR 0 R/W H'FDE6 Clock Pulse H'FF0E 4 PF4DR 0 R/W Port F 3 PF3DR 0 R/W 2 PF2DR 0 R/W 1 PF1DR 0 R/W 0 PF0DR 0 R/W Stores output data for port F pins (PF6 to PF0) 979 ADDRA--A/D Data Register A ADDRB--A/D Data Register B ADDRC--A/D Data Register C ADDRD--A/D Data Register D Note added H'FF90 H'FF92 H'FF94 H'FF96 A/D Converter A/D Converter A/D Converter A/D Converter Note: The upper byte can be read directly, but for the lower byte, data transfer is performed via a temporary register (TEMP). For details, see section 16.3, Interface to Bus Master. C.4 Port A Block Diagrams Figure C-4 (c) Port A Block Diagram (Pin PA2) 1000 (Incorrect) SCK input enable, SCK input (Correct) RxD input enable, RxD input Section C.9 Port F Block Diagrams Figure C-9 (i) Port F Block Diagram (Pin PF7) Page 1018 Description Modes 4 to 6 S* Reset WDDRF PF7 Internal data bus R Q D D PF7DDR C RDRF RPORF Appendix F Product Code Lineup Table F-1 H8S/2626 Series and H8S/2623 Series Product Code Lineup 1023 Note * deleted Contents Section 1 1.1 1.2 1.3 Overview ........................................................................................................... 1 Overview............................................................................................................................ 1 Internal Block Diagram ..................................................................................................... 6 Pin Descriptions................................................................................................................. 8 1.3.1 Pin Arrangement .................................................................................................. 8 1.3.2 Pin Functions in Each Operating Mode................................................................ 10 1.3.3 Pin Functions........................................................................................................ 18 CPU..................................................................................................................... 23 23 23 24 25 25 26 31 32 32 33 34 36 37 37 39 40 40 41 43 52 54 54 57 61 61 62 63 66 66 66 i Section 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Overview............................................................................................................................ 2.1.1 Features ................................................................................................................ 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU .................................. 2.1.3 Differences from H8/300 CPU............................................................................. 2.1.4 Differences from H8/300H CPU.......................................................................... CPU Operating Modes ...................................................................................................... Address Space.................................................................................................................... Register Configuration ...................................................................................................... 2.4.1 Overview .............................................................................................................. 2.4.2 General Registers.................................................................................................. 2.4.3 Control Registers.................................................................................................. 2.4.4 Initial Register Values .......................................................................................... Data Formats...................................................................................................................... 2.5.1 General Register Data Formats ............................................................................ 2.5.2 Memory Data Formats.......................................................................................... Instruction Set.................................................................................................................... 2.6.1 Overview .............................................................................................................. 2.6.2 Instructions and Addressing Modes ..................................................................... 2.6.3 Table of Instructions Classified by Function........................................................ 2.6.4 Basic Instruction Formats..................................................................................... Addressing Modes and Effective Address Calculation ..................................................... 2.7.1 Addressing Mode.................................................................................................. 2.7.2 Effective Address Calculation.............................................................................. Processing States ............................................................................................................... 2.8.1 Overview .............................................................................................................. 2.8.2 Reset State ............................................................................................................ 2.8.3 Exception-Handling State .................................................................................... 2.8.4 Program Execution State ...................................................................................... 2.8.5 Bus-Released State ............................................................................................... 2.8.6 Power-Down State................................................................................................ Basic Timing...................................................................................................................... 2.9.1 Overview .............................................................................................................. 2.9.2 On-Chip Memory (ROM, RAM) ......................................................................... 2.9.3 On-Chip Supporting Module Access Timing....................................................... 2.9.4 On-Chip HCAN Module Access Timing ............................................................. 2.9.5 External Address Space Access Timing............................................................... 2.10 Usage Note ........................................................................................................................ 2.10.1 TAS Instruction .................................................................................................... 2.9 67 67 67 69 71 72 72 72 73 73 73 74 74 74 75 76 78 78 78 78 78 79 79 Section 3 3.1 3.2 3.3 3.4 3.5 MCU Operating Modes ................................................................................ Overview............................................................................................................................ 3.1.1 Operating Mode Selection.................................................................................... 3.1.2 Register Configuration ......................................................................................... Register Descriptions......................................................................................................... 3.2.1 Mode Control Register (MDCR).......................................................................... 3.2.2 System Control Register (SYSCR) ...................................................................... 3.2.3 Pin Function Control Register (PFCR) ................................................................ Operating Mode Descriptions............................................................................................ 3.3.1 Mode 4.................................................................................................................. 3.3.2 Mode 5.................................................................................................................. 3.3.3 Mode 6.................................................................................................................. 3.3.4 Mode 7.................................................................................................................. Pin Functions in Each Operating Mode............................................................................. Address Map in Each Operating Mode ............................................................................. Overview............................................................................................................................ 4.1.1 Exception Handling Types and Priority ............................................................... 4.1.2 Exception Handling Operation ............................................................................. 4.1.3 Exception Vector Table........................................................................................ Reset .................................................................................................................................. 4.2.1 Overview .............................................................................................................. 4.2.2 Reset Sequence..................................................................................................... 4.2.3 Interrupts after Reset ............................................................................................ 4.2.4 State of On-Chip Supporting Modules after Reset Release ................................. Traces ................................................................................................................................ Interrupts............................................................................................................................ Trap Instruction ................................................................................................................. Stack Status after Exception Handling .............................................................................. Notes on Use of the Stack.................................................................................................. Section 4 4.1 Exception Handling........................................................................................ 83 83 83 84 84 86 86 86 88 88 89 90 91 92 93 4.2 4.3 4.4 4.5 4.6 4.7 Section 5 5.1 ii Interrupt Controller ........................................................................................ 95 Overview............................................................................................................................ 95 5.2 5.3 5.4 5.5 5.6 5.1.1 Features ................................................................................................................ 5.1.2 Block Diagram...................................................................................................... 5.1.3 Pin Configuration ................................................................................................. 5.1.4 Register Configuration ......................................................................................... Register Descriptions......................................................................................................... 5.2.1 System Control Register (SYSCR) ...................................................................... 5.2.2 Interrupt Priority Registers A to K, M (IPRA to IPRK, IPRM)........................... 5.2.3 IRQ Enable Register (IER) .................................................................................. 5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 5.2.5 IRQ Status Register (ISR) .................................................................................... Interrupt Sources................................................................................................................ 5.3.1 External Interrupts................................................................................................ 5.3.2 Internal Interrupts ................................................................................................. 5.3.3 Interrupt Exception Handling Vector Table ......................................................... Interrupt Operation ............................................................................................................ 5.4.1 Interrupt Control Modes and Interrupt Operation ................................................ 5.4.2 Interrupt Control Mode 0...................................................................................... 5.4.3 Interrupt Control Mode 2...................................................................................... 5.4.4 Interrupt Exception Handling Sequence .............................................................. 5.4.5 Interrupt Response Times..................................................................................... Usage Notes ....................................................................................................................... 5.5.1 Contention between Interrupt Generation and Disabling..................................... 5.5.2 Instructions that Disable Interrupts ...................................................................... 5.5.3 Times when Interrupts are Disabled..................................................................... 5.5.4 Interrupts during Execution of EEPMOV Instruction.......................................... DTC Activation by Interrupt ............................................................................................. 5.6.1 Overview .............................................................................................................. 5.6.2 Block Diagram...................................................................................................... 5.6.3 Operation .............................................................................................................. 95 96 97 97 98 98 99 100 101 102 103 103 104 104 108 108 111 113 115 116 117 117 118 118 119 119 119 119 120 Section 6 6.1 PC Break Controller (PBC) ......................................................................... 123 123 123 124 125 125 125 126 126 128 128 129 129 iii 6.2 6.3 Overview............................................................................................................................ 6.1.1 Features ................................................................................................................ 6.1.2 Block Diagram...................................................................................................... 6.1.3 Register Configuration ......................................................................................... Register Descriptions......................................................................................................... 6.2.1 Break Address Register A (BARA) ..................................................................... 6.2.2 Break Address Register B (BARB)...................................................................... 6.2.3 Break Control Register A (BCRA) ...................................................................... 6.2.4 Break Control Register B (BCRB) ....................................................................... 6.2.5 Module Stop Control Register C (MSTPCRC).................................................... Operation ........................................................................................................................... 6.3.1 PC Break Interrupt Due to Instruction Fetch........................................................ 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.3.7 PC Break Interrupt Due to Data Access ............................................................... Notes on PC Break Interrupt Handling ................................................................ Operation in Transitions to Power-Down Modes ................................................ PC Break Operation in Continuous Data Transfer ............................................... When Instruction Execution is Delayed by One State ......................................... Additional Notes .................................................................................................. 129 130 130 131 132 133 Section 7 7.1 Bus Controller.................................................................................................. 135 135 135 136 137 138 139 139 140 141 145 147 148 150 150 151 152 153 154 154 154 156 157 165 167 167 167 169 170 170 172 173 174 174 174 175 7.2 7.3 7.4 7.5 7.6 7.7 7.8 Overview............................................................................................................................ 7.1.1 Features ................................................................................................................ 7.1.2 Block Diagram...................................................................................................... 7.1.3 Pin Configuration ................................................................................................. 7.1.4 Register Configuration ......................................................................................... Register Descriptions......................................................................................................... 7.2.1 Bus Width Control Register (ABWCR) ............................................................... 7.2.2 Access State Control Register (ASTCR).............................................................. 7.2.3 Wait Control Registers H and L (WCRH, WCRL).............................................. 7.2.4 Bus Control Register H (BCRH).......................................................................... 7.2.5 Bus Control Register L (BCRL)........................................................................... 7.2.6 Pin Function Control Register (PFCR) ................................................................ Overview of Bus Control................................................................................................... 7.3.1 Area Partitioning .................................................................................................. 7.3.2 Bus Specifications ................................................................................................ 7.3.3 Memory Interfaces................................................................................................ 7.3.4 Interface Specifications for Each Area................................................................. Basic Bus Interface............................................................................................................ 7.4.1 Overview .............................................................................................................. 7.4.2 Data Size and Data Alignment ............................................................................. 7.4.3 Valid Strobes ........................................................................................................ 7.4.4 Basic Timing ........................................................................................................ 7.4.5 Wait Control ......................................................................................................... Burst ROM Interface ......................................................................................................... 7.5.1 Overview .............................................................................................................. 7.5.2 Basic Timing ........................................................................................................ 7.5.3 Wait Control ......................................................................................................... Idle Cycle........................................................................................................................... 7.6.1 Operation .............................................................................................................. 7.6.2 Pin States in Idle Cycle ........................................................................................ Write Data Buffer Function ............................................................................................... Bus Release........................................................................................................................ 7.8.1 Overview .............................................................................................................. 7.8.2 Operation.............................................................................................................. 7.8.3 Pin States in External Bus Released State............................................................ iv 7.8.4 Transition Timing................................................................................................. 7.8.5 Usage Note ........................................................................................................... 7.9 Bus Arbitration .................................................................................................................. 7.9.1 Overview .............................................................................................................. 7.9.2 Operation .............................................................................................................. 7.9.3 Bus Transfer Timing ............................................................................................ 7.10 Resets and the Bus Controller............................................................................................ 176 177 177 177 177 178 178 179 179 179 180 181 182 182 184 185 185 185 186 186 187 188 189 189 191 192 195 196 197 198 200 201 202 204 205 208 208 209 209 213 213 v Section 8 8.1 8.2 8.3 8.4 8.5 Data Transfer Controller (DTC) ................................................................ Overview............................................................................................................................ 8.1.1 Features ................................................................................................................ 8.1.2 Block Diagram...................................................................................................... 8.1.3 Register Configuration ......................................................................................... Register Descriptions......................................................................................................... 8.2.1 DTC Mode Register A (MRA)............................................................................. 8.2.2 DTC Mode Register B (MRB) ............................................................................. 8.2.3 DTC Source Address Register (SAR) .................................................................. 8.2.4 DTC Destination Address Register (DAR) .......................................................... 8.2.5 DTC Transfer Count Register A (CRA) .............................................................. 8.2.6 DTC Transfer Count Register B (CRB) ............................................................... 8.2.7 DTC Enable Registers (DTCER) ......................................................................... 8.2.8 DTC Vector Register (DTVECR) ........................................................................ 8.2.9 Module Stop Control Register A (MSTPCRA).................................................... Operation ........................................................................................................................... 8.3.1 Overview .............................................................................................................. 8.3.2 Activation Sources................................................................................................ 8.3.3 DTC Vector Table ................................................................................................ 8.3.4 Location of Register Information in Address Space ............................................ 8.3.5 Normal Mode........................................................................................................ 8.3.6 Repeat Mode ........................................................................................................ 8.3.7 Block Transfer Mode............................................................................................ 8.3.8 Chain Transfer...................................................................................................... 8.3.9 Operation Timing ................................................................................................. 8.3.10 Number of DTC Execution States........................................................................ 8.3.11 Procedures for Using DTC ................................................................................... 8.3.12 Examples of Use of the DTC................................................................................ Interrupts............................................................................................................................ Usage Notes ....................................................................................................................... I/O Ports ............................................................................................................ Overview............................................................................................................................ Port 1.................................................................................................................................. 9.2.1 Overview .............................................................................................................. Section 9 9.1 9.2 9.2.2 Register Configuration ......................................................................................... 9.2.3 Pin Functions........................................................................................................ 9.3 Port 4.................................................................................................................................. 9.3.1 Overview .............................................................................................................. 9.3.2 Register Configuration ......................................................................................... 9.3.3 Pin Functions........................................................................................................ 9.4 Port 9.................................................................................................................................. 9.4.1 Overview .............................................................................................................. 9.4.2 Register Configuration ......................................................................................... 9.4.3 Pin Functions........................................................................................................ 9.5 Port A................................................................................................................................. 9.5.1 Overview .............................................................................................................. 9.5.2 Register Configuration ......................................................................................... 9.5.3 Pin Functions........................................................................................................ 9.5.4 MOS Input Pull-Up Function ............................................................................... 9.6 Port B ................................................................................................................................. 9.6.1 Overview .............................................................................................................. 9.6.2 Register Configuration ......................................................................................... 9.6.3 Pin Functions........................................................................................................ 9.6.4 MOS Input Pull-Up Function ............................................................................... 9.7 Port C ................................................................................................................................. 9.7.1 Overview .............................................................................................................. 9.7.2 Register Configuration ......................................................................................... 9.7.3 Pin Functions........................................................................................................ 9.7.4 MOS Input Pull-Up Function ............................................................................... 9.8 Port D................................................................................................................................. 9.8.1 Overview .............................................................................................................. 9.8.2 Register Configuration ......................................................................................... 9.8.3 Pin Functions........................................................................................................ 9.8.4 MOS Input Pull-Up Function ............................................................................... 9.9 Port E ................................................................................................................................. 9.9.1 Overview .............................................................................................................. 9.9.2 Register Configuration ......................................................................................... 9.9.3 Pin Functions........................................................................................................ 9.9.4 MOS Input Pull-Up Function ............................................................................... 9.10 Port F ................................................................................................................................. 9.10.1 Overview .............................................................................................................. 9.10.2 Register Configuration ......................................................................................... 9.10.3 Pin Functions........................................................................................................ 214 216 228 228 229 229 230 230 231 231 232 232 233 236 239 240 240 241 243 252 253 253 254 257 262 263 263 264 266 267 268 268 269 271 272 273 273 274 276 Section 10 16-Bit Timer Pulse Unit (TPU).................................................................. 279 10.1 Overview............................................................................................................................ 279 10.1.1 Features ................................................................................................................ 279 vi 10.2 10.3 10.4 10.5 10.6 10.7 10.1.2 Block Diagram...................................................................................................... 10.1.3 Pin Configuration ................................................................................................. 10.1.4 Register Configuration ......................................................................................... Register Descriptions......................................................................................................... 10.2.1 Timer Control Register (TCR) ............................................................................. 10.2.2 Timer Mode Register (TMDR) ............................................................................ 10.2.3 Timer I/O Control Register (TIOR) ..................................................................... 10.2.4 Timer Interrupt Enable Register (TIER) .............................................................. 10.2.5 Timer Status Register (TSR) ................................................................................ 10.2.6 Timer Counter (TCNT) ........................................................................................ 10.2.7 Timer General Register (TGR) ............................................................................ 10.2.8 Timer Start Register (TSTR)................................................................................ 10.2.9 Timer Synchro Register (TSYR).......................................................................... 10.2.10 Module Stop Control Register A (MSTPCRA) ................................................... Interface to Bus Master...................................................................................................... 10.3.1 16-Bit Registers.................................................................................................... 10.3.2 8-Bit Registers...................................................................................................... Operation ........................................................................................................................... 10.4.1 Overview .............................................................................................................. 10.4.2 Basic Functions .................................................................................................... 10.4.3 Synchronous Operation ........................................................................................ 10.4.4 Buffer Operation .................................................................................................. 10.4.5 Cascaded Operation.............................................................................................. 10.4.6 PWM Modes ........................................................................................................ 10.4.7 Phase Counting Mode .......................................................................................... Interrupts............................................................................................................................ 10.5.1 Interrupt Sources and Priorities............................................................................ 10.5.2 DTC Activation .................................................................................................... 10.5.3 A/D Converter Activation .................................................................................... Operation Timing .............................................................................................................. 10.6.1 Input/Output Timing............................................................................................. 10.6.2 Interrupt Signal Timing........................................................................................ Usage Notes ....................................................................................................................... 283 284 286 288 288 293 295 308 311 315 316 317 318 319 320 320 320 322 322 323 329 331 335 337 342 349 349 351 351 352 352 356 360 Section 11 Programmable Pulse Generator (PPG) .................................................... 371 11.1 Overview............................................................................................................................ 11.1.1 Features ................................................................................................................ 11.1.2 Block Diagram...................................................................................................... 11.1.3 Pin Configuration ................................................................................................. 11.1.4 Registers ............................................................................................................... 11.2 Register Descriptions......................................................................................................... 11.2.1 Next Data Enable Registers H and L (NDERH, NDERL)................................... 11.2.2 Output Data Registers H and L (PODRH, PODRL) ............................................ 371 371 372 373 374 375 375 376 vii 11.2.3 Next Data Registers H and L (NDRH, NDRL).................................................... 11.2.4 Notes on NDR Access.......................................................................................... 11.2.5 PPG Output Control Register (PCR).................................................................... 11.2.6 PPG Output Mode Register (PMR)...................................................................... 11.2.7 Port 1 Data Direction Register (P1DDR) ............................................................. 11.2.8 Module Stop Control Register A (MSTPCRA).................................................... 11.3 Operation ........................................................................................................................... 11.3.1 Overview .............................................................................................................. 11.3.2 Output Timing ...................................................................................................... 11.3.3 Normal Pulse Output............................................................................................ 11.3.4 Non-Overlapping Pulse Output ............................................................................ 11.3.5 Inverted Pulse Output ........................................................................................... 11.3.6 Pulse Output Triggered by Input Capture ............................................................ 11.4 Usage Notes ....................................................................................................................... 377 377 379 381 384 384 385 385 386 387 389 392 393 394 Section 12 Watchdog Timer ............................................................................................. 397 12.1 Overview............................................................................................................................ 12.1.1 Features ................................................................................................................ 12.1.2 Block Diagram...................................................................................................... 12.1.3 Pin Configuration ................................................................................................. 12.1.4 Register Configuration ......................................................................................... 12.2 Register Descriptions......................................................................................................... 12.2.1 Timer Counter (TCNT) ........................................................................................ 12.2.2 Timer Control/Status Register (TCSR) ................................................................ 12.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 12.2.4 Pin Function Control Register (PFCR) ................................................................ 12.2.5 Notes on Register Access ..................................................................................... 12.3 Operation ........................................................................................................................... 12.3.1 Watchdog Timer Operation.................................................................................. 12.3.2 Interval Timer Operation...................................................................................... 12.3.3 Timing of Setting Overflow Flag (OVF).............................................................. 12.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF) ......................... 12.4 Interrupts............................................................................................................................ 12.5 Usage Notes ....................................................................................................................... 12.5.1 Contention between Timer Counter (TCNT) Write and Increment ..................... 12.5.2 Changing Value of PSS and CKS2 to CKS0........................................................ 12.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 12.5.4 System Reset by WDTOVF Signal...................................................................... 12.5.5 Internal Reset in Watchdog Timer Mode ............................................................. 12.5.6 OVF Flag Clearing in Interval Timer Mode ........................................................ 397 397 398 400 400 401 401 401 406 407 408 410 410 412 412 413 414 414 414 415 415 415 415 416 Section 13 Serial Communication Interface (SCI) .................................................... 417 13.1 Overview ........................................................................................................................... 417 viii 13.2 13.3 13.4 13.5 13.1.1 Features ................................................................................................................ 13.1.2 Block Diagram...................................................................................................... 13.1.3 Pin Configuration ................................................................................................. 13.1.4 Register Configuration ......................................................................................... Register Descriptions......................................................................................................... 13.2.1 Receive Shift Register (RSR)............................................................................... 13.2.2 Receive Data Register (RDR) .............................................................................. 13.2.3 Transmit Shift Register (TSR).............................................................................. 13.2.4 Transmit Data Register (TDR) ............................................................................. 13.2.5 Serial Mode Register (SMR)................................................................................ 13.2.6 Serial Control Register (SCR).............................................................................. 13.2.7 Serial Status Register (SSR)................................................................................. 13.2.8 Bit Rate Register (BRR)....................................................................................... 13.2.9 Smart Card Mode Register (SCMR) .................................................................... 13.2.10 Module Stop Control Register B (MSTPCRB).................................................... Operation ........................................................................................................................... 13.3.1 Overview .............................................................................................................. 13.3.2 Operation in Asynchronous Mode........................................................................ 13.3.3 Multiprocessor Communication Function............................................................ 13.3.4 Operation in Clocked Synchronous Mode ........................................................... SCI Interrupts .................................................................................................................... Usage Notes ....................................................................................................................... 417 419 420 421 422 422 422 423 423 424 427 431 435 443 444 446 446 448 459 467 475 477 Section 14 Smart Card Interface...................................................................................... 487 14.1 Overview............................................................................................................................ 14.1.1 Features ................................................................................................................ 14.1.2 Block Diagram...................................................................................................... 14.1.3 Pin Configuration ................................................................................................. 14.1.4 Register Configuration ......................................................................................... 14.2 Register Descriptions......................................................................................................... 14.2.1 Smart Card Mode Register (SCMR) .................................................................... 14.2.2 Serial Status Register (SSR)................................................................................. 14.2.3 Serial Mode Register (SMR)................................................................................ 14.2.4 Serial Control Register (SCR).............................................................................. 14.3 Operation ........................................................................................................................... 14.3.1 Overview .............................................................................................................. 14.3.2 Pin Connections.................................................................................................... 14.3.3 Data Format.......................................................................................................... 14.3.4 Register Settings................................................................................................... 14.3.5 Clock .................................................................................................................... 14.3.6 Data Transfer Operations ..................................................................................... 14.3.7 Operation in GSM Mode...................................................................................... 14.3.8 Operation in Block Transfer Mode ...................................................................... 487 487 488 489 490 491 491 493 495 497 498 498 498 500 502 504 506 513 514 ix 14.4 Usage Notes ....................................................................................................................... 515 Section 15 Hitachi Controller Area Network (HCAN) ............................................ 519 15.1 Overview............................................................................................................................ 15.1.1 Features ................................................................................................................ 15.1.2 Block Diagram...................................................................................................... 15.1.3 Pin Configuration ................................................................................................. 15.1.4 Register Configuration ......................................................................................... 15.2 Register Descriptions......................................................................................................... 15.2.1 Master Control Register (MCR)........................................................................... 15.2.2 General Status Register (GSR)............................................................................. 15.2.3 Bit Configuration Register (BCR)........................................................................ 15.2.4 Mailbox Configuration Register (MBCR)............................................................ 15.2.5 Transmit Wait Register (TXPR) .......................................................................... 15.2.6 Transmit Wait Cancel Register (TXCR) .............................................................. 15.2.7 Transmit Acknowledge Register (TXACK) ........................................................ 15.2.8 Abort Acknowledge Register (ABACK).............................................................. 15.2.9 Receive Complete Register (RXPR) .................................................................... 15.2.10 Remote Request Register (RFPR)........................................................................ 15.2.11 Interrupt Register (IRR) ....................................................................................... 15.2.12 Mailbox Interrupt Mask Register (MBIMR)........................................................ 15.2.13 Interrupt Mask Register (IMR) ............................................................................ 15.2.14 Receive Error Counter (REC) .............................................................................. 15.2.15 Transmit Error Counter (TEC) ............................................................................. 15.2.16 Unread Message Status Register (UMSR) ........................................................... 15.2.17 Local Acceptance Filter Masks (LAFML, LAFMH) ........................................... 15.2.18 Message Control (MC0 to MC15)........................................................................ 15.2.19 Message Data (MD0 to MD15)............................................................................ 15.2.20 Module Stop Control Register C (MSTPCRC).................................................... 15.3 Operation ........................................................................................................................... 15.3.1 Hardware and Software Resets ............................................................................ 15.3.2 Initialization after Hardware Reset ...................................................................... 15.3.3 Transmit Mode ..................................................................................................... 15.3.4 Receive Mode....................................................................................................... 15.3.5 HCAN Sleep Mode .............................................................................................. 15.3.6 HCAN Halt Mode ................................................................................................ 15.3.7 Interrupt Interface................................................................................................. 15.3.8 DTC Interface....................................................................................................... 15.4 CAN Bus Interface ............................................................................................................ 15.5 Usage Notes ....................................................................................................................... 519 519 520 521 522 524 524 525 527 529 530 531 532 533 534 535 536 540 541 543 544 544 545 547 551 553 554 554 557 561 568 574 576 576 577 578 579 Section 16 A/D Converter ................................................................................................. 581 16.1 Overview............................................................................................................................ 581 x 16.2 16.3 16.4 16.5 16.6 16.1.1 Features ................................................................................................................ 16.1.2 Block Diagram...................................................................................................... 16.1.3 Pin Configuration ................................................................................................. 16.1.4 Register Configuration ......................................................................................... Register Descriptions......................................................................................................... 16.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 16.2.2 A/D Control/Status Register (ADCSR)................................................................ 16.2.3 A/D Control Register (ADCR)............................................................................. 16.2.4 Module Stop Control Register A (MSTPCRA).................................................... Interface to Bus Master...................................................................................................... Operation ........................................................................................................................... 16.4.1 Single Mode (SCAN = 0) ..................................................................................... 16.4.2 Scan Mode (SCAN = 1) ....................................................................................... 16.4.3 Input Sampling and A/D Conversion Time.......................................................... 16.4.4 External Trigger Input Timing ............................................................................. Interrupts............................................................................................................................ Usage Notes ....................................................................................................................... 581 582 583 584 585 585 586 589 590 591 592 592 594 596 597 598 598 Section 17 D/A Converter [Provided in the H8S/2626 Series only] .................... 603 17.1 Overview............................................................................................................................ 17.1.1 Features ................................................................................................................ 17.1.2 Block Diagram...................................................................................................... 17.1.3 Pin Configuration ................................................................................................. 17.1.4 Register Configuration ......................................................................................... 17.2 Register Descriptions......................................................................................................... 17.2.1 D/A Data Registers 2 and 3 (DADR2, DADR3).................................................. 17.2.2 D/A Control Register 23 (DACR23).................................................................... 17.2.3 Module Stop Control Register C (MSTPCRC).................................................... 17.3 Operation ........................................................................................................................... 603 603 604 605 605 606 606 606 608 609 Section 18 RAM ................................................................................................................... 611 18.1 Overview............................................................................................................................ 18.1.1 Block Diagram...................................................................................................... 18.1.2 Register Configuration ......................................................................................... 18.2 Register Descriptions......................................................................................................... 18.2.1 System Control Register (SYSCR) ...................................................................... 18.3 Operation ........................................................................................................................... 18.4 Usage Notes ....................................................................................................................... 611 611 612 612 612 613 613 Section 19 ROM ................................................................................................................... 615 19.1 Features.............................................................................................................................. 615 19.2 Overview............................................................................................................................ 616 19.2.1 Block Diagram...................................................................................................... 616 xi 19.3 19.4 19.5 19.6 19.7 19.8 19.9 19.10 19.11 19.12 19.13 19.14 xii 19.2.2 Mode Transitions.................................................................................................. 19.2.3 On-Board Programming Modes ........................................................................... 19.2.4 Flash Memory Emulation in RAM....................................................................... 19.2.5 Differences between Boot Mode and User Program Mode.................................. 19.2.6 Block Configuration ............................................................................................. Pin Configuration .............................................................................................................. Register Configuration ...................................................................................................... Register Descriptions......................................................................................................... 19.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 19.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 19.5.3 Erase Block Register 1 (EBR1)............................................................................ 19.5.4 Erase Block Register 2 (EBR2)............................................................................ 19.5.5 RAM Emulation Register (RAMER) ................................................................... 19.5.6 Flash Memory Power Control Register (FLPWCR) ............................................ 19.5.7 Serial Control Register X (SCRX) ....................................................................... On-Board Programming Modes ........................................................................................ 19.6.1 Boot Mode............................................................................................................ 19.6.2 User Program Mode ............................................................................................. Flash Memory Programming/Erasing................................................................................ 19.7.1 Program Mode...................................................................................................... 19.7.2 Program-Verify Mode .......................................................................................... 19.7.3 Erase Mode........................................................................................................... 19.7.4 Erase-Verify Mode ............................................................................................... Protection........................................................................................................................... 19.8.1 Hardware Protection............................................................................................. 19.8.2 Software Protection .............................................................................................. 19.8.3 Error Protection .................................................................................................... Flash Memory Emulation in RAM.................................................................................... Interrupt Handling when Programming/Erasing Flash Memory ....................................... Flash Memory Programmer Mode .................................................................................... 19.11.1 Socket Adapter Pin Correspondence Diagram ................................................... 19.11.2 Programmer Mode Operation............................................................................. 19.11.3 Memory Read Mode........................................................................................... 19.11.4 Auto-Program Mode .......................................................................................... 19.11.5 Auto-Erase Mode................................................................................................ 19.11.6 Status Read Mode............................................................................................... 19.11.7 Status Polling...................................................................................................... 19.11.8 Programmer Mode Transition Time................................................................... 19.11.9 Notes on Memory Programming........................................................................ Flash Memory and Power-Down States ............................................................................ 19.12.1 Note on Power-Down States .............................................................................. Flash Memory Programming and Erasing Precautions ..................................................... Note on Switching from F-ZTAT Version to Mask ROM Version .................................. 617 618 620 621 622 622 623 623 623 626 627 627 628 629 630 631 631 636 638 640 641 645 645 647 647 648 649 651 653 653 654 656 657 660 662 664 665 665 666 667 667 668 673 Section 20 Clock Pulse Generator .................................................................................. 675 20.1 Overview............................................................................................................................ 20.1.1 Block Diagram...................................................................................................... 20.1.2 Register Configuration ......................................................................................... 20.2 Register Descriptions......................................................................................................... 20.2.1 System Clock Control Register (SCKCR) ........................................................... 20.2.2 Low-Power Control Register (LPWRCR)............................................................ 20.3 Oscillator............................................................................................................................ 20.3.1 Connecting a Crystal Resonator ........................................................................... 20.3.2 External Clock Input ............................................................................................ 20.4 PLL Circuit........................................................................................................................ 20.5 Medium-Speed Clock Divider........................................................................................... 20.6 Bus Master Clock Selection Circuit .................................................................................. 20.7 Subclock Oscillator (H8S/2626 Series Only).................................................................... 20.8 Subclock Waveform Shaping Circuit (H8S/2626 Series Only) ........................................ 20.9 Note on Crystal Resonator................................................................................................. 675 676 676 677 677 678 679 679 682 684 684 684 685 686 686 Section 21A Power-Down Modes [H8S/2623 Series] ............................................. 687 21A.1 21A.2 Overview ........................................................................................................................ 21A.1.1 Register Configuration ................................................................................... Register Descriptions...................................................................................................... 21A.2.1 Standby Control Register (SBYCR) .............................................................. 21A.2.2 System Clock Control Register (SCKCR) ..................................................... 21A.2.3 Low-Power Control Register (LPWRCR)...................................................... 21A.2.4 Module Stop Control Register (MSTPCR) .................................................... Medium-Speed Mode ..................................................................................................... Sleep Mode..................................................................................................................... 21A.4.1 Sleep Mode..................................................................................................... 21A.4.2 Exiting Sleep Mode........................................................................................ Module Stop Mode ......................................................................................................... 21A.5.1 Module Stop Mode ......................................................................................... 21A.5.2 Usage Notes.................................................................................................... Software Standby Mode ................................................................................................. 21A.6.1 Software Standby Mode ................................................................................. 21A.6.2 Clearing Software Standby Mode .................................................................. 21A.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode ................................................................................................ 21A.6.4 Software Standby Mode Application Example .............................................. 21A.6.5 Usage Notes.................................................................................................... Hardware Standby Mode................................................................................................ 21A.7.1 Hardware Standby Mode................................................................................ 21A.7.2 Hardware Standby Mode Timing ................................................................... o Clock Output Disabling Function................................................................................ 687 690 690 690 692 693 694 695 696 696 696 696 696 698 698 698 698 699 700 701 701 701 702 702 xiii 21A.3 21A.4 21A.5 21A.6 21A.7 21A.8 Section 21B Power-Down Modes [H8S/2626 Series] ............................................. 703 21B.1 21B.2 Overview ........................................................................................................................ 21B.1.1 Register Configuration ................................................................................... Register Descriptions...................................................................................................... 21B.2.1 Standby Control Register (SBYCR) .............................................................. 21B.2.2 System Clock Control Register (SCKCR) ..................................................... 21B.2.3 Low-Power Control Register (LPWRCR)...................................................... 21B.2.4 Timer Control/Status Register (TCSR) .......................................................... 21B.2.5 Module Stop Control Register (MSTPCR) .................................................... Medium-Speed Mode ..................................................................................................... Sleep Mode..................................................................................................................... 21B.4.1 Sleep Mode..................................................................................................... 21B.4.2 Exiting Sleep Mode........................................................................................ Module Stop Mode ......................................................................................................... 21B.5.1 Module Stop Mode ......................................................................................... 21B.5.2 Usage Notes.................................................................................................... Software Standby Mode ................................................................................................. 21B.6.1 Software Standby Mode ................................................................................. 21B.6.2 Clearing Software Standby Mode .................................................................. 21B.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode ................................................................................................ 21B.6.4 Software Standby Mode Application Example .............................................. 21B.6.5 Usage Notes.................................................................................................... Hardware Standby Mode................................................................................................ 21B.7.1 Hardware Standby Mode................................................................................ 21B.7.2 Hardware Standby Mode Timing ................................................................... Watch Mode ................................................................................................................... 21B.8.1 Watch Mode ................................................................................................... 21B.8.2 Exiting Watch Mode ...................................................................................... 21B.8.3 Notes............................................................................................................... Sub-Sleep Mode ............................................................................................................. 21B.9.1 Sub-Sleep Mode ............................................................................................. 21B.9.2 Exiting Sub-Sleep Mode ................................................................................ Sub-Active Mode............................................................................................................ 21B.10.1 Sub-Active Mode............................................................................................ 21B.10.2 Exiting Sub-Active Mode............................................................................... Direct Transitions ........................................................................................................... 21B.11.1 Overview of Direct Transitions...................................................................... o Clock Output Disabling Function................................................................................ Usage Notes.................................................................................................................... 703 707 708 708 710 711 713 715 716 717 717 717 717 717 719 719 719 719 720 721 722 722 722 723 723 723 724 724 725 725 725 726 726 726 727 727 727 728 21B.3 21B.4 21B.5 21B.6 21B.7 21B.8 21B.9 21B.10 21B.11 21B.12 21B.13 Section 22 Electrical Characteristics.............................................................................. 729 22.1 Absolute Maximum Ratings.............................................................................................. 729 xiv 22.2 DC Characteristics ............................................................................................................. 22.3 AC Characteristics ............................................................................................................. 22.3.1 Clock Timing........................................................................................................ 22.3.2 Control Signal Timing.......................................................................................... 22.3.3 Bus Timing ........................................................................................................... 22.3.4 Timing of On-Chip Supporting Modules ............................................................. 22.4 A/D Conversion Characteristics ........................................................................................ 22.5 D/A Conversion Characteristics ........................................................................................ 22.6 Flash Memory Characteristics ........................................................................................... 22.7 Usage Note ........................................................................................................................ 730 733 734 735 737 743 747 748 749 750 Appendix A Instruction Set.............................................................................................. 751 A.1 A.2 A.3 A.4 A.5 A.6 Instruction List................................................................................................................... Instruction Codes ............................................................................................................... Operation Code Map.......................................................................................................... Number of States Required for Instruction Execution ...................................................... Bus States during Instruction Execution............................................................................ Condition Code Modification............................................................................................ 751 776 791 795 806 820 Appendix B Internal I/O Register .................................................................................. 826 B.1 B.2 Address .............................................................................................................................. 826 Functions............................................................................................................................ 841 Appendix C I/O Port Block Diagrams.......................................................................... 991 C.1 C.2 C.3 C.4 C.5 C.6 C.7 C.8 C.9 Port 1 Block Diagrams ...................................................................................................... 991 Port 4 Block Diagram........................................................................................................ 997 Port 9 Block Diagram........................................................................................................ 997 Port A Block Diagrams...................................................................................................... 998 Port B Block Diagram ....................................................................................................... 1003 Port C Block Diagrams...................................................................................................... 1004 Port D Block Diagram ....................................................................................................... 1008 Port E Block Diagram........................................................................................................ 1009 Port F Block Diagrams ...................................................................................................... 1010 Appendix D Pin States ....................................................................................................... 1019 D.1 Port States in Each Mode .................................................................................................. 1019 Appendix E Appendix F Timing of Transition to and Recovery from Hardware Standby Mode.............................................................................................. 1022 Product Code Lineup ................................................................................. 1023 Appendix G Package Dimensions.................................................................................. 1024 xv xvi Section 1 Overview 1.1 Overview The H8S/2626 Series and H8S/2623 Series are series of microcomputers (MCUs) that integrate peripheral functions required for system configuration together with an H8S/2600 CPU employing an original Hitachi architecture. The H8S/2600 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300 and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300, H8/300L, or H8/300H Series. On-chip peripheral functions required for system configuration include a data transfer controller (DTC) bus master, ROM and RAM memory, a16-bit timer-pulse unit (TPU), programmable pulse generator (PPG), watchdog timer (WDT), serial communication interface (SCI), Hitachi controller area network (HCAN), A/D converter, D/A converter (H8S/2626 Series only), and I/O ports. The on-chip ROM is 256-kbyte flash memory (F-ZTATTM)* or 256-, 128-, or 64-kbyte mask ROM. The ROM is connected to the CPU by a 16-bit data bus, enabling both byte and word data to be accessed in one state. Instruction fetching has been speeded up, and processing speed increased. Four operating modes, modes 4 to 7, are provided, and there is a choice of single-chip mode or external expansion mode. The features of the H8S/2626 Series and H8S/2623 Series are shown in table 1-1. Note: * F-ZTAT is a trademark of Hitachi, Ltd. 1 Table 1-1 Item CPU Overview Specifications * General-register machine Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) * High-speed operation suitable for realtime control Maximum operating frequency: 20 MHz High-speed arithmetic operations 8/16/32-bit register-register add/subtract: 50 ns 16 x 16-bit register-register multiply: 200 ns 16 x 16 + 42-bit multiply and accumulate: 200 ns 32 / 16-bit register-register divide: 1000 ns * Instruction set suitable for high-speed operation 69 basic instructions 8/16/32-bit move/arithmetic and logic instructions Unsigned/signed multiply and divide instructions Multiply-and accumulate instruction Powerful bit-manipulation instructions * Two CPU operating modes Normal mode: 64-kbyte address space (Not available in the H8S/2626 Series or H8S/2623 Series) Advanced mode: 16-Mbyte address space Bus controller * * * * * * Address space divided into 8 areas, with bus specifications settable independently for each area Choice of 8-bit or 16-bit access space for each area 2-state or 3-state access space can be designated for each area Number of program wait states can be set for each area Burst ROM directly connectable External bus release function Supports debugging functions by means of PC break interrupts Two break channels PC break controller * * 2 Item Data transfer controller (DTC) Specifications * * * * Can be activated by internal interrupt or software Multiple transfers or multiple types of transfer possible for one activation source Transfer possible in repeat mode, block transfer mode, etc. Request can be sent to CPU for interrupt that activated DTC 6-channel 16-bit timer Pulse input/output processing capability for up to 16 pins Automatic 2-phase encoder count capability Maximum 8-bit pulse output possible with TPU as time base Output trigger selectable in 4-bit groups Non-overlap margin can be set Direct output or inverse output setting Watchdog timer or interval timer selectable Subclock operation possible (one channel only) Watchdog timer or interval timer selectable 16-bit timer-pulse unit (TPU) * * * Programmable pulse generator (PPG) * * * * Watchdog timer * (WDT), 2 channels * (H8S/2626 Series) Watchdog timer * (WDT), 1 channel (H8S/2623 Series) Serial communication interface (SCI), 3 channels (SCI0 to SCI2) Hitachi controller area network (HCAN), 1 channel A/D converter * * * * * * * * * * * * D/A converter (H8S/2626 Series only) * * Asynchronous mode or synchronous mode selectable Multiprocessor communication function Smart card interface function CAN: Ver. 2.0B compliant Buffer size: 15 transmit/receive buffers, one transmit-only buffer Receive message filtering Resolution: 10 bits Input: 16 channels 13.3 s minimum conversion time (at 20 MHz operation) Single or scan mode selectable Sample-and-hold function A/D conversion can be activated by external trigger or timer trigger Resolution: 8 bits Output: 2 channels 3 Item Specifications 51 input/output pins, 17 input-only pins 53 input/output pins, 17 input-only pins Flash memory or masked ROM High-speed static RAM Product Name H8S/2626, H8S/2623 H8S/2625, H8S/2622 H8S/2624, H8S/2621 ROM 256 kbytes 128 kbytes 64 kbytes RAM 12 kbytes 8 kbytes 4 kbytes I/O ports * (H8S/2626 Series) I/O ports * (H8S/2623 Series) Memory * * Interrupt controller * * Seven external interrupt pins (NMI, IRQ0 to IRQ5) Internal interrupt sources H8S/2626: 48 H8S/2623: 47 * Power-down state * * * * * * Operating modes * Eight priority levels settable Medium-speed mode Sleep mode Module stop mode Software standby mode Hardware standby mode Subclock operation (H8S/2626 Series only) Four MCU operating modes External Data Bus CPU Operating Mode Advanced On-Chip ROM Disabled Disabled Enabled Enabled Initial Width 16 bits 8 bits 8 bits -- Max. Width 16 bits 16 bits 16 bits -- Mode 4 5 6 7 Description On-chip ROM disabled expansion mode On-chip ROM disabled expansion mode On-chip ROM enabled expansion mode Single-chip mode 4 Item Clock pulse generator Package Product lineup Specifications * * * Built-in PLL circuit (x1, x2, x4) Input clock frequency: 2 to 20 MHz 100-pin plastic QFP (FP-100B) Model Mask ROM Version HD6432626 HD6432623 HD6432625 HD6432622 HD6432624 HD6432621 F-ZTAT Version HD64F2626 HD64F2623 -- -- ROM/RAM (Bytes) 256 k/12 k 128 k/8 k 64 k/4 k Package FP-100B FP-100B FP-100B 5 1.2 Internal Block Diagram Figures 1-1 and 1-2 show internal block diagrams of the H8S/2623 Series and H8S/2626 Series. PD7/D15 PD6/D14 PD5/D13 PD4/D12 PD3/D11 PD2/D10 PD1/D9 PD0/D8 PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 PVCC1 PVCC2 PVCC3 PVCC4 VCC VCC VSS VSS VSS VSS VSS Port D Port E PF7/o PF6/AS PF5/RD PF4/HWR PF3/LWR/ADTRG/IRQ3 PF2/WAIT/BREQO PF1/BACK PF0/BREQ/IRQ2 PC break controller (2 channels) Port F Peripheral data bus Peripheral address bus MD2 MD1 MD0 EXTAL XTAL PLLVCC PLLCAP PLLVSS STBY RES WDTOVF NMI FWE* Clock pulse generator H8S/2600 CPU Internal data bus Internal address bus PLL PA5 PA4 PA3/A19/SCK2 PA2/A18/RxD2 PA1/A17/TxD2 PA0/A16 PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3/A11/TIOCD3 PB2/A10/TIOCC3 PB1/A9/TIOCB3 PB0/A8/TIOCA3 PC7/A7 PC6/A6 PC5/A5/SCK1/IRQ5 PC4/A4/RxD1 PC3/A3/TxD1 PC2/A2/SCK0/IRQ4 PC1/A1/RxD0 PC0/A0/TxD0 Bus controller Interrupt controller DTC WDT x 1 channel RAM SCI x 3 channels TPU HCAN x 1 channel Port C ROM (Mask ROM, flash memory) Port B Port A PPG A/D converter Port 9 P97/AN15 P96/AN14 P95/AN13 P94/AN12 P93 / AN11 P92 / AN10 P91 / AN9 P90 / AN8 Port 1 Port 4 P17/PO15/TIOCB2/TCLKD P16/PO14/TIOCA2/IRQ1 P15/PO13/TIOCB1/TCLKC P14/PO12/TIOCA1/IRQ0 P13/PO11/TIOCD0/TCLKB/A23 P12/PO10/TIOCC0/TCLKA/A22 P11/PO9/TIOCB0/A21 P10/PO8/TIOCA0/A20 HRxD HTxD Vref AVCC AVSS Notes: * The FWE pin is used only in the flash memory version. Figure 1-1 Internal Block Diagram (H8S/2623 Series) 6 P47/AN7 P46/AN6 P45/AN5 P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0 PD7/D15 PD6/D14 PD5/D13 PD4/D12 PD3/D11 PD2/D10 PD1/D9 PD0/D8 Port D MD2 MD1 MD0 OSC1 OSC2 EXTAL XTAL PLLVCC PLLCAP PLLVSS STBY RES WDTOVF NMI FWE* PF7/o PF6/AS PF5/RD PF4/HWR PF3/LWR/ADTRG/IRQ3 PF2/WAIT/BREQO PF1/BACK PF0/BREQ/IRQ2 PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 PVCC1 PVCC2 PVCC3 PVCC4 VCC VCC VSS VSS VSS VSS VSS Port E Port A Clock pulse generator H8S/2600 CPU Internal address bus PLL Internal data bus PA3/A19/SCK2 PA2/A18/RxD2 PA1/A17/TxD2 PA0/A16 PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3/A11/TIOCD3 PB2/A10/TIOCC3 PB1/A9/TIOCB3 PB0/A8/TIOCA3 PC7/A7 PC6/A6 PC5/A5/SCK1/IRQ5 PC4/A4/RxD1 PC3/A3/TxD1 PC2/A2/SCK0/IRQ4 PC1/A1/RxD0 PC0/A0/TxD0 Bus controller PC break controller (2 channels) Port F WDT x 2 channels RAM SCI x 3 channels TPU HCAN x 1 channel D/A converter Port C ROM (mask ROM or flash memory) Peripheral address bus Interrupt controller DTC Peripheral data bus Port B PPG A/D converter Port 9 P97/AN15/DA3 P96/AN14/DA2 P95/AN13 P94/AN12 P93 / AN11 P92 / AN10 P91 / AN9 P90 / AN8 Port 1 Port 4 P17/PO15/TIOCB2/TCLKD P16/PO14/TIOCA2/IRQ1 P15/PO13/TIOCB1/TCLKC P14/PO12/TIOCA1/IRQ0 P13/PO11/TIOCD0/TCLKB/A23 P12/PO10/TIOCC0/TCLKA/A22 P11/PO9/TIOCB0/A21 P10/PO8/TIOCA0/A20 HRxD HTxD Vref AVCC AVSS Notes: * The FWE pin is provided in the flash memory version only. Figure 1-2 Internal Block Diagram (H8S/2626 Series) P47 / AN7 P46 / AN6 P45 / AN5 P44 / AN4 P43 / AN3 P42 / AN2 P41 / AN1 P40 / AN0 7 1.3 1.3.1 Pin Descriptions Pin Arrangement Figures 1-3 and 1-4 show pin arrangements of the H8S/2623 Series and H8S/2626 Series. PF0/BREQ/IRQ2 PF1/BACK PF2/WAIT/BREQO PF3/LWR/ADTRG/IRQ3 PF4/HWR PF5/PD PF6/AS PF7/o FWE EXTAL VSS XTAL VCC STBY NMI RES PLLVCC PLLCAP PLLVSS MD2 MD1 VSS MD0 PVCC3 PA5 AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6 P47/AN7 P90/AN8 P91/AN9 P92/AN10 P93/AN11 P94/AN12 P95/AN13 P96/AN14 P97/AN15 AVSS VSS WDTOVF PVCC4 P10/PO8/TIOCA0/A20 P11/PO9/TIOCB0/A21 P12/PO10/TIOCC0/TCLKA/A22 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 Top view (FP-100B) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 PA4 PA3/A19/SCK2 PA2/A18/RxD2 PA1/A17/TxD2 PA0/A16 PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3/A11/TIOCD3 PB2/A10/TIOCC3 PVCC2 PB1/A9/TIOCB3 VSS PB0/A8/TIOCA3 PC7/A7 PC6/A6 PC5/A5/SCK1/IRQ5 PC4/A4/RxD1 PC3/A3/TxD1 PC2/A2/SCK0/IRQ4 PC1/A1/RxD0 PC0/A0/TxD0 PD7/D15 PD6/D14 Figure 1-3 Pin Arrangement (FP-100B: Top View) (H8S/2623 Series) 8 P13/PO11/TIOCD0/TCLKB/A23 P14/PO12/TIOCA1/IRQ0 P15/PO13/TIOCB1/TCLKC P16/PO14/TIOCA2/IRQ1 P17/PO15/TIOCB2/TCLKD VCC HTxD VSS HRxD PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 VSS PE5/D5 PVCC1 PE6/D6 PE7/D7 PD0/D8 PD1/D9 PD2/D10 PD3/D11 PD4/D12 PD5/D13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6 P47/AN7 P90/AN8 P91/AN9 P92/AN10 P93/AN11 P94/AN12 P95/AN13 P96/AN14/DA2 P97/AN15/DA3 AVSS VSS WDTOVF PVCC4 P10/PO8/TIOCA0/A20 P11/PO9/TIOCB0/A21 P12/PO10/TIOCC0/TCLKA/A22 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PF0/BREQ/IRQ2 PF1/BACK/BUZZ PF2/WAIT/BREQO PF3/LWR/ADTRG/IRQ3 PF4/HWR PF5/PD PF6/AS PF7/o FWE EXTAL VSS XTAL VCC STBY NMI RES PLLVCC PLLCAP PLLVSS MD2 MD1 VSS MD0 PVCC3 OSC2 Top view (FP-100B) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 OSC1 PA3/A19/SCK2 PA2/A18/RxD2 PA1/A17/TxD2 PA0/A16 PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3/A11/TIOCD3 PB2/A10/TIOCC3 PVCC2 PB1/A9/TIOCB3 VSS PB0/A8/TIOCA3 PC7/A7 PC6/A6 PC5/A5/SCK1/IRQ5 PC4/A4/RxD1 PC3/A3/TxD1 PC2/A2/SCK0/IRQ4 PC1/A1/RxD0 PC0/A0/TxD0 PD7/D15 PD6/D14 Figure 1-4 Pin Arrangement (FP-100B: Top View) (H8S/2626 Series) P13/PO11/TIOCD0/TCLKB/A23 P14/PO12/TIOCA1/IRQ0 P15/PO13/TIOCB1/TCLKC P16/PO14/TIOCA2/IRQ1 P17/PO15/TIOCB2/TCLKD VCC HTxD VSS HRxD PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 VSS PE5/D5 PVCC1 PE6/D6 PE7/D7 PD0/D8 PD1/D9 PD2/D10 PD3/D11 PD4/D12 PD5/D13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 9 1.3.2 Pin Functions in Each Operating Mode Tables 1-2 and 1-3 show the pin functions in each of the operating modes of the H8S/2623 Series and H8S/2626 Series. Table 1-2 Pin No. FP-100B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 10 Mode 4 Mode 5 Pin Functions in Each Operating Mode Pin Name Mode 6 Mode 7 P13/PO11/TIOCD0/ P13/PO11/TIOCD0/ P13/PO11/TIOCD0/ P13/PO11/TIOCD0/ TCLKB/A23 TCLKB/A23 TCLKB/A23 TCLKB P14/PO12/TIOCA1/ P14/PO12/TIOCA1/ P14/PO12/TIOCA1/ P14/PO12/TIOCA1/ IRQ0 IRQ0 IRQ0 IRQ0 P15/PO13/TIOCB1/ P15/PO13/TIOCB1/ P15/PO13/TIOCB1/ P15/PO13/TIOCB1/ TCLKC TCLKC TCLKC TCLKC P16/PO14/TIOCA2/ P16/PO14/TIOCA2/ P16/PO14/TIOCA2/ P16/PO14/TIOCA2/ IRQ1 IRQ1 IRQ1 IRQ1 P17/PO15/TIOCB2/ P17/PO15/TIOCB2/ P17/PO15/TIOCB2/ P17/PO15/TIOCB2/ TCLKD TCLKD TCLKD TCLKD VCC HTxD VSS HRxD PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 VSS PE5/D5 PVCC1 PE6/D6 PE7/D7 D8 D9 D10 D11 D12 VCC HTxD VSS HRxD PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 VSS PE5/D5 PVCC1 PE6/D6 PE7/D7 D8 D9 D10 D11 D12 VCC HTxD VSS HRxD PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 VSS PE5/D5 PVCC1 PE6/D6 PE7/D7 D8 D9 D10 D11 D12 VCC HTxD VSS HRxD PE0 PE1 PE2 PE3 PE4 VSS PE5 PVCC1 PE6 PE7 PD0 PD1 PD2 PD3 PD4 Pin No. FP-100B 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Mode 4 D13 D14 D15 A0 A1 A2 A3 A4 A5 A6 A7 PB0/A8/TIOCA3 VSS PB1/A9/TIOCB3 PVCC2 PB2/A10/TIOCC3 PB3/A11/TIOCD3 PB4/A12/TIOCA4 PB5/A13/TIOCB4 PB6/A14/TIOCA5 PB7/A15/TIOCB5 PA0/A16 PA1/A17/TxD2 PA2/A18/RxD2 PA3/A19/SCK2 PA4 PA5 PVCC3 MD0 VSS MD1 MD2 Mode 5 D13 D14 D15 A0 A1 A2 A3 A4 A5 A6 A7 Pin Name Mode 6 D13 D14 D15 PC0/A0/TxD0 PC1/A1/RxD0 Mode 7 PD5 PD6 PD7 PC0/TxD0 PC1/RxD0 PC2/A2/SCK0/IRQ4 PC2/SCK0/IRQ4 PC3/A3/TxD1 PC4/A4/RxD1 PC3/TxD1 PC4/RxD1 PC5/A5/SCK1/IRQ5 PC5/SCK1/IRQ5 PC6/A6 PC7/A7 PB0/A8/TIOCA3 VSS PB1/A9/TIOCB3 PVCC2 PB2/A10/TIOCC3 PB3/A11/TIOCD3 PB4/A12/TIOCA4 PB5/A13/TIOCB4 PB6/A14/TIOCA5 PB7/A15/TIOCB5 PA0/A16 PA1/A17/TxD2 PA2/A18/RxD2 PA3/A19/SCK2 PA4 PA5 PVCC3 MD0 VSS MD1 MD2 PC6 PC7 PB0/TIOCA3 VSS PB1/TIOCB3 PVCC2 PB2/TIOCC3 PB3/TIOCD3 PB4/TIOCA4 PB5/TIOCB4 PB6/TIOCA5 PB7/TIOCB5 PA0 PA1/TxD2 PA2/RxD2 PA3/SCK2 PA4 PA5 PVCC3 MD0 VSS MD1 MD2 PB0/A8/TIOCA3 VSS PB1/A9/TIOCB3 PVCC2 PB2/A10/TIOCC3 PB3/A11/TIOCD3 PB4/A12/TIOCA4 PB5/A13/TIOCB4 PB6/A14/TIOCA5 PB7/A15/TIOCB5 PA0/A16 PA1/A17/TxD2 PA2/A18/RxD2 PA3/A19/SCK2 PA4 PA5 PVCC3 MD0 VSS MD1 MD2 11 Pin No. FP-100B 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 Mode 4 PLLVSS PLLCAP PLLVCC RES NMI STBY VCC XTAL VSS EXTAL FWE PF7/o AS RD HWR Mode 5 PLLVSS PLLCAP PLLVCC RES NMI STBY VCC XTAL VSS EXTAL FWE PF7/o AS RD HWR Pin Name Mode 6 PLLVSS PLLCAP PLLVCC RES NMI STBY VCC XTAL VSS EXTAL FWE PF7/o AS RD HWR Mode 7 PLLVSS PLLCAP PLLVCC RES NMI STBY VCC XTAL VSS EXTAL FWE PF7/o PF6 PF5 PF4 PF3/LWR/ADTRG/ PF3/LWR/ADTRG/ PF3/LWR/ADTRG/ PF3/ADTRG/ IRQ3 IRQ3 IRQ3 IRQ3 PF2/WAIT/BREQO PF2/WAIT/BREQO PF2/WAIT/BREQO PF2 PF1/BACK PF0/BREQ/IRQ2 AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6 P47/AN7 P90/AN8 P91/AN9 PF1/BACK PF0/BREQ/IIRQ2 AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6 P47/AN7 P90/AN8 P91/AN9 PF1/BACK PF0/BREQ/IIRQ2 AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6 P47/AN7 P90/AN8 P91/AN9 PF1 PF0/IRQ2 AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6 P47/AN7 P90/AN8 P91/AN9 12 Pin No. FP-100B 88 89 90 91 92 93 94 95 96 97 98 99 100 Mode 4 P92/AN10 P93/AN11 P94/AN12 P95/AN13 P96/AN14 P97/AN15 AVSS VSS WDTOVF PVCC4 P10/PO8/TIOCA0/ A20 P11/PO9/TIOCB0/ A21 Mode 5 P92/AN10 P93/AN11 P94/AN12 P95/AN13 P96/AN14 P97/AN15 AVSS VSS WDTOVF PVCC4 Pin Name Mode 6 P92/AN10 P93/AN11 P94/AN12 P95/AN13 P96/AN14 P97/AN15 AVSS VSS WDTOVF PVCC4 P10/PO8/TIOCA0/ A20 P11/PO9/TIOCB0/ A21 Mode 7 P92/AN10 P93/AN11 P94/AN12 P95/AN13 P96/AN14 P97/AN15 AVSS VSS WDTOVF PVCC4 P10/PO8/TIOCA0 P11/PO9/TIOCB0 P10/PO8/TIOCA0/ A20 P11/PO9/TIOCB0/ A21 P12/PO10/TIOCC0/ P12/PO10/TIOCC0/ P12/PO10/TIOCC0/ P12/PO10/TIOCC0/ TCLKA/A22 TCLKA/A22 TCLKA/A22 TCLKA Note: NC pins should be connected to VSS or left open. 13 Table 1-3 Pin No. FP-100B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Pin Functions in Each Operating Mode Pin Name Mode 4 Mode 5 Mode 6 Mode 7 P13/PO11/TIOCD0/ P13/PO11/TIOCD0/ P13/PO11/TIOCD0/ P13/PO11/TIOCD0/ TCLKB/A23 TCLKB/A23 TCLKB/A23 TCLKB P14/PO12/TIOCA1/ P14/PO12/TIOCA1/ P14/PO12/TIOCA1/ P14/PO12/TIOCA1/ IRQ0 IRQ0 IRQ0 IRQ0 P15/PO13/TIOCB1/ P15/PO13/TIOCB1/ P15/PO13/TIOCB1/ P15/PO13/TIOCB1/ TCLKC TCLKC TCLKC TCLKC P16/PO14/TIOCA2/ P16/PO14/TIOCA2/ P16/PO14/TIOCA2/ P16/PO14/TIOCA2/ IRQ1 IRQ1 IRQ1 IRQ1 P17/PO15/TIOCB2/ P17/PO15/TIOCB2/ P17/PO15/TIOCB2/ P17/PO15/TIOCB2/ TCLKD TCLKD TCLKD TCLKD VCC HTxD VSS HRxD PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 VSS PE5/D5 PVCC1 PE6/D6 PE7/D7 D8 D9 D10 D11 D12 VCC HTxD VSS HRxD PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 VSS PE5/D5 PVCC1 PE6/D6 PE7/D7 D8 D9 D10 D11 D12 VCC HTxD VSS HRxD PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 VSS PE5/D5 PVCC1 PE6/D6 PE7/D7 D8 D9 D10 D11 D12 VCC HTxD VSS HRxD PE0 PE1 PE2 PE3 PE4 VSS PE5 PVCC1 PE6 PE7 PD0 PD1 PD2 PD3 PD4 14 Pin No. FP-100B 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Mode 4 D13 D14 D15 A0 A1 A2 A3 A4 A5 A6 A7 PB0/A8/TIOCA3 VSS PB1/A9/TIOCB3 PVCC2 PB2/A10/TIOCC3 PB3/A11/TIOCD3 PB4/A12/TIOCA4 PB5/A13/TIOCB4 PB6/A14/TIOCA5 PB7/A15/TIOCB5 PA0/A16 PA1/A17/TxD2 PA2/A18/RxD2 PA3/A19/SCK2 OSC1 OSC2 PVCC3 MD0 VSS MD1 MD2 Mode 5 D13 D14 D15 A0 A1 A2 A3 A4 A5 A6 A7 Pin Name Mode 6 D13 D14 D15 PC0/A0/TxD0 PC1/A1/RxD0 Mode 7 PD5 PD6 PD7 PC0/TxD0 PC1/RxD0 PC2/A2/SCK0/IRQ4 PC2/SCK0/IRQ4 PC3/A3/TxD1 PC4/A4/RxD1 PC3/TxD1 PC4/RxD1 PC5/A5/SCK1/IRQ5 PC5/SCK1/IRQ5 PC6/A6 PC7/A7 PB0/A8/TIOCA3 VSS PB1/A9/TIOCB3 PVCC2 PB2/A10/TIOCC3 PB3/A11/TIOCD3 PB4/A12/TIOCA4 PB5/A13/TIOCB4 PB6/A14/TIOCA5 PB7/A15/TIOCB5 PA0/A16 PA1/A17/TxD2 PA2/A18/RxD2 PA3/A19/SCK2 OSC1 OSC2 PVCC3 MD0 VSS MD1 MD2 PC6 PC7 PB0/TIOCA3 VSS PB1/TIOCB3 PVCC2 PB2/TIOCC3 PB3/TIOCD3 PB4/TIOCA4 PB5/TIOCB4 PB6/TIOCA5 PB7/TIOCB5 PA0 PA1/TxD2 PA2/RxD2 PA3/SCK2 OSC1 OSC2 PVCC3 MD0 VSS MD1 MD2 PB0/A8/TIOCA3 VSS PB1/A9/TIOCB3 PVCC2 PB2/A10/TIOCC3 PB3/A11/TIOCD3 PB4/A12/TIOCA4 PB5/A13/TIOCB4 PB6/A14/TIOCA5 PB7/A15/TIOCB5 PA0/A16 PA1/A17/TxD2 PA2/A18/RxD2 PA3/A19/SCK2 OSC1 OSC2 PVCC3 MD0 VSS MD1 MD2 15 Pin No. FP-100B 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 Mode 4 PLLVSS PLLCAP PLLVCC RES NMI STBY VCC XTAL VSS EXTAL FWE PF7/o AS RD HWR PF3/LWR/ADTRG/ IRQ3 PF2/WAIT/BREQO PF1/BACK/BUZZ PF0/BREQ/IRQ2 AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6 P47/AN7 P90/AN8 P91/AN9 Mode 5 PLLVSS PLLCAP PLLVCC RES NMI STBY VCC XTAL VSS EXTAL FWE PF7/o AS RD HWR Pin Name Mode 6 PLLVSS PLLCAP PLLVCC RES NMI STBY VCC XTAL VSS EXTAL FWE PF7/o AS RD HWR PF3/LWR/ADTRG/ IRQ3 PF2/WAIT/BREQO PF1/BACK/BUZZ PF0/BREQ/IIRQ2 AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6 P47/AN7 P90/AN8 P91/AN9 Mode 7 PLLVSS PLLCAP PLLVCC RES NMI STBY VCC XTAL VSS EXTAL FWE PF7/o PF6 PF5 PF4 PF3/ADTRG/ IRQ3 PF2 PF1/BUZZ PF0/IRQ2 AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6 P47/AN7 P90/AN8 P91/AN9 PF3/LWR/ADTRG/ IRQ3 PF2/WAIT/BREQO PF1/BACK/BUZZ PF0/BREQ/IIRQ2 AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6 P47/AN7 P90/AN8 P91/AN9 16 Pin No. FP-100B 88 89 90 91 92 93 94 95 96 97 98 99 100 Mode 4 P92/AN10 P93/AN11 P94/AN12 P95/AN13 P96/AN14/DA2 P97/AN15/DA3 AVSS VSS WDTOVF PVCC4 P10/PO8/TIOCA0/ A20 P11/PO9/TIOCB0/ A21 Mode 5 P92/AN10 P93/AN11 P94/AN12 P95/AN13 P96/AN14/DA2 P97/AN15/DA3 AVSS VSS WDTOVF PVCC4 Pin Name Mode 6 P92/AN10 P93/AN11 P94/AN12 P95/AN13 P96/AN14/DA2 P97/AN15/DA3 AVSS VSS WDTOVF PVCC4 P10/PO8/TIOCA0/ A20 P11/PO9/TIOCB0/ A21 Mode 7 P92/AN10 P93/AN11 P94/AN12 P95/AN13 P96/AN14/DA2 P97/AN15/DA3 AVSS VSS WDTOVF PVCC4 P10/PO8/TIOCA0 P11/PO9/TIOCB0 P10/PO8/TIOCA0/ A20 P11/PO9/TIOCB0/ A21 P12/PO10/TIOCC0/ P12/PO10/TIOCC0/ P12/PO10/TIOCC0/ P12/PO10/TIOCC0/ TCLKA/A22 TCLKA/A22 TCLKA/A22 TCLKA Note: NC pins should be connected to VSS or left open. 17 1.3.3 Pin Functions Table 1-4 summarizes the pin functions. Table 1-4 Type Power supply Pin Functions Symbol VCC I/O Input Pin Name Power supply Function For connection to the power supply. Connect all V CC pins to the system power supply. PVCC1 PVCC2 PVCC3 PVCC4 VSS Input Input Input Input Input Port power supply Port power supply pins. Connect all Port power supply these pins to the same power supply. Port power supply Port power supply Ground For connection to the power supply (0 V). Connect all VSS pins to the system power supply (0 V). Clock PLLVCC PLLVSS PLLCAP XTAL Input Input Input Input PLL power supply On-chip PLL oscillator power supply PLL ground PLL capacitance Crystal On-chip PLL oscillator ground On-chip PLL oscillator external capacitance pin For connection to a crystal resonator. For examples of crystal resonator connection and external clock input, see section 20, Clock Pulse Generator. For connection to a crystal resonator. For examples of crystal resonator connection and external clock input, see section 20, Clock Pulse Generator. For connection to a recommended 32.768 kHz resonator. For examples of crystal resonator connection, see section 20, Clock Pulse Generator. For connection to a recommended 32.768 kHz resonator. For examples of crystal resonator connection, see section 20, Clock Pulse Generator. Supplies the system clock to external devices. EXTAL Input External clock OSC1* 1 Input Subclock OSC2* 1 Input Subclock o Output System clock 18 Type Operating mode control Symbol MD2 to MD0 I/O Input Pin Name Mode pins Function These pins set the operating mode. The relation between the settings of pins MD2 to MD0 and the operating mode is shown below. Inputs at these pins should not be changed during operation. MD2 0 MD1 0 MD0 0 1 1 0 1 1 0 0 1 1 0 1 Operating Mode -- -- -- -- Mode 4 Mode 5 Mode 6 Mode 7 System control RES STBY BREQ BREQO Input Input Input Output Reset input Standby Bus request Bus request output When this pin is driven low, the chip is reset. When this pin is driven low, a transition is made to hardware standby mode. Used by an external bus master to issue a bus request to the chip. External bus request signal used when an internal bus master accesses external space in the external busreleased state. Indicates that the bus has been released to an external bus master. BACK FWE Interrupts NMI Output Input Input Bus request acknowledge Flash write enable Pin for use by flash memory Nonmaskable interrupt Interrupt request 5 to 0 Address bus Requests a nonmaskable interrupt. If this pin is not used, it should be fixed high. These pins request a maskable interrupt. These pins output address signals. IRQ5 to IRQ0 Address bus A23 to A0 Input Output 19 Type Data bus Bus control Symbol D15 to D0 AS RD HWR I/O Input/ output Output Output Output Pin Name Data bus Address strobe Read High write Function Bidirectional data bus Goes low to indicate valid address output on the address bus. Goes low to indicate reading from the external address space. Strobe signal indicating writing to the external address space; indicates valid data on the upper data bus (D15 to D8). Strobe signal indicating writing to the external address space; indicates valid data on the lower data bus (D7 to D0). Requests insertion of wait states in bus cycles during access to 3-state external address space. These pins input an external clock. LWR Output Low write WAIT Input Wait 16-bit timerpulse unit (TPU) TCLKD to TCLKA TIOCA0, TIOCB0, TIOCC0, TIOCD0 TIOCA1, TIOCB1 TIOCA2, TIOCB2 TIOCA3, TIOCB3, TIOCC3, TIOCD3 TIOCA4, TIOCB4 TIOCA5, TIOCB5 Input Clock input D to A Input capture/ output compare match A0 to D0 Input capture/ output compare match A1 and B1 Input capture/ output compare match A2 and B2 Input capture/ output compare match A3 to D3 Input capture/ output compare match A4 and B4 Input capture/ output compare match A5 and B5 Input/ output The TGR0A to TGR0D input capture input/output compare output/PWM output pins The TGR1A and TGR1B input capture input/output compare output/PWM output pins The TGR2A and TGR2B input capture input/output compare output/PWM output pins The TGR3A to TGR3D input capture input/output compare output/PWM output pins The TGR4A and TGR4B input capture input/output compare output/PWM output pins The TGR5A and TGR5B input capture input/output compare output/PWM output pins Input/ output Input/ output Input/ output Input/ output Input/ output 20 Type Symbol I/O Output Pin Name Pulse output 15 to 8 Function Pulse output pins Programmable PO15 to PO8 pulse generator (PPG) Watchdog timer (WDT) Serial communication interface (SCI)/ smart card interface WDTOVF TxD2, TxD1, TxD0 RxD2, RxD1, RxD0 SCK2, SCK1, SCK0 Hitachi HTxD controller area network HRxD (HCAN) A/D converter AN15 to AN0 ADTRG Output Output Watchdog timer overflow Transmit data The counter overflow signal output pin in watchdog timer mode Data output pins Input Receive data Data input pins Input/ output Output Input Input Input Serial clock Clock input/output pins HCAN transmit data HCAN receive data Analog 15 to 0 A/D conversion external trigger input Analog output Analog power supply The CAN bus transmission pin The CAN bus reception pin Analog input pins Pin for input of an external trigger to start A/D conversion D/A converter analog output pins The power supply pin for the A/D and D/A converters. When the A/D and D/A converters are not used, connect this pin to the system power supply (+5 V). The ground pin and reference voltage for the A/D and D/A converters. Connect this pin to the system power supply (0 V). The reference voltage input pin for the A/D and D/A converters. When the A/D and D/A converters are not used, connect this pin to the system power supply (+5 V). D/A converter pin DA3, DA2 Output Input A/D converter/ AVCC D/A converter AVSS Input Analog ground Vref Input Analog reference power supply 21 Type I/O ports Symbol P17 to P10 P47 to P40 P97 to P90 PA5 to PA0* 2 PB7 to PB0 PC7 to PC0 PD7 to PD0 PE7 to PE0 PF7 to PF0 I/O Input/ output Input Input Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Pin Name Port 1 Function Eight input/output pins. Input or output can be selected for each pin in the port 1 data direction register (P1DDR). Eight input pins Eight input pins Six input/output pins. Input or output can be selected for each pin in the port A data direction register (PADDR). Eight input/output pins. Input or output can be selected for each pin in the port B data direction register (PBDDR). Eight input/output pins. Input or output can be selected for each pin in the port C data direction register (PCDDR). Eight input/output pins. Input or output can be selected for each pin in the port D data direction register (PDDDR). Eight input/output pins. Input or output can be selected for each pin in the port E data direction register (PEDDR). Eight input/output pins. Input or output can be selected for each pin in the port F data direction register (PFDDR). Port 4 Port 9 Port A Port B Port C Port D Port E Port F Notes: *1 Applies to the H8S/2626 Series only. *2 PA3 to PA0 in the H8S/2626 Series. 22 Section 2 CPU 2.1 Overview The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is ideal for realtime control. 2.1.1 Features The H8S/2600 CPU has the following features. * Upward-compatible with H8/300 and H8/300H CPUs Can execute H8/300 and H8/300H object programs * General-register architecture Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) * Sixty-nine basic instructions 8/16/32-bit arithmetic and logic instructions Multiply and divide instructions Powerful bit-manipulation instructions Multiply-and-accumulate instruction * Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @-ERn] Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8,PC) or @(d:16,PC)] Memory indirect [@@aa:8] * 16-Mbyte address space Program: 16 Mbytes Data: 16 Mbytes (4 Gbytes architecturally) 23 * High-speed operation All frequently-used instructions execute in one or two states Maximum clock rate : 20 MHz 8/16/32-bit register-register add/subtract : 50 ns 8 x 8-bit register-register multiply : 150 ns 16 / 8-bit register-register divide : 600 ns 16 x 16-bit register-register multiply : 200 ns 32 / 16-bit register-register divide : 1000 ns * Two CPU operating modes Normal mode* Advanced mode Note: * Not available in the H8S/2626 Series or H8S/2623 Series. * Power-down state Transition to power-down state by SLEEP instruction CPU clock speed selection 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below. * Register configuration The MAC register is supported only by the H8S/2600 CPU. * Basic instructions The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the H8S/2600 CPU. * Number of execution states The number of execution states of the MULXU and MULXS instructions is different in each CPU. Execution States Instruction MULXU Mnemonic MULXU.B Rs, Rd MULXU.W Rs, ERd MULXS MULXS.B Rs, Rd MULXS.W Rs, ERd H8S/2600 3 4 4 5 H8S/2000 12 20 13 21 24 In addition, there are differences in address space, CCR and EXR register functions, power-down modes, etc., depending on the model. 2.1.3 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements. * More general registers and control registers Eight 16-bit expanded registers, and one 8-bit and two 32-bit control registers, have been added. * Expanded address space Normal mode* supports the same 64-kbyte address space as the H8/300 CPU. Advanced mode supports a maximum 16-Mbyte address space. Note: * Not available in the H8S/2626 Series or H8S/2623 Series. * Enhanced addressing The addressing modes have been enhanced to make effective use of the 16-Mbyte address space. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Signed multiply and divide instructions have been added. A multiply-and-accumulate instruction has been added. Two-bit shift instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions execute twice as fast. 2.1.4 Differences from H8/300H CPU In comparison to the H8/300H CPU, the H8S/2600 CPU has the following enhancements. * Additional control register One 8-bit and two 32-bit control registers have been added. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. A multiply-and-accumulate instruction has been added. 25 Two-bit shift instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions execute twice as fast. 2.2 CPU Operating Modes The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode* supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space (architecturally a maximum 16-Mbyte program area and a maximum of 4 Gbytes for program and data areas combined). The mode is selected by the mode pins of the microcontroller. Note: * Not available in the H8S/2626 Series or H8S/2623 Series. Maximum 64 kbytes, program and data areas combined Normal mode* CPU operating modes Advanced mode Maximum 16-Mbytes for program and data areas combined Note: * Not available in the H8S/2626 Series or H8S/2623 Series. Figure 2-1 CPU Operating Modes (1) Normal Mode (Not Available in the H8S/2626 Series or H8S/2623 Series) The exception vector table and stack have the same structure as in the H8/300 CPU. Address Space: A maximum address space of 64 kbytes can be accessed. Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When En is used as a 16-bit register it can contain any value, even when the corresponding general register (Rn) is used as an address register. If the general register is referenced in the register indirect addressing mode with pre-decrement (@-Rn) or post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding extended register (En) will be affected. 26 Instruction Set: All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid. Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits (figure 2-2). The exception vector table differs depending on the microcontroller. For details of the exception vector table, see section 4, Exception Handling. H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Reset exception vector Manual reset exception vector* (Reserved for system use) Exception vector table Exception vector 1 Exception vector 2 Note: * Not available in the H8S/2626 Series or H8S/2623 Series. Figure 2-2 Exception Vector Table (Normal Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In normal mode the operand is a 16-bit word operand, providing a 16bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note that this area is also used for the exception vector table. 27 Stack Structure: When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2-3. When EXR is invalid, it is not pushed onto the stack. For details, see section 4, Exception Handling. SP PC (16 bits) SP *2 (SP ) EXR*1 Reserved*1 *3 CCR CCR*3 PC (16 bits) (a) Subroutine Branch (b) Exception Handling Notes: *1 When EXR is not used it is not stored on the stack. *2 SP when EXR is not used. *3 Ignored when returning. Figure 2-3 Stack Structure in Normal Mode (2) Advanced Mode Address Space: Linear access is provided to a 16-Mbyte maximum address space (architecturally a maximum 16-Mbyte program area and a maximum 4-Gbyte data area, with a maximum of 4 Gbytes for program and data areas combined). Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. Instruction Set: All instructions and addressing modes can be used. 28 Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2-4). For details of the exception vector table, see section 4, Exception Handling. H'00000000 Reserved Reset exception vector H'00000003 H'00000004 Reserved Manual reset exception vector* H'00000007 H'00000008 Exception vector table H'0000000B H'0000000C (Reserved for system use) H'00000010 Reserved Exception vector 1 Note: * Not available in the H8S/2626 Series or H8S/2623 Series. Figure 2-4 Exception Vector Table (Advanced Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the first part of this range is also the exception vector table. 29 Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2-5. When EXR is invalid, it is not pushed onto the stack. For details, see section 4, Exception Handling. SP SP Reserved PC (24 bits) *2 (SP ) EXR*1 Reserved*1 *3 CCR PC (24 bits) (a) Subroutine Branch (b) Exception Handling Notes: *1 When EXR is not used it is not stored on the stack. *2 SP when EXR is not used. *3 Ignored when returning. Figure 2-5 Stack Structure in Advanced Mode 30 2.3 Address Space Figure 2-6 shows a memory map of the H8S/2600 CPU. The H8S/2600 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. H'0000 H'00000000 H'FFFF Program area H'00FFFFFF Cannot be used by the H8S/2626 Series or H8S/2623 Series H'FFFFFFFF (a) Normal Mode* (b) Advanced Mode Data area Note: * Not available in the H8S/2626 Series or H8S/2623 Series. Figure 2-6 Memory Map 31 2.4 2.4.1 Register Configuration Overview The CPU has the internal registers shown in figure 2-7. There are two types of registers: general registers and control registers. General Registers (Rn) and Extended Registers (En) 15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 (SP) Control Registers (CR) 23 PC 76543210 EXR T -- -- -- -- I2 I1 I0 76543210 CCR I UI H U N Z V C 63 MAC 31 Legend SP: PC: EXR: T: I2 to I0: CCR: I: UI: Sign extension MACL 0 41 MACH 32 0 E0 E1 E2 E3 E4 E5 E6 E7 07 R0H R1H R2H R3H R4H R5H R6H R7H 07 R0L R1L R2L R3L R4L R5L R6L R7L 0 Stack pointer Program counter Extended control register Trace bit Interrupt mask bits Condition-code register Interrupt mask bit User bit or interrupt mask bit* H: U: N: Z: V: C: MAC: Half-carry flag User bit Negative flag Zero flag Overflow flag Carry flag Multiply-accumulate register Note: * Cannot be used as an interrupt mask bit in the H8S/2626 Series or H8S/2623 Series. Figure 2-7 CPU Registers 32 2.4.2 General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers. Figure 2-8 illustrates the usage of the general registers. The usage of each register can be selected independently. * Address registers * 32-bit registers * 16-bit registers E registers (extended registers) (E0 to E7) * 8-bit registers ER registers (ER0 to ER7) R registers (R0 to R7) RH registers (R0H to R7H) RL registers (R0L to R7L) Figure 2-8 Usage of General Registers 33 General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2-9 shows the stack. Free area SP (ER7) Stack area Figure 2-9 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR), 8-bit condition-code register (CCR), and 64-bit multiply-accumulate register (MAC). (1) Program Counter (PC): This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0.) (2) Extended Control Register (EXR): This 8-bit register contains the trace bit (T) and three interrupt mask bits (I2 to I0). Bit 7--Trace Bit (T): Selects trace mode. When this bit is cleared to 0, instructions are executed in sequence. When this bit is set to 1, a trace exception is generated each time an instruction is executed. Bits 6 to 3--Reserved: They are always read as 1. 34 Bits 2 to 0--Interrupt Mask Bits (I2 to I0): These bits designate the interrupt mask level (0 to 7). For details, refer to section 5, Interrupt Controller. Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC instructions. All interrupts, including NMI, are disabled for three states after one of these instructions is executed, except for STC. (3) Condition-Code Register (CCR): This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Bit 7--Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. (NMI is accepted regardless of the I bit setting.) The I bit is set to 1 by hardware at the start of an exceptionhandling sequence. For details, refer to section 5, Interrupt Controller. Bit 6--User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask bit. For details, refer to section 5, Interrupt Controller. Bit 5--Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. Bit 4--User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. Bit 3--Negative Flag (N): Stores the value of the most significant bit (sign bit) of data. Bit 2--Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. Bit 1--Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0--Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: * Add instructions, to indicate a carry * Subtract instructions, to indicate a borrow * Shift and rotate instructions, to store the value shifted out of the end bit The carry flag is also used as a bit accumulator by bit manipulation instructions. 35 Some instructions leave some or all of the flag bits unchanged. For the action of each instruction on the flag bits, refer to Appendix A.1, List of Instructions. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. (4) Multiply-Accumulate Register (MAC): This 64-bit register stores the results of multiplyand-accumulate operations. It consists of two 32-bit registers denoted MACH and MACL. The lower 10 bits of MACH are valid; the upper bits are a sign extension. 2.4.4 Initial Register Values Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized. The stack pointer should therefore be initialized by an MOV.L instruction executed immediately after a reset. 36 2.5 Data Formats The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats Figure 2-10 shows the data formats in general registers. Data Type Register Number Data Format 1-bit data RnH 7 0 76543210 Don't care 1-bit data RnL Don't care 7 0 76543210 4-bit BCD data RnH 7 Upper 43 Lower 0 Don't care 4-bit BCD data RnL Don't care 7 Upper 43 Lower 0 Byte data RnH 7 MSB 0 Don't care LSB 7 Don't care Byte data RnL 0 LSB MSB Figure 2-10 General Register Data Formats 37 Data Type Register Number Data Format Word data Rn 15 MSB 0 LSB Word data 15 MSB Longword data 31 MSB En 0 LSB ERn 16 15 En Rn 0 LSB Legend ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2-10 General Register Data Formats (cont) 38 2.5.2 Memory Data Formats Figure 2-11 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches. Data Type Address 7 1-bit data Address L 7 6 5 4 3 2 1 0 0 Data Format Byte data Address L MSB LSB Word data Address 2M MSB Address 2M + 1 LSB Longword data Address 2N MSB Address 2N + 1 Address 2N + 2 Address 2N + 3 LSB Figure 2-11 Memory Data Formats When ER7 is used as an address register to access the stack, the operand size should be word size or longword size. 39 2.6 2.6.1 Instruction Set Overview The H8S/2600 CPU has 69 types of instructions. The instructions are classified by function in table 2-1. Table 2-1 Function Data transfer Instruction Classification Instructions MOV POP* , PUSH* LDM, STM MOVFPE* , MOVTPE* 3 3 1 1 Size BWL WL L B BWL B BWL L BW WL B -- BWL Types 5 Arithmetic operations ADD, SUB, CMP, NEG ADDX, SUBX, DAA, DAS INC, DEC ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS EXTU, EXTS TAS* 4 23 MAC, LDMAC, STMAC, CLRMAC Logic operations Shift Bit manipulation Branch System control AND, OR, XOR, NOT 4 8 14 5 9 1 SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BWL BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR Bcc* 2, JMP, BSR, JSR, RTS B -- TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP -- -- Block data transfer EEPMOV Total: 69 Notes: B-byte size; W-word size; L-longword size. *1 POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP. *2 Bcc is the general name for conditional branch instructions. *3 Not available in the H8S/2626 Series or H8S/2623 Series. *4 Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. 40 2.6.2 Addressing Modes Table 2-2 Function #xx Instruction Rn @ERn @(d:16,ERn) @(d:32,ERn) @-ERn/@ERn+ @aa:8 @aa:16 @aa:24 @aa:32 @(d:8,PC) @(d:16,PC) @@aa:8 Data transfer -- -- -- BWL BWL B L BWL B BW BW BWL WL -- -- -- L -- -- -- -- -- -- -- -- -- -- -- -- -- -- B -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- L -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- WL MOV BWL BWL BWL BWL BWL BWL B BWL -- BWL -- -- -- -- POP, PUSH -- LDM, STM -- MOVEPE*1, MOVTPE*1 -- Arithmetic operations ADD, CMP BWL SUB WL ADDX, SUBX B ADDS, SUBS -- INC, DEC -- DAA, DAS -- Instructions and Addressing Modes -- MULXU, DIVXU MULXS, DIVXS -- NEG -- EXTU, EXTS -- TAS*2 -- MAC -- CLRMAC -- Combinations of Instructions and Addressing Modes Table 2-2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU can use. LDMAC, STMAC -- -- 41 #xx Rn @ERn @(d:16,ERn) @(d:32,ERn) @-ERn/@ERn+ @aa:8 @aa:16 @aa:24 @aa:32 @(d:8,PC) @(d:16,PC) @@aa:8 Logic operations AND, OR, XOR NOT -- -- -- -- -- -- -- -- B -- B -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B W W W W -- -- -- -- B W W W W -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- W W -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B B -- -- -- B B -- B -- -- -- -- -- -- W W -- -- -- -- -- -- -- -- -- -- -- -- -- BWL -- -- -- -- -- -- -- -- -- BWL -- -- -- -- -- -- -- -- -- -- -- BWL BWL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Shift Bcc, BSR JMP, JSR RTS TRAPA RTE SLEEP LDC STC ANDC, ORC, XORC NOP Bit manipulation Branch System control -- -- -- Block data transfer BW Legend B: Byte W: Word L: Longword Notes: *1 Not available in the H8S/2626 Series or H8S/2623 Series. *2 Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. -- 42 Addressing Modes Instruction Function 2.6.3 Table of Instructions Classified by Function Table 2-3 summarizes the instructions in each functional category. The notation used in table 2-3 is defined below. Operation Notation Rd Rs Rn ERn MAC (EAd) (EAs) EXR CCR N Z V C PC SP #IMM disp + - x / :8/:16/:24/:32 General register (destination)* General register (source)* General register* General register (32-bit register) Multiply-accumulate register (32-bit register) Destination operand Source operand Extended control register Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical exclusive OR Move NOT (logical complement) 8-, 16-, 24-, or 32-bit length Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). 43 Table 2-3 Type Data transfer Instructions Classified by Function Instruction MOV Size* 1 B/W/L Function (EAs) Rd, Rs (Ead) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. Cannot be used in the H8S/2626 Series or H8S/2623 Series. Cannot be used in the H8S/2626 Series or H8S/2623 Series. @SP+ Rn Pops a register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn. Rn @-SP Pushes a register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP. @SP+ Rn (register list) Pops two or more general registers from the stack. Rn (register list) @-SP Pushes two or more general registers onto the stack. MOVFPE MOVTPE POP B B W/L PUSH W/L LDM STM L L 44 Type Arithmetic operations Instruction ADD SUB Size* 1 B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.) Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry or borrow on byte data in two general registers, or on immediate data and data in a general register. Rd 1 Rd, Rd 2 Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) Rd 1 Rd, Rd 2 Rd, Rd 4 Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. Rd decimal adjust Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4-bit BCD data. Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. Rd x Rs Rd Performs signed multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16bit remainder. ADDX SUBX B INC DEC B/W/L ADDS SUBS DAA DAS L B MULXU B/W MULXS B/W DIVXU B/W 45 Type Arithmetic operations Instruction DIVXS Size* 1 B/W Function Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16bit remainder. Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result. 0 - Rd Rd Takes the two's complement (arithmetic complement) of data in a general register. Rd (zero extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. Rd (sign extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. @ERd - 0, 1 ( CMP B/W/L NEG B/W/L EXTU W/L EXTS W/L TAS B MAC -- CLRMAC LDMAC STMAC -- L 46 Type Logic operations Instruction AND Size* 1 B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. (Rd) (Rd) Takes the one's complement of general register contents. Rd (shift) Rd Performs an arithmetic shift on general register contents. 1-bit or 2-bit shift is possible. Rd (shift) Rd Performs a logical shift on general register contents. 1-bit or 2-bit shift is possible. Rd (rotate) Rd Rotates general register contents. 1-bit or 2-bit rotation is possible. Rd (rotate) Rd Rotates general register contents through the carry flag. 1-bit or 2-bit rotation is possible. OR B/W/L XOR B/W/L NOT B/W/L Shift operations SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR B/W/L B/W/L B/W/L B/W/L 47 Type Bitmanipulation instructions Instruction BSET Size* 1 B Function 1 ( BCLR B BNOT B BTST B BAND B BIAND B BOR B BIOR B 48 Type Bitmanipulation instructions Instruction BXOR Size* 1 B Function C ( BIXOR B BLD B BILD B BST B BIST B 49 Type Branch instructions Instruction Bcc Size* 1 -- Function Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA(BT) BRN(BF) BHI BLS BCC(BHS) BCS(BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal Condition Always Never CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z(N V) = 0 Z(N V) = 1 JMP BSR JSR RTS -- -- -- -- Branches unconditionally to a specified address. Branches to a subroutine at a specified address. Branches to a subroutine at a specified address. Returns from a subroutine 50 Type Instruction Size* 1 -- -- -- B/W Function Starts trap-instruction exception handling. Returns from an exception-handling routine. Causes a transition to a power-down state. (EAs) CCR, (EAs) EXR Moves the source operand contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. CCR (EAd), EXR (EAd) Transfers CCR or EXR contents to a general register or memory. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. CCR #IMM CCR, EXR #IMM EXR Logically ANDs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically ORs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically exclusive-ORs the CCR or EXR contents with immediate data. PC + 2 PC Only increments the program counter. System control TRAPA instructions RTE SLEEP LDC STC B/W ANDC B ORC B XORC B NOP -- 51 Type Block data transfer instruction Instruction EEPMOV.B Size* 1 -- Function if R4L 0 then Repeat @ER5+ @ER6+ R4L-1 R4L Until R4L = 0 else next; if R4 0 then Repeat @ER5+ @ER6+ R4-1 R4 Until R4 = 0 else next; Transfers a data block according to parameters set in general registers R4L or R4, ER5, and ER6. R4L or R4: size of block (bytes) ER5: starting source address ER6: starting destination address Execution of the next instruction begins as soon as the transfer is completed. EEPMOV.W -- Notes: *1 Size refers to the operand size. B: Byte W: Word L: Longword *2 Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. 2.6.4 Basic Instruction Formats The H8S/2626 Series and H8S/2623 Series instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). (1) Operation Field: Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. (2) Register Field: Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. (3) Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. (4) Condition Field: Specifies the branching condition of Bcc instructions. 52 Figure 2-12 shows examples of instruction formats. (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rn rm ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op EA (disp) (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16, etc. rn rm MOV.B @(d:16, Rn), Rm, etc. Figure 2-12 Instruction Formats (Examples) 53 2.7 2.7.1 Addressing Modes and Effective Address Calculation Addressing Mode The CPU supports the eight addressing modes listed in table 2-4. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2-4 No. 1 2 3 4 5 6 7 8 Addressing Modes Symbol Rn @ERn @(d:16,ERn)/@(d:32,ERn) @ERn+ @-ERn @aa:8/@aa:16/@aa:24/@aa:32 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8 Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect (1) Register Direct--Rn: The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. (2) Register Indirect--@ERn: The register field of the instruction code specifies an address register (ERn) which contains the address of the operand on memory. If the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00). (3) Register Indirect with Displacement--@(d:16, ERn) or @(d:32, ERn): A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added. 54 (4) Register Indirect with Post-Increment or Pre-Decrement--@ERn+ or @-ERn: * Register indirect with post-increment--@ERn+ The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or longword transfer instruction, the register value should be even. * Register indirect with pre-decrement--@-ERn The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the result becomes the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or longword transfer instruction, the register value should be even. (5) Absolute Address--@aa:8, @aa:16, @aa:24, or @aa:32: The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute address can access the entire address space. A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed to be 0 (H'00). Table 2-5 indicates the accessible absolute address ranges. Table 2-5 Absolute Address Access Ranges Normal Mode* 8 bits (@aa:8) 16 bits (@aa:16) 32 bits (@aa:32) Program instruction address 24 bits (@aa:24) H'FF00 to H'FFFF H'0000 to H'FFFF Advanced Mode H'FFFF00 to H'FFFFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF H'000000 to H'FFFFFF Absolute Address Data address Note: * Not available in the H8S/2626 Series or H8S/2623 Series. 55 (6) Immediate--#xx:8, #xx:16, or #xx:32: The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. (7) Program-Counter Relative--@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is -126 to +128 bytes (-63 to +64 words) or -32766 to +32768 bytes (-16383 to +16384 words) from the branch instruction. The resulting value should be an even number. (8) Memory Indirect--@@aa:8: This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode* the memory operand is a word operand and the branch address is 16 bits long. In advanced mode the memory operand is a longword operand, the first byte of which is assumed to be all 0 (H'00). Note that the first part of the address range is also the exception vector area. For further details, refer to section 4, Exception Handling. Note: * Not available in the H8S/2626 Series or H8S/2623 Series. 56 Specified by @aa:8 Branch address Specified by @aa:8 Reserved Branch address (a) Normal Mode* Note: * Not available in the H8S/2626 Series or H8S/2623 Series. (b) Advanced Mode Figure 2-13 Branch Address Specification in Memory Indirect Mode If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.2, Memory Data Formats.) 2.7.2 Effective Address Calculation Table 2-6 indicates how effective addresses are calculated in each addressing mode. In normal mode* the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Note: * Cannot be set in the H8S/2626 Series or H8S/2623 Series. 57 58 Effective Address Calculation Effective Address (EA) rn Operand is general register contents. 31 31 Don't care 24 23 General register contents 0 0 31 General register contents 31 disp 31 Sign extension disp 0 24 23 Don't care 0 0 31 General register contents 0 31 24 23 Don't care 0 1, 2, or 4 31 General register contents 31 24 23 Don't care Operand Size Value added Byte Word Longword 1 2 4 1, 2, or 4 0 0 No. Addressing Mode and Instruction Format Table 2-6 1 Register direct (Rn) op rm 2 Register indirect (@ERn) op r 3 Register indirect with displacement @(d:16, ERn) or @(d:32, ERn) Effective Address Calculation op r 4 Register indirect with post-increment or pre-decrement * Register indirect with post-increment @ERn+ op r * Register indirect with pre-decrement @-ERn op r No. Effective Address Calculation Addressing Mode and Instruction Format Effective Address (EA) 5 31 24 23 H'FFFF abs Don't care Absolute address 87 0 @aa:8 op @aa:16 31 op abs Don't care 24 23 16 15 Sign extension 0 @aa:24 abs 31 24 23 Don't care 0 op @aa:32 op abs 31 24 23 Don't care 0 6 op IMM Immediate #xx:8/#xx:16/#xx:32 Operand is immediate data. 59 60 Effective Address Calculation 23 PC contents 0 Effective Address (EA) op 23 Sign extension disp 31 24 23 Don't care No. Addressing Mode and Instruction Format 7 Program-counter relative @(d:8, PC)/@(d:16, PC) disp 0 0 8 Memory indirect @@aa:8 * Normal mode* abs 31 H'000000 87 abs 0 31 24 23 Don't care op 16 15 H'00 0 15 Memory contents 0 * Advanced mode abs 31 H'000000 31 Memory contents 87 abs 0 31 24 23 Don't care op 0 0 Note: * Not available in the H8S/2626 Series or H8S/2623 Series. 2.8 2.8.1 Processing States Overview The CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2-14 shows a diagram of the processing states. Figure 2-15 indicates the state transitions. Reset state The CPU and all on-chip supporting modules have been initialized and are stopped. Exception-handling state A transient state in which the CPU changes the normal processing flow in response to a reset, interrupt, or trap instruction. Processing states Program execution state The CPU executes program instructions in sequence. Bus-released state The external bus has been released in response to a bus request signal from a bus master other than the CPU. Sleep mode Power-down state CPU operation is stopped to conserve power.* Software standby mode Hardware standby mode Note: * The power-down state also includes a medium-speed mode, module stop mode, subactive mode, subsleep mode, and watch mode. Subclock functions (subactive mode, subsleep mode, and watch mode) are not available in the H8S/2623 Series, but are available in the H8S/2626 Series. Figure 2-14 Processing States 61 End of bus request Bus request Program execution state Bus-released state En d o ha f ex nd ce lin pti g on Re qu es tf or ex ce pt ion ha nd lin g s bu t of t es d ues qu En req re s Bu SLEEP instruction with SSBY = 0 Sleep mode Inte pt rru req t ues SLEEP instruction with SSBY = 1 Exception handling state External interrupt request Software standby mode RES= High STBY= High, RES= Low Reset state *1 Hardware standby mode*2 Reset state Power-down state*3 Notes: *1 From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. A transition can also be made to the reset state when the watchdog timer overflows. *2 From any state, a transition to hardware standby mode occurs when STBY goes low. *3 Apart from these states, there are also the watch mode, subactive mode, and the subsleep mode in the H8S/2626 Series. See section 21B, Power-Down Modes [H8S/2626 Series]. Figure 2-15 State Transitions 2.8.2 Reset State When the RES input goes low all current processing stops and the CPU enters the reset state. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high. The reset state can also be entered by a watchdog timer overflow. For details, refer to section 12, Watchdog Timer. 62 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. (1) Types of Exception Handling and Their Priority Exception handling is performed for traces, resets, interrupts, and trap instructions. Table 2-7 indicates the types of exception handling and their priority. Trap instruction exception handling is always accepted, in the program execution state. Exception handling and the stack structure depend on the interrupt control mode set in SYSCR. Table 2-7 Priority High Exception Handling Types and Priority Type of Exception Reset Detection Timing Synchronized with clock Start of Exception Handling Exception handling starts immediately after a low-to-high transition at the RES pin, or when the watchdog timer overflows. When the trace (T) bit is set to 1, the trace starts at the end of the current instruction or current exception-handling sequence When an interrupt is requested, exception handling starts at the end of the current instruction or current exception-handling sequence Exception handling starts when a trap (TRAPA) instruction is executed* 3 Trace End of instruction execution or end of exception-handling sequence* 1 End of instruction execution or end of exception-handling sequence* 2 When TRAPA instruction is executed Interrupt Trap instruction Low Notes: *1 Traces are enabled only in interrupt control mode 2. Trace exception-handling is not executed at the end of the RTE instruction. *2 Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions, or immediately after reset exception handling. *3 Trap instruction exception handling is always accepted, in the program execution state. 63 (2) Reset Exception Handling After the RES pin has gone low and the reset state has been entered, when RES pin goes high again, reset exception handling starts. The CPU enters the reset state when the RES is low. When reset exception handling starts the CPU fetches a start address (vector) from the exception vector table and starts program execution from that address. All interrupts, including NMI, are disabled during reset exception handling and after it ends. (3) Traces Traces are enabled only in interrupt control mode 2. Trace mode is entered when the T bit of EXR is set to 1. When trace mode is established, trace exception handling starts at the end of each instruction. At the end of a trace exception-handling sequence, the T bit of EXR is cleared to 0 and trace mode is cleared. Interrupt masks are not affected. The T bit saved on the stack retains its value of 1, and when the RTE instruction is executed to return from the trace exception-handling routine, trace mode is entered again. Trace exceptionhandling is not executed at the end of the RTE instruction. Trace mode is not entered in interrupt control mode 0, regardless of the state of the T bit. (4) Interrupt Exception Handling and Trap Instruction Exception Handling When interrupt or trap-instruction exception handling begins, the CPU references the stack pointer (ER7) and pushes the program counter and other control registers onto the stack. Next, the CPU alters the settings of the interrupt mask bits in the control registers. Then the CPU fetches a start address (vector) from the exception vector table and program execution starts from that start address. Figure 2-16 shows the stack after exception handling ends. 64 Normal mode*2 SP SP CCR CCR*1 PC (16 bits) EXR Reserved*1 CCR CCR*1 PC (16 bits) (a) Interrupt control mode 0 (b) Interrupt control mode 2 Advanced mode SP SP CCR PC (24 bits) EXR Reserved*1 CCR PC (24 bits) (c) Interrupt control mode 0 (d) Interrupt control mode 2 Notes: *1 Ignored when returning. *2 Not available in the H8S/2626 Series or H8S/2623 Series. Figure 2-16 Stack Structure after Exception Handling (Examples) 65 2.8.4 Program Execution State In this state the CPU executes program instructions in sequence. 2.8.5 Bus-Released State This is a state in which the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts operations. Bus masters other than the CPU are data transfer controller (DTC). For further details, refer to section 7, Bus Controller. 2.8.6 Power-Down State The power-down state includes both modes in which the CPU stops operating and modes in which the CPU does not stop. There are five modes in which the CPU stops operating: sleep mode, software standby mode, hardware standby mode, subsleep mode*, and watch mode*. There are also three other power-down modes: medium-speed mode, module stop mode, and subactive mode*. In medium-speed mode the CPU and other bus masters operate on a medium-speed clock. Module stop mode permits halting of the operation of individual modules, other than the CPU. Subactive mode*, subsleep mode*, and watch mode* are power-down states using subclock input. For details, refer to section 21B, Power-Down Modes [H8S/2626 Series]. Note: * Supported only in the H8S/2626 Series; not available in the H8S/2623 Series. 66 2.9 2.9.1 Basic Timing Overview The H8S/2600 CPU is driven by a system clock, denoted by the symbol o. The period from one rising edge of o to the next is referred to as a "state." The memory cycle or bus cycle consists of one, two, or three states. Different methods are used to access on-chip memory, on-chip supporting modules, and the external address space. 2.9.2 On-Chip Memory (ROM, RAM) On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and word transfer instruction. Figure 2-17 shows the on-chip memory access cycle. Figure 2-18 shows the pin states. Bus cycle T1 o Internal address bus Internal read signal Internal data bus Internal write signal Write access Internal data bus Write data Read data Address Read access Figure 2-17 On-Chip Memory Access Cycle 67 Bus cycle T1 o Address bus AS RD HWR, LWR Data bus Retained High High High High-impedance state Figure 2-18 Pin States during On-Chip Memory Access 68 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2-19 shows the access timing for the on-chip supporting modules. Figure 2-20 shows the pin states. Bus cycle T1 T2 o Internal address bus Address Internal read signal Read access Internal data bus Internal write signal Write access Internal data bus Write data Read data Figure 2-19 On-Chip Supporting Module Access Cycle 69 Bus cycle T1 T2 o Address bus Retained AS RD HWR, LWR High High High Data bus High-impedance state Figure 2-20 Pin States during On-Chip Supporting Module Access Cycle 70 2.9.4 On-Chip HCAN Module Access Timing On-chip HCAN module access is performed in four states. The data bus width is 16 bits. Wait states can be inserted by means of a wait request from the HCAN. On-chip HCAN module access timing is shown in figures 2-21 and 2-22, and the pin states in figure 2-23. Bus cycle T1 o Internal address bus HCAN read signal Read Internal data bus HCAN write signal Write Internal data bus Write data Read data Address T2 T3 T4 Figure 2-21 On-Chip HCAN Module Access Cycle (No Wait State) Bus cycle T1 o Internal address bus HCAN read signal Read Internal data bus HCAN write signal Write Internal data bus Write data Read data Address T2 T3 Tw Tw T4 Figure 2-22 On-Chip HCAN Module Access Cycle (Wait States Inserted) 71 Bus cycle T1 o Address bus AS RD HWR, LWR Data bus Retained High High High High-impedance state T2 T3 T4 Figure 2-23 Pin States in On-Chip HCAN Module Access 2.9.5 External Address Space Access Timing The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to section 7, Bus Controller. 2.10 2.10.1 Usage Note TAS Instruction Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS instruction is not generated by the Hitachi H8S and H8/300 series C/C++ compilers. If the TAS instruction is used as a user-defined intrinsic function, ensure that only register ER0, ER1, ER4, or ER5 is used. 72 Section 3 MCU Operating Modes 3.1 3.1.1 Overview Operating Mode Selection The H8S/2626 Series and H8S/2623 Series have four operating modes (modes 4 to 7). These modes enable selection of the CPU operating mode, enabling/disabling of on-chip ROM, and the initial bus width setting, by setting the mode pins (MD2 to MD0). Table 3-1 lists the MCU operating modes. Table 3-1 MCU Operating Mode Selection External Data Bus On-Chip Initial ROM Width -- -- Max. Width MCU CPU Operating Operating Mode MD2 MD1 MD0 Mode Description 0* 1* 2* 3* 4 5 6 7 1 1 0 1 0 0 0 1 0 1 0 1 0 1 -- -- -- Advanced On-chip ROM disabled, Disabled 16 bits expanded mode 8 bits On-chip ROM enabled, Enabled 8 bits expanded mode Single-chip mode -- 16 bits 16 bits 16 bits Note: * Not available in the H8S/2626 Series or H8S/2623 Series. The CPU's architecture allows for 4 Gbytes of address space, but the H8S/2626 Series and H8S/2623 Series actually access a maximum of 16 Mbytes. Modes 4 to 6 are externally expanded modes that allow access to external memory and peripheral devices. The external expansion modes allow switching between 8-bit and 16-bit bus modes. After program execution starts, an 8-bit or 16-bit address space can be set for each area, depending on the bus controller setting. If 16-bit access is selected for any one area, 16-bit bus mode is set; if 8-bit access is selected for all areas, 8-bit bus mode is set. Note that the functions of each pin depend on the operating mode. 73 The H8S/2626 Series and H8S/2623 Series can be used only in modes 4 to 7. This means that the mode pins must be set to select one of these modes. Do not change the inputs at the mode pins during operation. 3.1.2 Register Configuration The H8S/2626 Series and H8S/2623 Series have a mode control register (MDCR) that indicates the inputs at the mode pins (MD2 to MD0), and a system control register (SYSCR) that controls the operation of the H8S/2626 Series or H8S/2623 Series chip. Table 3-2 summarizes these registers. Table 3-2 Name Mode control register System control register Pin function control register MCU Registers Abbreviation MDCR SYSCR PFCR R/W R/W R/W R/W Initial Value Undetermined H'01 H'0D/H'00 Address* H'FDE7 H'FDE5 H'FDEB Note: * Lower 16 bits of the address. 3.2 3.2.1 Bit Register Descriptions Mode Control Register (MDCR) : 7 -- 1 R/W 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- 2 MDS2 --* R 1 MDS1 --* R 0 MDS0 --* R Initial value : R/W : Note: * Determined by pins MD2 to MD0. MDCR is an 8-bit register that indicates the current operating mode of the H8S/2626 Series or H8S/2623 Series chip. Bit 7--Reserved: Only 1 should be written to this bit. Bits 6 to 3--Reserved: These bits are always read as 0 and cannot be modified. Bits 2 to 0--Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the input levels at pins MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to MD2 to MD0. MDS2 to MDS0 are read-only bits-they cannot be written to. The mode pin (MD2 to MD0) input levels are latched into these bits when MDCR is read. These latches are canceled by a reset. 74 3.2.2 Bit System Control Register (SYSCR) : 7 MACS 0 R/W 6 -- 0 -- 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 2 -- 0 R/W 1 -- 0 -- 0 RAME 1 R/W Initial value : R/W : SYSCR is an 8-bit readable/writable register that selects saturating or non-saturating calculation for the MAC instruction, selects the interrupt control mode and the detected edge for NMI, and enables or disables on-chip RAM. SYSCR is initialized to H'01 by a reset and in hardware standby mode. SYSCR is not initialized in software standby mode. Bit 7--MAC Saturation (MACS): Selects either saturating or non-saturating calculation for the MAC instruction. Bit 7 MACS 0 1 Description Non-saturating calculation for MAC instruction Saturating calculation for MAC instruction (Initial value) Bit 6--Reserved: This bit is always read as 0 and cannot be modified. Bits 5 and 4--Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control mode of the interrupt controller. For details of the interrupt control modes, see section 5.4.1, Interrupt Control Modes and Interrupt Operation. Bit 5 INTM1 0 Bit 4 INTM0 0 1 1 0 1 Interrupt Control Mode 0 -- 2 -- Description Control of interrupts by I bit Setting prohibited Control of interrupts by I2 to I0 bits and IPR Setting prohibited (Initial value) 75 Bit 3--NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input. Bit 3 NMIEG 0 1 Description An interrupt is requested at the falling edge of NMI input An interrupt is requested at the rising edge of NMI input (Initial value) Bit 2--Reserved: Only 0 should be written to this bit. Bit 1--Reserved: This bit is always read as 0 and cannot be modified. Bit 0--RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset status is released. It is not initialized in software standby mode. Bit 0 RAME 0 1 Description On-chip RAM is disabled On-chip RAM is enabled (Initial value) Note: When the DTC is used, the RAME bit must be set to 1. 3.2.3 Bit Pin Function Control Register (PFCR) : 7 -- 0 R/W 6 -- 0 R/W 5 BUZZE 0 R/W 4 -- 0 R/W 3 AE3 1/0 R/W 2 AE2 1/0 R/W 1 AE1 0 R/W 0 AE0 1/0 R/W Initial value : R/W : PFCR is an 8-bit readable/writable register that performs address output control in external expanded mode. PFCR is initialized to H'0D/H'00 by a reset and in hardware standby mode. It retains its previous state in software standby mode. Bits 7 to 4--Reserved: Only 0 should be written to these bits. Bit 5--BUZZE Output Enable (BUZZE): This bit is for use only in the H8S/2626. Only 0 should be writtn to this bit. Bits 3 to 0--Address Output Enable 3 to 0 (AE3 to AE0): These bits select enabling or disabling of address outputs A8 to A23 in ROMless expanded mode and modes with ROM. When a pin is enabled for address output, the address is output regardless of the corresponding DDR 76 setting. When a pin is disabled for address output, it becomes an output port when the corresponding DDR bit is set to 1. Bit 3 AE3 0 Bit 2 AE2 0 Bit 1 AE1 0 Bit 0 AE0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Description A8-A23 address output disabled (Initial value*) A8 address output enabled; A9-A23 address output disabled A8, A9 address output enabled; A10-A23 address output disabled A8-A10 address output enabled; A11-A23 address output disabled A8-A11 address output enabled; A12-A23 address output disabled A8-A12 address output enabled; A13-A23 address output disabled A8-A13 address output enabled; A14-A23 address output disabled A8-A14 address output enabled; A15-A23 address output disabled A8-A15 address output enabled; A16-A23 address output disabled A8-A16 address output enabled; A17-A23 address output disabled A8-A17 address output enabled; A18-A23 address output disabled A8-A18 address output enabled; A19-A23 address output disabled A8-A19 address output enabled; A20-A23 address output disabled A8-A20 address output enabled; A21-A23 address output disabled (Initial value*) A8-A21 address output enabled; A22, A23 address output disabled A8-A23 address output enabled Note: * In expanded mode with ROM, bits AE3 to AE0 are initialized to B'0000. In ROMless expanded mode, bits AE3 to AE0 are initialized to B'1101. Address pins A0 to A7 are made address outputs by setting the corresponding DDR bits to 1. 77 3.3 3.3.1 Operating Mode Descriptions Mode 4 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports 1, A, B, and C, function as an address bus, ports D and E function as a data bus, and part of port F carries bus control signals. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, note that if 8bit access is designated by the bus controller for all areas, the bus mode switches to 8 bits. 3.3.2 Mode 5 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports 1, A, B, and C, function as an address bus, ports D and E function as a data bus, and part of port F carries bus control signals. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if 16bit access is designated by the bus controller for any area, the bus mode switches to 16 bits and port E becomes a data bus. 3.3.3 Mode 6 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. Ports 1, A, B, and C, function as input port pins immediately after a reset. Address output can be performed by setting the corresponding DDR (data direction register) bits to 1. Port D function as a data bus, and part of port F carries data bus signals. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if 16bit access is designated by the bus controller for any area, the bus mode switches to 16 bits and port E becomes a data bus. 3.3.4 Mode 7 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled, but external addresses cannot be accessed. All I/O ports are available for use as input-output ports. 78 3.4 Pin Functions in Each Operating Mode The pin functions of ports 1 and A to F vary depending on the operating mode. Table 3-3 shows their functions in each operating mode. Table 3-3 Port Port 1 P10 P11 to P13 Port A Port B Port C Port D Port E Port F PF7 PF6 to PF4 PF3 PF2 to PF0 Legend P: I/O port A: Address bus output D: Data bus I/O C: Control signals, clock I/O *: After reset PA4 to PA0 Pin Functions in Each Mode Mode 4 A P*/A A A A D P/D* P/C* C P/C* P*/C Mode 5 A P*/A A A A D P*/D P/C* C P*/C P*/C Mode 6 P*/A P*/A P*/A P*/A P*/A D P*/D P/C* C P*/C P*/C Mode 7 P P P P P P P P*/C P 3.5 Address Map in Each Operating Mode An address map of the H8S/2623 and H8S/2626 is shown in figure 3-1, and an address map of the H8S/2622, and H8S/2625 in figure 3-2, and an address map of the H8S/2621 and H8S/2624 in figure 3-3. The address space is 16 Mbytes in modes 4 to 7 (advanced modes). The address space is divided into eight areas for modes 4 to 7. For details, see section 7, Bus Controller. 79 Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 7 (advanced single-chip mode) H'000000 External address space On-chip ROM On-chip ROM H'03FFFF H'040000 H'FFB000 H'FFC000 H'FFEFC0 H'FFF800 Internal I/O registers H'FFFF40 External area H'FFFF40 H'FFB000 H'FFC000 H'FFEFC0 H'FFF800 Internal I/O registers H'FFFF3F External area H'FFFF60 Internal I/O registers H'FFFFC0 On-chip RAM H'FFFFFF H'FFFF60 Internal I/O registers H'FFFFC0 On-chip RAM* H'FFFFFF H'FFFF60 Internal I/O registers H'FFFFC0 On-chip RAM* H'FFFFFF External address space Reserved area On-chip RAM* External area Reserved area On-chip RAM* External area H'FFF800 Internal I/O registers H'FFC000 H'FFEFBF On-chip RAM Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3-1 Memory Map in Each Operating Mode in the H8S/2623 and H8S/2626 80 Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 7 (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM External address space H'01FFFF H'020000 Reserved area H'040000 H'FFB000 H'FFD000 H'FFEFC0 H'FFF800 Internal I/O registers H'FFFF40 External area H'FFFF40 H'FFB000 H'FFD000 H'FFEFC0 H'FFF800 External address space Reserved area On-chip RAM* External area Reserved area On-chip RAM* External area H'FFF800 Internal I/O registers H'FFFF3F External area H'FFFF60 Internal I/O registers H'FFFFC0 On-chip RAM H'FFFFFF Internal I/O registers H'FFD000 H'FFEFBF On-chip RAM H'FFFF60 Internal I/O registers H'FFFFC0 On-chip RAM* H'FFFFFF H'FFFF60 Internal I/O registers H'FFFFC0 On-chip RAM* H'FFFFFF Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3-2 Memory Map in Each Operating Mode in the H8S/2622 and H8S/2625 81 Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 7 (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM H'00FFFF H'010000 External address space Reserved area H'040000 H'FFB000 Reserved area H'FFE000 H'FFEFC0 H'FFF800 Internal I/O registers H'FFFF40 External area H'FFFF40 On-chip RAM* External area H'FFE000 H'FFEFC0 H'FFF800 H'FFB000 External address space Reserved area On-chip RAM* External area H'FFF800 Internal I/O registers H'FFFF3F External area H'FFFF60 Internal I/O registers H'FFFFC0 On-chip RAM H'FFFFFF Internal I/O registers H'FFE000 H'FFEFBF On-chip RAM H'FFFF60 Internal I/O registers H'FFFFC0 On-chip RAM* H'FFFFFF H'FFFF60 Internal I/O registers H'FFFFC0 On-chip RAM* H'FFFFFF Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3-3 Memory Map in Each Operating Mode in the H8S/2621 and H8S/2624 82 Section 4 Exception Handling 4.1 4.1.1 Overview Exception Handling Types and Priority As table 4-1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4-1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Trap instruction exceptions are accepted at all times, in the program execution state. Exception handling sources, the stack structure, and the operation of the CPU vary depending on the interrupt control mode set by the INTM0 and INTM1 bits of SYSCR. Table 4-1 Priority High Exception Types and Priority Exception Type Reset Start of Exception Handling Starts immediately after a low-to-high transition at the RES pin, or when the watchdog timer overflows. The CPU enters the reset state when the RES pin is low. Starts when execution of the current instruction or exception handling ends, if the trace (T) bit is set to 1 Starts when a direction transition occurs as the result of SLEEP instruction execution. Starts when execution of the current instruction or exception handling ends, if an interrupt request has been issued* 2 Trace* 1 Direct transition Interrupt Low Trap instruction (TRAPA)*3 Started by execution of a trap instruction (TRAPA) Notes: *1 Traces are enabled only in interrupt control mode 2. Trace exception handling is not executed after execution of an RTE instruction. *2 Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. *3 Trap instruction exception handling requests are accepted at all times in program execution state. 83 4.1.2 Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: 1. The program counter (PC), condition code register (CCR), and extended register (EXR) are pushed onto the stack. 2. The interrupt mask bits are updated. The T bit is cleared to 0. 3. A vector address corresponding to the exception source is generated, and program execution starts from that address. For a reset exception, steps 2 and 3 above are carried out. 4.1.3 Exception Vector Table The exception sources are classified as shown in figure 4-1. Different vector addresses are assigned to different exception sources. Table 4-2 lists the exception sources and their vector addresses. Reset Reset Manual reset*1 Trace Exception sources Interrupts External interrupts: NMI, IRQ5 to IRQ0 Internal interrupts: 47 interrupt sources*2 in on-chip supporting modules Trap instruction Notes: *1 Not available in the H8S/2626 Series or H8S/2623 Series. *2 48 interrupt sources in the H8S/2626 Series. Figure 4-1 Exception Sources 84 Table 4-2 Exception Vector Table Vector Address* 1 Exception Source Reset Manual reset* Reserved 3 Vector Number 0 1 2 3 4 Advanced Mode H'0000 to H'0003 H'0004 to H'0007 H'0008 to H'000B H'000C to H'000F H'0010 to H'0013 H'0014 to H'0017 H'0018 to H'001B H'001C to H'001F H'0020 to H'0023 H'0024 to H'0027 H'0028 to H'002B H'002C to H'002F H'0030 to H'0033 H'0034 to H'0037 H'0038 to H'003B H'003C to H'003F H'0040 to H'0043 H'0044 to H'0047 H'0048 to H'004B H'004C to H'004F H'0050 to H'0053 H'0054 to H'0057 H'0058 to H'005B H'005C to H'005F H'0060 to H'0063 H'01FC to H'01FF Trace Direct transitions* (H8S/2626 only) External interrupt NMI 4 5 6 7 8 9 10 11 Trap instruction (4 sources) Reserved 12 13 14 15 External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 16 17 18 19 20 21 22 23 Reserved Internal interrupt* 2 24 127 Notes: *1 Lower 16 bits of the address. *2 For details of internal interrupt vectors, see section 5.3.3, Interrupt Exception Handling Vector Table. *3 Not available in the H8S/2626 Series or H8S/2623 Series. *4 See section 21B.11, Direct Transitions, for details. 85 4.2 4.2.1 Reset Overview A reset has the highest exception priority. When the RES pin goes low, all processing halts and the H8S/2626 Series or H8S/2623 Series enters the reset state. A reset initializes the internal state of the CPU and the registers of on-chip supporting modules. Immediately after a reset, interrupt control mode 0 is set. Reset exception handling begins when the RES pin changes from low to high. The chip can also be reset by overflow of the watchdog timer. For details see section 12, Watchdog Timer. 4.2.2 Reset Sequence The chip enters the reset state when the RES pin goes low. To ensure that the chip is reset, hold the RES pin low for at least 20 ms at power-up. To reset the chip during operation, hold the RES pin low for at least 20 states. When the RES pin goes high after being held low for the necessary time, the chip starts reset exception handling as follows: 1. The internal state of the CPU and the registers of the on-chip supporting modules are initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR. 2. The reset exception handling vector address is read and transferred to the PC, and program execution starts from the address indicated by the PC. Figures 4-2 and 4-3 show examples of the reset sequence. 86 Vector fetch Internal Prefetch of first processing program instruction * * * o RES Address bus RD HWR, LWR D15 to D0 (2) (1) (3) (5) High (4) (6) (1) (3) Reset exception handling vector address (when reset, (1) = H'000000, (3) = H'000002) (2) (4) Start address (contents of reset exception handling vector address) (5) Start address ((5) = (2) (4)) (6) First program instruction Note: * Three program wait states are inserted. Figure 4-2 Reset Sequence (Modes 4 and 5) 87 Vector fetch Prefetch of Internal first program processing instruction o RES Internal address bus (1) (3) (5) Internal read signal Internal write signal Internal data bus (2) High (4) (6) (1) (3) Reset exception handling vector address (when reset, (1) = H'000000, (3) = H'000002) (2) (4) Start address (contents of reset exception handling vector address) (5) Start address ((5) = (2) (4)) (6) First program instruction Figure 4-3 Reset Sequence (Modes 6 and 7) 4.2.3 Interrupts after Reset If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.L #xx: 32, SP). 4.2.4 State of On-Chip Supporting Modules after Reset Release After reset release, MSTPCRA to MSTPCRC are initialized to H'3F, H'FF, and H'FF, respectively, and all modules except the DTC enter module stop mode. Consequently, on-chip supporting module registers cannot be read or written to. Register reading and writing is enabled when module stop mode is exited. 88 4.3 Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction. Trace mode is canceled by clearing the T bit in EXR to 0. It is not affected by interrupt masking. Table 4-3 shows the state of CCR and EXR after execution of trace exception handling. Interrupts are accepted even within the trace exception handling routine. The T bit saved on the stack retains its value of 1, and when control is returned from the trace exception handling routine by the RTE instruction, trace mode resumes. Trace exception handling is not carried out after execution of the RTE instruction. Table 4-3 Status of CCR and EXR after Trace Exception Handling CCR Interrupt Control Mode 0 2 1 I UI I2 to I0 EXR T Trace exception handling cannot be used. -- -- 0 Legend 1: Set to 1 0: Cleared to 0 --: Retains value prior to execution. 89 4.4 Interrupts Interrupt exception handling can be requested by seven external sources (NMI, IRQ5 to IRQ0) and internal sources (H8S/2626 Series: 48, H8S/2623 Series: 47) in the on-chip supporting modules. Figure 4-4 classifies the interrupt sources and the number of interrupts of each type. The on-chip supporting modules that can request interrupts include the watchdog timer (WDT), 16-bit timer-pulse unit (TPU), serial communication interface (SCI), data transfer controller (DTC), PC break controller (PBC), Hitachi controller area network (HCAN), and A/D converter. Each interrupt source has a separate vector address. NMI is the highest-priority interrupt. Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign interrupts other than NMI to eight priority/mask levels to enable multiplexed interrupt control. For details of interrupts, see section 5, Interrupt Controller. External interrupts Interrupts NMI (1) IRQ5 to IRQ0 (6) Internal interrupts WDT* H8S/2626 Series (2), H8S/2623 Series (1) TPU (26) SCI (12) DTC (1) PBC (1) HCAN (5) A/D converter (1) Notes: Numbers in parentheses are the numbers of interrupt sources. * When the watchdog timer is used as an interval timer, it generates an interrupt request at each counter overflow. Figure 4-4 Interrupt Sources and Number of Interrupts 90 4.5 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4-4 shows the status of CCR and EXR after execution of trap instruction exception handling. Table 4-4 Status of CCR and EXR after Trap Instruction Exception Handling CCR Interrupt Control Mode 0 2 I 1 1 UI -- -- I2 to I0 -- -- EXR T -- 0 Legend 1: Set to 1 0: Cleared to 0 --: Retains value prior to execution. 91 4.6 Stack Status after Exception Handling Figures 4-5 (1) and 4-5 (2) show the stack after completion of trap instruction exception handling and interrupt exception handling. SP SP CCR CCR* PC (16 bits) EXR Reserved* CCR CCR* PC (16 bits) (a) Interrupt control mode 0 Note: * Ignored on return. (b) Interrupt control mode 2 Figure 4-5 (1) Stack Status after Exception Handling (Normal Modes: Not Available in the H8S/2626 Series or H8S/2623 Series) SP SP CCR PC (24 bits) EXR Reserved* CCR PC (24 bits) (a) Interrupt control mode 0 Note: * Ignored on return. (b) Interrupt control mode 2 Figure 4-5 (2) Stack Status after Exception Handling (Advanced Modes) 92 4.7 Notes on Use of the Stack When accessing word data or longword data, the H8S/2626 Series or H8S/2623 Series assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W PUSH.L Rn ERn (or MOV.W Rn, @-SP) (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W POP.L Rn ERn (or MOV.W @SP+, Rn) (or MOV.L @SP+, ERn) Setting SP to an odd value may lead to a malfunction. Figure 4-6 shows an example of what happens when the SP value is odd. CCR SP PC SP R1L PC H'FFFEFA H'FFFEFB H'FFFEFC H'FFFEFD H'FFFEFF SP TRAP instruction executed MOV.B R1L, @-ER7 SP set to H'FFFEFF Data saved above SP Contents of CCR lost Legend CCR: Condition code register PC: Program counter R1L: General register R1L SP: Stack pointer Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode. Figure 4-6 Operation when SP Value is Odd 93 94 Section 5 Interrupt Controller 5.1 5.1.1 Overview Features The H8S/2626 Series and H8S/2623 Series control interrupts by means of an interrupt controller. The interrupt controller has the following features: * Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). * Priorities settable with IPR An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority levels can be set for each module for all interrupts except NMI. NMI is assigned the highest priority level of 8, and can be accepted at all times. * Independent vector addresses All interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. * Seven external interrupts NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge can be selected for NMI. Falling edge, rising edge, or both edge detection, or level sensing, can be selected for IRQ5 to IRQ0. * DTC control DTC activation is performed by means of interrupts. 95 5.1.2 Block Diagram A block diagram of the interrupt controller is shown in figure 5-1. INTM1 INTM0 SYSCR NMIEG NMI input IRQ input NMI input unit IRQ input unit ISR ISCR IER Priority determination I Internal interrupt request SWDTEND to SLE0 IPR Interrupt controller Interrupt request Vector number CPU CCR I2 to I0 EXR Legend ISCR IER ISR IPR SYSCR : IRQ sense control register : IRQ enable register : IRQ status register : Interrupt priority register : System control register Figure 5-1 Block Diagram of Interrupt Controller 96 5.1.3 Pin Configuration Table 5-1 summarizes the pins of the interrupt controller. Table 5-1 Name Nonmaskable interrupt External interrupt requests 5 to 0 Interrupt Controller Pins Symbol NMI I/O Input Function Nonmaskable external interrupt; rising or falling edge can be selected Maskable external interrupts; rising, falling, or both edges, or level sensing, can be selected IRQ5 to IRQ0 Input 5.1.4 Register Configuration Table 5-2 summarizes the registers of the interrupt controller. Table 5-2 Name System control register IRQ sense control register H IRQ sense control register L IRQ enable register IRQ status register Interrupt priority register A Interrupt priority register B Interrupt priority register C Interrupt priority register D Interrupt priority register E Interrupt priority register F Interrupt priority register G Interrupt priority register H Interrupt priority register I Interrupt priority register J Interrupt priority register K Interrupt priority register M Interrupt Controller Registers Abbreviation SYSCR ISCRH ISCRL IER ISR IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK IPRM R/W R/W R/W R/W R/W R/(W)* R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 2 Initial Value H'01 H'00 H'00 H'00 H'00 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 Address* 1 H'FDE5 H'FE12 H'FE13 H'FE14 H'FE15 H'FEC0 H'FEC1 H'FEC2 H'FEC3 H'FEC4 H'FEC5 H'FEC6 H'FEC7 H'FEC8 H'FEC9 H'FECA H'FECC Notes: *1 Lower 16 bits of the address. *2 Only 0 can be written, for flag clearing. 97 5.2 5.2.1 Bit Register Descriptions System Control Register (SYSCR) : 7 MACS 0 R/W 6 -- 0 -- 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 2 -- 0 R/W 1 -- 0 -- 0 RAME 1 R/W Initial value : R/W : SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for NMI. Only bits 5 to 3 are described here; for details of the other bits, see section 3.2.2, System Control Register (SYSCR). SYSCR is initialized to H'01 by a reset and in hardware standby mode. SYSCR is not initialized in software standby mode. Bits 5 and 4--Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select one of two interrupt control modes for the interrupt controller. Bit 5 INTM1 0 Bit 4 INTM0 0 1 1 0 1 Interrupt Control Mode 0 -- 2 -- Description Interrupts are controlled by I bit Setting prohibited Interrupts are controlled by bits I2 to I0, and IPR Setting prohibited (Initial value) Bit 3--NMI Edge Select (NMIEG): Selects the input edge for the NMI pin. Bit 3 NMIEG 0 1 Description Interrupt request generated at falling edge of NMI input Interrupt request generated at rising edge of NMI input (Initial value) 98 5.2.2 Bit Interrupt Priority Registers A to K, M (IPRA to IPRK, IPRM) : 7 -- 0 -- 6 IPR6 1 R/W 5 IPR5 1 R/W 4 IPR4 1 R/W 3 -- 0 -- 2 IPR2 1 R/W 1 IPR1 1 R/W 0 IPR0 1 R/W Initial value : R/W : The IPR registers are twelve 8-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than NMI. The correspondence between IPR settings and interrupt sources is shown in table 5-3. The IPR registers set a priority (level 7 to 0) for each interrupt source other than NMI. The IPR registers are initialized to H'77 by a reset and in hardware standby mode. They are not initialized in software standby mode. Bits 7 and 3--Reserved: These bits are always read as 0 and cannot be modified. Table 5-3 Correspondence between Interrupt Sources and IPR Settings Bits Register IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK IPRM 6 to 4 IRQ0 IRQ2 IRQ3 --* 1 WDT0 PC break TPU channel 0 TPU channel 2 TPU channel 4 --* 1 2 to 0 IRQ1 IRQ4 IRQ5 DTC --* 1 A/D converter, WDT1*2 TPU channel 1 TPU channel 3 TPU channel 5 --* 1 SCI channel 0 SCI channel 2 --* 1 --* 1 SCI channel 1 HCAN Notes: *1 Reserved bits. These bits are always read as 1 and cannot be modified. *2 Valid only in the H8S/2626 Series. 99 As shown in table 5-3, multiple interrupts are assigned to one IPR. Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits 6 to 4 and 2 to 0 sets the priority of the corresponding interrupt. The lowest priority level, level 0, is assigned by setting H'0, and the highest priority level, level 7, by setting H'7. When interrupt requests are generated, the highest-priority interrupt according to the priority levels set in the IPR registers is selected. This interrupt level is then compared with the interrupt mask level set by the interrupt mask bits (I2 to I0) in the extend register (EXR) in the CPU, and if the priority level of the interrupt is higher than the set mask level, an interrupt request is issued to the CPU. 5.2.3 Bit IRQ Enable Register (IER) : 7 -- 0 R/W 6 -- 0 R/W 5 IRQ5E 0 R/W 4 IRQ4E 0 R/W 3 IRQ3E 0 R/W 2 IRQ2E 0 R/W 1 IRQ1E 0 R/W 0 IRQ0E 0 R/W Initial value : R/W : IER is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests IRQ5 to IRQ0. IER is initialized to H'00 by a reset and in hardware standby mode. They are not initialized in software standby mode. Bits 7 and 6--Reserved: Only 0 should be written to these bits. Bits 5 to 0--IRQ5 to IRQ0 Enable (IRQ7E to IRQ0E): These bits select whether IRQ5 to IRQ0 are enabled or disabled. Bit n IRQnE 0 1 Description IRQn interrupts disabled IRQn interrupts enabled (n = 5 to 0) (Initial value) 100 5.2.4 ISCRH Bit IRQ Sense Control Registers H and L (ISCRH, ISCRL) : 15 -- 0 R/W 14 -- 0 R/W 13 -- 0 R/W 12 -- 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value : R/W ISCRL Bit : : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial value : R/W : The ISCR registers are 16-bit readable/writable registers that select rising edge, falling edge, or both edge detection, or level sensing, for the input at pins IRQ5 to IRQ0. The ISCR registers are initialized to H'0000 by a reset and in hardware standby mode. They are not initialized in software standby mode. Bits 15 to 12--Reserved: Only 0 should be written to these bits. Bits 11 to 0: IRQ7 Sense Control A and B (IRQ5SCA, IRQ5SCB) to IRQ0 Sense Control A and B (IRQ0SCA, IRQ0SCB) Bits 11 to 0 IRQ5SCB to IRQ0SCB 0 IRQ5SCA to IRQ0SCA 0 1 1 0 1 Description Interrupt request generated at IRQ5 to IRQ0 input low level (Initial value) Interrupt request generated at falling edge of IRQ5 to IRQ0 input Interrupt request generated at rising edge of IRQ5 to IRQ0 input Interrupt request generated at both falling and rising edges of IRQ5 to IRQ0 input 101 5.2.5 Bit IRQ Status Register (ISR) : 7 -- 0 R/(W)* 6 -- 0 R/(W)* 5 IRQ5F 0 R/(W)* 4 IRQ4F 0 R/(W)* 3 IRQ3F 0 R/(W)* 2 IRQ2F 0 R/(W)* 1 IRQ1F 0 R/(W)* 0 IRQ0F 0 R/(W)* Initial value : R/W : Note: * Only 0 can be written, to clear the flag. ISR is an 8-bit readable/writable register that indicates the status of IRQ5 to IRQ0 interrupt requests. ISR is initialized to H'00 by a reset and in hardware standby mode. They are not initialized in software standby mode. Bits 7 and 6--Reserved: Only 0 should be written to these bits. Bits 5 to 0--IRQ5 to IRQ0 flags (IRQ5F to IRQ0F): These bits indicate the status of IRQ7 to IRQ0 interrupt requests. Bit n IRQnF 0 Description [Clearing conditions] (Initial value) * * * * 1 Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag When interrupt exception handling is executed when low-level detection is set (IRQnSCB = IRQnSCA = 0) and IRQn input is high When IRQn interrupt exception handling is executed when falling, rising, or both-edge detection is set (IRQnSCB = 1 or IRQnSCA = 1) When the DTC is activated by an IRQn interrupt, and the DISEL bit in MRB of the DTC is cleared to 0 When IRQn input goes low when low-level detection is set (IRQnSCB = IRQnSCA = 0) When a falling edge occurs in IRQn input when falling edge detection is set (IRQnSCB = 0, IRQnSCA = 1) When a rising edge occurs in IRQn input when rising edge detection is set (IRQnSCB = 1, IRQnSCA = 0) When a falling or rising edge occurs in IRQn input when both-edge detection is set (IRQnSCB = IRQnSCA = 1) (n = 5 to 0) 102 [Setting conditions] * * * * 5.3 Interrupt Sources Interrupt sources comprise external interrupts (NMI and IRQ5 to IRQ0) and internal interrupts (48 sources: H8S/2626 Series, 47 sources: H8S/2623 Series). 5.3.1 External Interrupts There are seven external interrupts: NMI and IRQ5 to IRQ0. These interrupts can be used to restore the H8S/2626 Series or H8S/2623 Series chip from software standby mode. NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling edge on the NMI pin. The vector number for NMI interrupt exception handling is 7. IRQ5 to IRQ0 Interrupts: Interrupts IRQ5 to IRQ0 are requested by an input signal at pins IRQ5 to IRQ0. Interrupts IRQ5 to IRQ0 have the following features: * Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins IRQ5 to IRQ0. * Enabling or disabling of interrupt requests IRQ5 to IRQ0 can be selected with IER. * The interrupt priority level can be set with IPR. * The status of interrupt requests IRQ5 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0 by software. A block diagram of interrupts IRQ5 to IRQ0 is shown in figure 5-2. IRQnE IRQnSCA, IRQnSCB IRQnF Edge/level detection circuit IRQn input Clear signal Note: n = 5 to 0 IRQn interrupt S R Q request Figure 5-2 Block Diagram of Interrupts IRQ5 to IRQ0 103 Figure 5-3 shows the timing of setting IRQnF. o IRQn input pin IRQnF Figure 5-3 Timing of Setting IRQnF The vector numbers for IRQ5 to IRQ0 interrupt exception handling are 21 to 16. Detection of IRQ5 to IRQ0 interrupts does not depend on whether the relevant pin has been set for input or output. However, when a pin is used as an external interrupt input pin, do not clear the corresponding DDR to 0 and use the pin as an I/O pin for another function. 5.3.2 Internal Interrupts There are 48 sources for internal interrupts from on-chip supporting modules in the H8S/2626 Series, and 47 in the H8S/2623 Series. * For each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. If both of these are set to 1 for a particular interrupt source, an interrupt request is issued to the interrupt controller. * The interrupt priority level can be set by means of IPR. * The DTC can be activated by a TPU, 8-bit timer, SCI, or other interrupt request. When the DTC is activated by an interrupt, the interrupt control mode and interrupt mask bits are not affected. 5.3.3 Interrupt Exception Handling Vector Table Table 5-4 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. Priorities among modules can be set by means of the IPR. The situation when two or more modules are set to the same priority, and priorities within a module, are fixed as shown in table 5-4. 104 Table 5-4 Interrupt Sources, Vector Addresses, and Interrupt Priorities Vector Address* Vector Number 7 16 17 18 19 20 21 -- DTC Watchdog timer 0 -- PC break A/D Watchdog timer 1 -- TPU channel 0 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 -- 37 38 39 Advanced Mode H'001C H'0040 H'0044 H'0048 H'004C H'0050 H'0054 H'0058 H'005C H'0060 H'0064 H'0068 H'006C H'0070 H'0074 H'0078 H'007C H'0080 H'0084 H'0088 H'008C H'0090 H'0094 H'0098 H'009C IPRF6 to 4 IPRA6 to 4 IPRA2 to 0 IPRB6 to 4 IPRB2 to 0 IPRC6 to 4 IPRC2 to 0 IPRD6 to 4 IPRD2 to 0 IPRE6 to 4 IPRE2 to 0 IPR Priority High Interrupt Source NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 Reserved SWDTEND (software activation interrupt end) WOVI0 (interval timer) Reserved PC break ADI (A/D conversion end) WOVI1 (interval timer) (H8S/2626 Series only) Reserved TGI0A (TGR0A input capture/compare match) TGI0B (TGR0B input capture/compare match) TGI0C (TGR0C input capture/compare match) TGI0D (TGR0D input capture/compare match) TCI0V (overflow 0) Reserved Origin of Interrupt Source External pin Low 105 Interrupt Source TGI1A (TGR1A input capture/compare match) TGI1B (TGR1B input capture/compare match) TCI1V (overflow 1) TCI1U (underflow 1) TGI2A (TGR2A input capture/compare match) TGI2B (TGR2B input capture/compare match) TCI2V (overflow 2) TCI2U (underflow 2) TGI3A (TGR3A input capture/compare match) TGI3B (TGR3B input capture/compare match) TGI3C (TGR3C input capture/compare match) TGI3D (TGR3D input capture/compare match) TCI3V (overflow 3) Reserved Origin of Interrupt Source TPU channel 1 Vector Address* Vector Number 40 41 42 43 Advanced Mode H'00A0 H'00A4 H'00A8 H'00AC H'00B0 H'00B4 H'00B8 H'00BC H'00C0 H'00C4 H'00C8 H'00CC H'00D0 H'00D4 H'00D8 H'00DC H'00E0 H'00E4 H'00E8 H'00EC H'00F0 H'00F4 H'00F8 H'00FC IPRH2 to 0 IPRH6 to 4 IPRG2 to 0 IPRG6 to 4 IPR IPRF2 to 0 Priority High TPU channel 2 44 45 46 47 TPU channel 3 48 49 50 51 52 -- 53 54 55 56 57 58 59 TGI4A (TGR4A input capture/compare match) TGI4B (TGR4B input capture/compare match) TCI4V (overflow 4) TCI4U (underflow 4) TGI5A (TGR5A input capture/compare match) TGI5B (TGR5B input capture/compare match) TCI5V (overflow 5) TCI5U (underflow 5) TPU channel 4 TPU channel 5 60 61 62 63 Low 106 Interrupt Source Reserved Origin of Interrupt Source -- Vector Address* Vector Number 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 Advanced Mode H'0100 H'0104 H'0108 H'010C H'0110 H'0114 H'0118 H'011C H'0120 H'0124 H'0128 H'012C H'0130 H'0134 H'0138 H'013C H'0140 H'0144 H'0148 H'014C H'0150 H'0154 H'0158 H'015C H'0160 H'0164 H'0168 H'016C H'01A0 H'01A4 H'01A8 H'01AC H'01B0 IPRJ2 to 0 IPRI2 to 0 IPR IPRI6 to 4 Priority High IPRJ6 to 4 ERI0 (receive error 0) RXI0 (reception completed 0) TXI0 (transmit data empty 0) TEI0 (transmission end 0) ERI1 (receive error 1) RXI1 (reception completed 1) TXI1 (transmit data empty 1) TEI1 (transmission end 1) ERI2 (receive error 2) RXI2 (reception completed 2) TXI2 (transmit data empty 2) TEI2 (transmission end 2) ERS0 OVR0 RM0 RM1 SLE0 SCI channel 0 80 81 82 83 84 85 86 87 88 89 90 91 104 105 106 107 108 SCI channel 1 IPRK6 to 4 SCI channel 2 IPRK2 to 0 HCAN IPRM6 to 4 IPRM2 to 0 Low Note: * Lower 16 bits of the start address. 107 5.4 5.4.1 Interrupt Operation Interrupt Control Modes and Interrupt Operation Interrupt operations in the H8S/2626 Series and H8S/2623 Series differ depending on the interrupt control mode. NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request. Interrupt sources for which the enable bits are set to 1 are controlled by the interrupt controller. Table 5-5 shows the interrupt control modes. The interrupt controller performs interrupt control according to the interrupt control mode set by the INTM1 and INTM0 bits in SYSCR, the priorities set in IPR, and the masking state indicated by the I and UI bits in the CPU's CCR, and bits I2 to I0 in EXR. Table 5-5 Interrupt Control Modes Interrupt Mask Bits Description I -- I2 to I0 Interrupt mask control is performed by the I bit. Setting prohibited 8-level interrupt mask control is performed by bits I2 to I0. 8 priority levels can be set with IPR. Setting prohibited SYSCR Interrupt Priority Setting Control Mode INTM1 INTM0 Registers 0 -- 2 1 0 0 1 0 -- -- IPR -- 1 -- -- 108 Figure 5-4 shows a block diagram of the priority decision circuit. Interrupt control mode 0 I Interrupt acceptance control Interrupt source Default priority determination 8-level mask control Vector number IPR I2 to I0 Interrupt control mode 2 Figure 5-4 Block Diagram of Interrupt Control Operation (1) Interrupt Acceptance Control In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR. Table 5-6 shows the interrupts selected in each interrupt control mode. Table 5-6 Interrupts Selected in Each Interrupt Control Mode (1) Interrupt Mask Bits Interrupt Control Mode 0 I 0 1 2 * Selected Interrupts All interrupts NMI interrupts All interrupts * : Don't care 109 (2) 8-Level Control In interrupt control mode 2, 8-level mask level determination is performed for the selected interrupts in interrupt acceptance control according to the interrupt priority level (IPR). The interrupt source selected is the interrupt with the highest priority level, and whose priority level set in IPR is higher than the mask level. Table 5-7 Interrupts Selected in Each Interrupt Control Mode (2) Selected Interrupts All interrupts Highest-priority-level (IPR) interrupt whose priority level is greater than the mask level (IPR > I2 to I0). Interrupt Control Mode 0 2 (3) Default Priority Determination When an interrupt is selected by 8-level control, its priority is determined and a vector number is generated. If the same value is set for IPR, acceptance of multiple interrupts is enabled, and so only the interrupt source with the highest priority according to the preset default priorities is selected and has a vector number generated. Interrupt sources with a lower priority than the accepted interrupt source are held pending. Table 5-8 shows operations and control signal functions in each interrupt control mode. Table 5-8 Operations and Control Signal Functions in Each Interrupt Control Mode Interrupt Acceptance Control I Interrupt Setting Control Mode INTM1 INTM0 8-Level Control I2 to I0 IPR Default Priority Determination T (Trace) 0 2 0 1 0 0 X IM --* 1 X -- IM --* 2 PR -- T Legend : Interrupt operation control performed X : No operation. (All interrupts enabled) IM : Used as interrupt mask bit PR : Sets priority. -- : Not used. Notes: *1 Set to 1 when interrupt is accepted. *2 Keep the initial setting. 110 5.4.2 Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU's CCR. Interrupts are enabled when the I bit is cleared to 0, and disabled when set to 1. Figure 5-5 shows a flowchart of the interrupt acceptance operation in this case. [1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. [2] The I bit is then referenced. If the I bit is cleared to 0, the interrupt request is accepted. If the I bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending. [3] Interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to the priority system is accepted, and other interrupt requests are held pending. [4] When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. [5] The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. [6] Next, the I bit in CCR is set to 1. This masks all interrupts except NMI. [7] A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address. 111 Program execution status Interrupt generated? Yes Yes No NMI No No I=0 Yes Hold pending No IRQ0 Yes No IRQ1 Yes SLE0 Yes Save PC and CCR I1 Read vector address Branch to interrupt handling routine Figure 5-5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 112 5.4.3 Interrupt Control Mode 2 Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits I2 to I0 of EXR in the CPU with IPR. Figure 5-6 shows a flowchart of the interrupt acceptance operation in this case. [1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. [2] When interrupt requests are sent to the interrupt controller, the interrupt with the highest priority according to the interrupt priority levels set in IPR is selected, and lower-priority interrupt requests are held pending. If a number of interrupt requests with the same priority are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 5-4 is selected. [3] Next, the priority of the selected interrupt request is compared with the interrupt mask level set in EXR. An interrupt request with a priority no higher than the mask level set at that time is held pending, and only an interrupt request with a priority higher than the interrupt mask level is accepted. [4] When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. [5] The PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. [6] The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority level of the accepted interrupt. If the accepted interrupt is NMI, the interrupt mask level is set to H'7. [7] A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address. 113 Program execution status Interrupt generated? Yes Yes NMI No No No Level 7 interrupt? Yes Mask level 6 or below? Yes Level 6 interrupt? No Yes Mask level 5 or below? Yes No Level 1 interrupt? No Yes No Mask level 0? Yes No Save PC, CCR, and EXR Hold pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Figure 5-6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2 114 5.4.4 Interrupt acceptance Instruction prefetch Stack Vector fetch Internal operation Internal operation Interrupt service routine instruction prefetch Interrupt level determination Wait for end of instruction o Interrupt request signal Internal address bus (1) (3) (7) (9) (5) (11) (13) Interrupt Exception Handling Sequence Internal read signal Internal write signal (2) (8) Figure 5-7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. Figure 5-7 Interrupt Exception Handling (4) (6) (10) (12) Internal data us (14) (1) Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) (2) (4) Instruction code (Not executed.) (3) Instruction prefetch address (Not executed.) (5) SP-2 (7) SP-4 (6) (8) Saved PC and saved CCR (9) (11) Vector address (10) (12) Interrupt handling routine start address (vector address contents) (13) Interrupt handling routine start address ((13) = (10) (12)) (14) First instruction of interrupt handling routine 115 5.4.5 Interrupt Response Times The H8S/2626 Series and H8S/2623 Series are capable of fast word transfer to on-chip memory, and have the program area in on-chip ROM and the stack area in on-chip RAM, enabling highspeed processing. Table 5-9 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5-9 are explained in table 5-10. Table 5-9 Interrupt Response Times Normal Mode* 5 No. 1 2 3 4 5 6 Execution Status Interrupt priority determination* 1 Advanced Mode INTM1 = 0 3 1 to (19+2*SI) 2*S K 2*S I 2*S I 2 12 to 32 INTM1 = 1 3 1 to (19+2*SI) 3*S K 2*S I 2*S I 2 13 to 33 INTM1 = 0 3 INTM1 = 1 3 1 to (19+2*SI) 3*S K SI 2*S I 2 12 to 32 Number of wait states until executing 1 to instruction ends* 2 (19+2*SI) PC, CCR, EXR stack save Vector fetch Instruction fetch* 3 4 2*S K SI 2*S I 2 11 to 31 Internal processing* Total (using on-chip memory) Notes: *1 *2 *3 *4 *5 Two states in case of internal interrupt. Refers to MULXS and DIVXS instructions. Prefetch after interrupt acceptance and interrupt handling routine prefetch. Internal processing after interrupt acceptance and internal processing after vector fetch. Not available in the H8S/2626 Series or H8S/2623 Series. 116 Table 5-10 Number of States in Interrupt Handling Routine Execution Statuses Object of Access External Device 8 Bit Bus Symbol Instruction fetch Branch address read Stack manipulation SI SJ SK Internal Memory 1 2-State Access 4 3-State Access 6+2m 16 Bit Bus 2-State Access 2 3-State Access 3+m Legend m : Number of wait states in an external device access. 5.5 5.5.1 Usage Notes Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. The same also applies when an interrupt source flag is cleared to 0. Figure 5-8 shows an example in which the TCIEV bit in the TPU's TIER0 register is cleared to 0. 117 TIER0 write cycle by CPU TCIV exception handling o Internal address bus TIER0 address Internal write signal TCIEV TCFV TCIV interrupt signal Figure 5-8 Contention between Interrupt Generation and Disabling The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. 5.5.2 Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.5.3 Times when Interrupts are Disabled There are times when interrupt acceptance is disabled by the interrupt controller. The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has updated the mask level with an LDC, ANDC, ORC, or XORC instruction. 118 5.5.4 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the move is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used. L1: EEPMOV.W MOV.W BNE R4,R4 L1 5.6 5.6.1 DTC Activation by Interrupt Overview The DTC can be activated by an interrupt. In this case, the following options are available: * Interrupt request to CPU * Activation request to DTC * Selection of a number of the above For details of interrupt requests that can be used with to activate the DTC, see section 8, Data Transfer Controller (DTC). 5.6.2 Block Diagram Figure 5-9 shows a block diagram of the DTC interrupt controller. 119 Interrupt request IRQ interrupt Interrupt source clear signal Selection circuit Select signal Clear signal DTCER DTC activation request vector number Control logic Clear signal DTC On-chip supporting module DTVECR SWDTE clear signal Determination of priority Interrupt controller CPU interrupt request vector number CPU I, I2 to I0 Figure 5-9 Interrupt Control for DTC 5.6.3 Operation The interrupt controller has three main functions in DTC control. (1) Selection of Interrupt Source: Interrupt sources can be specified as DTC activation requests or CPU interrupt requests by means of the DTCE bit of DTCERA to DTCERG in the DTC. After a DTC data transfer, the DTCE bit can be cleared to 0 and an interrupt request sent to the CPU in accordance with the specification of the DISEL bit of MRB in the DTC. When the DTC has performed the specified number of data transfers and the transfer counter value is zero, the DTCE bit is cleared to 0 and an interrupt request is sent to the CPU after the DTC data transfer. (2) Determination of Priority: The DTC activation source is selected in accordance with the default priority order, and is not affected by mask or priority levels. See section 8.3.3, DTC Vector Table, for the respective priorities. (3) Operation Order: If the same interrupt is selected as a DTC activation source and a CPU interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception handling. Table 5-11 summarizes interrupt source selection and interrupt source clearance control according to the settings of the DTCE bit of DTCERA to DTCERG in the DTC, and the DISEL bit of MRB in the DTC. 120 Table 5-11 Interrupt Source Selection and Clearing Control Settings DTC DTCE 0 1 DISEL * 0 1 O Interrupt Source Selection/Clearing Control DTC X X CPU Legend : The relevant interrupt is used. Interrupt source clearing is performed. (The CPU should clear the source flag in the interrupt handling routine.) O : The relevant interrupt is used. The interrupt source is not cleared. X : The relevant bit cannot be used. * : Don't care (4) Notes on Use: SCI and A/D converter interrupt sources are cleared when the DTC reads or writes to the prescribed register. 121 122 Section 6 PC Break Controller (PBC) 6.1 Overview The PC break controller (PBC) provides functions that simplify program debugging. Using these functions, it is easy to create a self-monitoring debugger, enabling programs to be debugged with the chip alone, without using an in-circuit emulator. Four break conditions can be set in the PBC: instruction fetch, data read, data write, and data read/write. 6.1.1 Features The PC break controller has the following features: * Two break channels (A and B) * The following can be set as break compare conditions: 24 address bits Bit masking possible Bus cycle Instruction fetch Data access: data read, data write, data read/write Bus master Either CPU or CPU/DTC can be selected * The timing of PC break exception handling after the occurrence of a break condition is as follows: Immediately before execution of the instruction fetched at the set address (instruction fetch) Immediately after execution of the instruction that accesses data at the set address (data access) * Module stop mode can be set The initial setting is for PBC operation to be halted. Register access is enabled by clearing module stop mode. 123 6.1.2 Block Diagram Figure 6-1 shows a block diagram of the PC break controller. BARA BCRA Output control Control logic Match signal Mask control Comparator Internal address Access status PC break interrupt Comparator Match signal Control logic Output control BCRB Mask control BARB Figure 6-1 Block Diagram of PC Break Controller 124 6.1.3 Register Configuration Table 6-1 shows the PC break controller registers. Table 6-1 PC Break Controller Registers Initial Value Name Break address register A Break address register B Break control register A Break control register B Module stop control register C Abbreviation BARA BARB BCRA BCRB MSTPCRC R/W R/W R/W R/(W)* R/(W)* R/W 2 2 Reset H'000000 H'000000 H'00 H'00 H'FF Manual Reset* 3 Address* 1 Retained Retained Retained Retained Retained H'FE00 H'FE04 H'FE08 H'FE09 H'FDEA Notes: *1 Lower 16 bits of the address. *2 Only 0 can be written, for flag clearing. *3 Not available in the H8S/2626 Series or H8S/2623 Series. 6.2 6.2.1 Bit Register Descriptions Break Address Register A (BARA) 31 -- *** 24 -- 23 22 21 20 19 18 17 16 *** 7 6 5 4 3 2 1 0 *** BAA BAA BAA BAA BAA BAA BAA BAA 23 22 21 20 19 18 17 16 *** BAA BAA BAA BAA BAA BAA BAA BAA 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Initial value Undefined -- R/W *** *** Unde- 0 0 0 0 0 0 0 0 fined -- R/W R/W R/W R/W R/W R/W R/W R/W *** *** R/W R/W R/W R/W R/W R/W R/W R/W BARA is a 32-bit readable/writable register that specifies the channel A break address. BAA23 to BAA0 are initialized to H'000000 by a reset and in hardware standby mode. Bits 31 to 24--Reserved: These bits return an undefined value if read, and cannot be modified. Bits 23 to 0--Break Address A23 to A0 (BAA23 to BAA0): These bits hold the channel A PC break address. 125 6.2.2 Break Address Register B (BARB) BARB is the channel B break address register. The bit configuration is the same as for BARA. 6.2.3 Bit Break Control Register A (BCRA) 7 CMFA 6 CDA 0 R/W 5 4 3 2 1 0 BIEA 0 R/W BAMRA2 BAMRA1 BAMRA0 CSELA1 CSELA0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial value R/W 0 R/(W)* Note: * Only 0 can be written, for flag clearing. BCRA is an 8-bit readable/writable register that controls channel A PC breaks. BCRA (1) selects the break condition bus master, (2) specifies bits subject to address comparison masking, and (3) specifies whether the break condition is applied to an instruction fetch or a data access. It also contains a condition match flag. BCRA is initialized to H'00 by a reset and in hardware standby mode. Bit 7--Condition Match Flag A (CMFA): Set to 1 when a break condition set for channel A is satisfied. This flag is not cleared to 0. Bit 7 CMFA 0 Description [Clearing condition] When 0 is written to CMFA after reading CMFA = 1 1 [Setting condition] When a condition set for channel A is satisfied (Initial value) Bit 6--CPU Cycle/DTC Cycle Select A (CDA): Selects the channel A break condition bus master. Bit 6 CDA 0 1 Description PC break is performed when CPU is bus master PC break is performed when CPU or DTC is bus master (Initial value) 126 Bits 5 to 3--Break Address Mask Register A2 to A0 (BAMRA2 to BAMRA0): These bits specify which bits of the break address (BAA23-BAA0) set in BARA are to be masked. Bit 5 Bit 4 Bit 3 BAMRA2 BAMRA1 BAMRA0 Description 0 0 0 1 1 0 1 1 0 0 1 1 0 1 All BARA bits are unmasked and included in break conditions (Initial value) BAA0 (lowest bit) is masked, and not included in break conditions BAA1-0 (lower 2 bits) are masked, and not included in break conditions BAA2-0 (lower 3 bits) are masked, and not included in break conditions BAA3-0 (lower 4 bits) are masked, and not included in break conditions BAA7-0 (lower 8 bits) are masked, and not included in break conditions BAA11-0 (lower 12 bits) are masked, and not included in break conditions BAA15-0 (lower 16 bits) are masked, and not included in break conditions Bits 2 and 1--Break Condition Select A (CSELA1, CSELA0): These bits select an instruction fetch, data read, data write, or data read/write cycle as the channel A break condition. Bit 2 CSELA1 0 Bit 1 CSELA0 0 1 1 0 1 Description Instruction fetch is used as break condition Data read cycle is used as break condition Data write cycle is used as break condition Data read/write cycle is used as break condition (Initial value) Bit 0--Break Interrupt Enable A (BIEA): Enables or disables channel A PC break interrupts. Bit 0 BIEA 0 1 Description PC break interrupts are disabled PC break interrupts are enabled (Initial value) 127 6.2.4 Break Control Register B (BCRB) BCRB is the channel B break control register. The bit configuration is the same as for BCRA. 6.2.5 Bit Initial value R/W Module Stop Control Register C (MSTPCRC) 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 MSTPCRC is an 8-bit readable/writable register that performs module stop mode control. When the MSTPC4 bit is set to 1, PC break controller operation is stopped at the end of the bus cycle, and module stop mode is entered. Register read/write accesses are not possible in module stop mode. For details, see sections 21A.5, 21B.5, Module Stop Mode. MSTPCRC is initialized to H'FF by a power on reset and in hardware standby mode. It is not initialized in software standby mode. Bit 4--Module Stop (MSTPC4): Specifies the PC break controller module stop mode. Bit 4 MSTPC4 0 1 Description PC break controller module stop mode is cleared PC break controller module stop mode is set (Initial value) 128 6.3 Operation The operation flow from break condition setting to PC break interrupt exception handling is shown in sections 6.3.1, PC Break Interrupt Due to Instruction Fetch and 6.3.2, PC Break Interrupt Due to Data Access, taking the example of channel A. 6.3.1 PC Break Interrupt Due to Instruction Fetch (1) Initial settings Set the break address in BARA. For a PC break caused by an instruction fetch, set the address of the first instruction byte as the break address. Set the break conditions in BCRA. BCRA bit 6 (CDA): With a PC break caused by an instruction fetch, the bus master must be the CPU. Set 0 to select the CPU. BCRA bits 5-3 (BAMA2-0): Set the address bits to be masked. BCRA bits 2-1 (CSELA1-0): Set 00 to specify an instruction fetch as the break condition. BCRA bit 0 (BIEA): Set to 1 to enable break interrupts. (2) Satisfaction of break condition When the instruction at the set address is fetched, a PC break request is generated immediately before execution of the fetched instruction, and the condition match flag (CMFA) is set. (3) Interrupt handling After priority determination by the interrupt controller, PC break interrupt exception handling is started. 6.3.2 PC Break Interrupt Due to Data Access (1) Initial settings Set the break address in BARA. For a PC break caused by a data access, set the target ROM, RAM, I/O, or external address space address as the break address. Stack operations and branch address reads are included in data accesses. Set the break conditions in BCRA. BCRA bit 6 (CDA): Select the bus master. BCRA bits 5-3 (BAMA2-0): Set the address bits to be masked. BCRA bits 2-1 (CSELA1-0): Set 01, 10, or 11 to specify data access as the break condition. BCRA bit 0 (BIEA): Set to 1 to enable break interrupts. 129 (2) Satisfaction of break condition After execution of the instruction that performs a data access on the set address, a PC break request is generated and the condition match flag (CMFA) is set. (3) Interrupt handling After priority determination by the interrupt controller, PC break interrupt exception handling is started. 6.3.3 Notes on PC Break Interrupt Handling (1) The PC break interrupt is shared by channels A and B. The channel from which the request was issued must be determined by the interrupt handler. (2) The CMFA and CMFB flags are not cleared to 0, so 0 must be written to CMFA or CMFB after first reading the flag while it is set to 1. If the flag is left set to 1, another interrupt will be requested after interrupt handling ends. (3) A PC break interrupt generated when the DTC is the bus master is accepted after the bus has been transferred to the CPU by the bus controller. 6.3.4 Operation in Transitions to Power-Down Modes The operation when a PC break interrupt is set for an instruction fetch at the address after a SLEEP instruction is shown below. (1) When the SLEEP instruction causes a transition from high-speed (medium-speed) mode to sleep mode, or from subactive mode to subsleep mode: After execution of the SLEEP instruction, a transition is not made to sleep mode or subsleep mode, and PC break interrupt handling is executed. After execution of PC break interrupt handling, the instruction at the address after the SLEEP instruction is executed (figure 6-2 (A)). (2) When the SLEEP instruction causes a transition from high-speed (medium-speed) mode to subactive mode: After execution of the SLEEP instruction, a transition is made to subactive mode via direct transition exception handling. After the transition, PC break interrupt handling is executed, then the instruction at the address after the SLEEP instruction is executed (figure 6-2 (B)) (Supported only in the H8S/2626 Series). (3) When the SLEEP instruction causes a transition from subactive mode to high-speed (mediumspeed) mode: 130 After execution of the SLEEP instruction, and following the clock oscillation settling time, a transition is made to high-speed (medium-speed) mode via direct transition exception handling. After the transition, PC break interrupt handling is executed, then the instruction at the address after the SLEEP instruction is executed (figure 6-2 (C)) (Supported only in the H8S/2626 Series). (4) When the SLEEP instruction causes a transition to software standby mode or watch mode: After execution of the SLEEP instruction, a transition is made to the respective mode, and PC break interrupt handling is not executed. However, the CMFA or CMFB flag is set (figure 6-2 (D)). SLEEP instruction execution SLEEP instruction execution SLEEP instruction execution SLEEP instruction execution PC break exception handling System clock subclock Subclock system clock, oscillation settling time Transition to respective mode (D) Execution of instruction after sleep instruction (A) Direct transition exception handling Subactive mode Direct transition exception handling High-speed (medium-speed) mode PC break exception handling PC break exception handling Execution of instruction after sleep instruction (B)* Execution of instruction after sleep instruction (C)* Note: * Supported only in the H8S/2626 Series. Figure 6-2 Operation in Power-Down Mode Transitions 6.3.5 PC Break Operation in Continuous Data Transfer If a PC break interrupt is generated when the following operations are being performed, exception handling is executed on completion of the specified transfer. (1) When a PC break interrupt is generated at the transfer address of an EEPMOV.B instruction: PC break exception handling is executed after all data transfers have been completed and the EEPMOV.B instruction has ended. (2) When a PC break interrupt is generated at a DTC transfer address: PC break exception handling is executed after the DTC has completed the specified number of data transfers, or after data for which the DISEL bit is set to 1 has been transferred. 131 6.3.6 When Instruction Execution is Delayed by One State Caution is required in the following cases, as instruction execution is one state later than usual. (1) When the PBC is enabled (i.e. when the break interrupt enable bit is set to 1), execution of a one-word branch instruction (Bcc d:8, BSR, JSR, JMP, TRAPA, RTE, or RTS) located in onchip ROM or RAM is always delayed by one state. (2) When break interruption by instruction fetch is set, the set address indicates on-chip ROM or RAM space, and that address is used for data access, the instruction that executes the data access is one state later than in normal operation. (3) When break interruption by instruction fetch is set and a break interrupt is generated, if the executing instruction immediately preceding the set instruction has one of the addressing modes shown below, and that address indicates on-chip ROM or RAM, and that address is used for data access, the instruction will be one state later than in normal operation. @ERn, @(d:16,ERn), @(d:32,ERn), @-ERn/ERn+, @aa:8, @aa:24, @aa:32, @(d:8,PC), @(d:16,PC), @@aa:8 (4) When break interruption by instruction fetch is set and a break interrupt is generated, if the executing instruction immediately preceding the set instruction is NOP or SLEEP, or has #xx,Rn as its addressing mode, and that instruction is located in on-chip ROM or RAM, the instruction will be one state later than in normal operation. 132 6.3.7 Additional Notes (1) When a PC break is set for an instruction fetch at the address following a BSR, JSR, JMP, TRAPA, RTE, or RTS instruction: Even if the instruction at the address following a BSR, JSR, JMP, TRAPA, RTE, or RTS instruction is fetched, it is not executed, and so a PC break interrupt is not generated by the instruction fetch at the next address. (2) When the I bit is set by an LDC, ANDC, ORC, or XORC instruction, a PC break interrupt becomes valid two states after the end of the executing instruction. If a PC break interrupt is set for the instruction following one of these instructions, since interrupts, including NMI, are disabled for a 3-state period in the case of LDC, ANDC, ORC, and XORC, the next instruction is always executed. For details, see section 5, Interrupt Controller. (3) When a PC break is set for an instruction fetch at the address following a Bcc instruction: A PC break interrupt is generated if the instruction at the next address is executed in accordance with the branch condition, but is not generated if the instruction at the next address is not executed. (4) When a PC break is set for an instruction fetch at the branch destination address of a Bcc instruction: A PC break interrupt is generated if the instruction at the branch destination is executed in accordance with the branch condition, but is not generated if the instruction at the branch destination is not executed. 133 134 Section 7 Bus Controller 7.1 Overview The H8S/2626 Series and H8S/2623 Series have an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily. The bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: the CPU and data transfer controller (DTC). 7.1.1 Features The features of the bus controller are listed below. * Manages external address space in area units Manages the external space as 8 areas of 2 Mbytes Bus specifications can be set independently for each area Burst ROM interface can be set * Basic bus interface 8-bit access or 16-bit access can be selected for each area 2-state access or 3-state access can be selected for each area Program wait states can be inserted for each area * Burst ROM interface Burst ROM interface can be set for area 0 Choice of 1- or 2-state burst access * Idle cycle insertion An idle cycle can be inserted in case of an external read cycle between different areas An idle cycle can be inserted in case of an external write cycle immediately after an external read cycle * Write buffer functions External write cycle and internal access can be executed in parallel * Bus arbitration function Includes a bus arbiter that arbitrates bus mastership among the CPU and DTC 135 * Other features External bus release function 7.1.2 Block Diagram Figure 7-1 shows a block diagram of the bus controller. Area decoder Internal address bus ABWCR External bus control signals ASTCR BCRH BCRL BACK BREQO Bus controller Internal data bus BREQ Internal control signals Bus mode signal WAIT Wait controller WCRH WCRL CPU bus request signal DTC bus request signal Bus arbiter CPU bus acknowledge signal DTC bus acknowledge signal Legend ABWCR: ASTCR: BCRH: BCRL: WCRH: WCRL: Bus width control register Access state control register Bus control register H Bus control register L Wait control register H Wait control register L Figure 7-1 Block Diagram of Bus Controller 136 7.1.3 Pin Configuration Table 7-1 summarizes the pins of the bus controller. Table 7-1 Name Address strobe Read High write Bus Controller Pins Symbol AS RD HWR I/O Output Output Output Function Strobe signal indicating that address output on address bus is enabled. Strobe signal indicating that external space is being read. Strobe signal indicating that external space is to be written, and upper half (D15 to D8) of data bus is enabled. Strobe signal indicating that external space is to be written, and lower half (D7 to D0) of data bus is enabled. Wait request signal when accessing external 3-state access space. Request signal that releases bus to external device. Acknowledge signal indicating that bus has been released. External bus request signal used when internal bus master accesses external space when external bus is released. Low write Wait Bus request Bus request acknowledge Bus request output LWR WAIT BREQ BACK BREQO Output Input Input Output Output 137 7.1.4 Register Configuration Table 7-2 summarizes the registers of the bus controller. Table 7-2 Bus Controller Registers Initial Value Name Bus width control register Access state control register Wait control register H Wait control register L Bus control register H Bus control register L Pin function control register Abbreviation ABWCR ASTCR WCRH WCRL BCRH BCRL PFCR R/W R/W R/W R/W R/W R/W R/W R/W Reset Manual Reset* 3 Address* 1 H'FED0 H'FED1 H'FED2 H'FED3 H'FED4 H'FED5 H'FDEB H'FF/H'00* 2 Retained H'FF H'FF H'FF H'D0 H'08 H'0D/H'00 Retained Retained Retained Retained Retained Retained Notes: *1 Lower 16 bits of the address. *2 Determined by the MCU operating mode. *3 Not available in the H8S/2623 Series. 138 7.2 7.2.1 Bit Register Descriptions Bus Width Control Register (ABWCR) : 7 ABW7 6 ABW6 1 R/W 0 R/W 5 ABW5 1 R/W 0 R/W 4 ABW4 1 R/W 0 R/W 3 ABW3 1 R/W 0 R/W 2 ABW2 1 R/W 0 R/W 1 ABW1 1 R/W 0 R/W 0 ABW0 1 R/W 0 R/W Modes 5 to 7 Initial value : R/W Mode 4 Initial value : R/W : : 1 R/W 0 R/W ABWCR is an 8-bit readable/writable register that designates each area for either 8-bit access or 16-bit access. ABWCR sets the data bus width for the external memory space. The bus width for on-chip memory and internal I/O registers is fixed regardless of the settings in ABWCR. After a reset and in hardware standby mode, ABWCR is initialized to H'FF in modes 5 to 7, and to H'00 in mode 4. It is not initialized in software standby mode. Bits 7 to 0--Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select whether the corresponding area is to be designated for 8-bit access or 16-bit access. Bit n ABWn 0 1 Description Area n is designated for 16-bit access Area n is designated for 8-bit access (n = 7 to 0) 139 7.2.2 Bit Access State Control Register (ASTCR) : 7 AST7 1 R/W 6 AST6 1 R/W 5 AST5 1 R/W 4 AST4 1 R/W 3 AST3 1 R/W 2 AST2 1 R/W 1 AST1 1 R/W 0 AST0 1 R/W Initial value : R/W : ASTCR is an 8-bit readable/writable register that designates each area as either a 2-state access space or a 3-state access space. ASTCR sets the number of access states for the external memory space. The number of access states for on-chip memory and internal I/O registers is fixed regardless of the settings in ASTCR. ASTCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 0--Area 7 to 0 Access State Control (AST7 to AST0): These bits select whether the corresponding area is to be designated as a 2-state access space or a 3-state access space. Wait state insertion is enabled or disabled at the same time. Bit n ASTn 0 1 Description Area n is designated for 2-state access Wait state insertion in area n external space is disabled Area n is designated for 3-state access Wait state insertion in area n external space is enabled (Initial value) (n = 7 to 0) 140 7.2.3 Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. Program waits are not inserted in the case of on-chip memory or internal I/O registers. WCRH and WCRL are initialized to H'FF by a reset and in hardware standby mode. They are not initialized in software standby mode. (1) WCRH Bit : 7 W71 Initial value : R/W : 1 R/W 6 W70 1 R/W 5 W61 1 R/W 4 W60 1 R/W 3 W51 1 R/W 2 W50 1 R/W 1 W41 1 R/W 0 W40 1 R/W Bits 7 and 6--Area 7 Wait Control 1 and 0 (W71, W70): These bits select the number of program wait states when area 7 in external space is accessed while the AST7 bit in ASTCR is set to 1. Bit 7 W71 0 Bit 6 W70 0 1 1 0 1 Description Program wait not inserted when external space area 7 is accessed 1 program wait state inserted when external space area 7 is accessed 2 program wait states inserted when external space area 7 is accessed 3 program wait states inserted when external space area 7 is accessed (Initial value) Bits 5 and 4--Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is set to 1. Bit 5 W61 0 Bit 4 W60 0 1 1 0 1 Description Program wait not inserted when external space area 6 is accessed 1 program wait state inserted when external space area 6 is accessed 2 program wait states inserted when external space area 6 is accessed 3 program wait states inserted when external space area 6 is accessed (Initial value) 141 Bits 3 and 2--Area 5 Wait Control 1 and 0 (W51, W50): These bits select the number of program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set to 1. Bit 3 W51 0 Bit 2 W50 0 1 1 0 1 Description Program wait not inserted when external space area 5 is accessed 1 program wait state inserted when external space area 5 is accessed 2 program wait states inserted when external space area 5 is accessed 3 program wait states inserted when external space area 5 is accessed (Initial value) Bits 1 and 0--Area 4 Wait Control 1 and 0 (W41, W40): These bits select the number of program wait states when area 4 in external space is accessed while the AST4 bit in ASTCR is set to 1. Bit 1 W41 0 Bit 0 W40 0 1 1 0 1 Description Program wait not inserted when external space area 4 is accessed 1 program wait state inserted when external space area 4 is accessed 2 program wait states inserted when external space area 4 is accessed 3 program wait states inserted when external space area 4 is accessed (Initial value) 142 (2) WCRL Bit : 7 W31 Initial value : R/W : 1 R/W 6 W30 1 R/W 5 W21 1 R/W 4 W20 1 R/W 3 W11 1 R/W 2 W10 1 R/W 1 W01 1 R/W 0 W00 1 R/W Bits 7 and 6--Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set to 1. Bit 7 W31 0 Bit 6 W30 0 1 1 0 1 Description Program wait not inserted when external space area 3 is accessed 1 program wait state inserted when external space area 3 is accessed 2 program wait states inserted when external space area 3 is accessed 3 program wait states inserted when external space area 3 is accessed (Initial value) Bits 5 and 4--Area 2 Wait Control 1 and 0 (W21, W20): These bits select the number of program wait states when area 2 in external space is accessed while the AST2 bit in ASTCR is set to 1. Bit 5 W21 0 Bit 4 W20 0 1 1 0 1 Description Program wait not inserted when external space area 2 is accessed 1 program wait state inserted when external space area 2 is accessed 2 program wait states inserted when external space area 2 is accessed 3 program wait states inserted when external space area 2 is accessed (Initial value) 143 Bits 3 and 2--Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set to 1. Bit 3 W11 0 Bit 2 W10 0 1 1 0 1 Description Program wait not inserted when external space area 1 is accessed 1 program wait state inserted when external space area 1 is accessed 2 program wait states inserted when external space area 1 is accessed 3 program wait states inserted when external space area 1 is accessed (Initial value) Bits 1 and 0--Area 0 Wait Control 1 and 0 (W01, W00): These bits select the number of program wait states when area 0 in external space is accessed while the AST0 bit in ASTCR is set to 1. Bit 1 W01 0 Bit 0 W00 0 1 1 0 1 Description Program wait not inserted when external space area 0 is accessed 1 program wait state inserted when external space area 0 is accessed 2 program wait states inserted when external space area 0 is accessed 3 program wait states inserted when external space area 0 is accessed (Initial value) 144 7.2.4 Bit Bus Control Register H (BCRH) : 7 ICIS1 1 R/W 6 ICIS0 1 R/W 5 0 R/W 4 1 R/W 3 0 R/W 2 -- 0 R/W 1 -- 0 R/W 0 -- 0 R/W BRSTRM BRSTS1 BRSTS0 Initial value : R/W : BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle insertion, and the memory interface for area 0. BCRH is initialized to H'D0 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7--Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read cycles are performed in different areas. Bit 7 ICIS1 0 1 Description Idle cycle not inserted in case of successive external read cycles in different areas Idle cycle inserted in case of successive external read cycles in different areas (Initial value) Bit 6--Idle Cycle Insert 0 (ICIS0): Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read and external write cycles are performed . Bit 6 ICIS0 0 1 Description Idle cycle not inserted in case of successive external read and external write cycles Idle cycle inserted in case of successive external read and external write cycles (Initial value) Bit 5--Burst ROM Enable (BRSTRM): Selects whether area 0 is used as a burst ROM interface. Bit 5 BRSTRM 0 1 Description Area 0 is basic bus interface Area 0 is burst ROM interface (Initial value) 145 Bit 4--Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM interface. Bit 4 BRSTS1 0 1 Description Burst cycle comprises 1 state Burst cycle comprises 2 states (Initial value) Bit 3--Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a burst ROM interface burst access. Bit 3 BRSTS0 0 1 Description Max. 4 words in burst access Max. 8 words in burst access (Initial value) Bits 2 to 0--Reserved: Only 0 should be written to these bits. 146 7.2.5 Bit Bus Control Register L (BCRL) : 7 BRLE 0 R/W 6 BREQOE 0 R/W 5 -- 0 -- 4 -- 0 R/W 3 -- 1 R/W 2 -- 0 R/W 1 WDBE 0 R/W 0 WAITE 0 R/W Initial value : R/W : BCRL is an 8-bit readable/writable register that performs selection of the external bus-released state protocol, enabling or disabling of the write data buffer function, and enabling or disabling of WAIT pin input. BCRL is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7--Bus Release Enable (BRLE): Enables or disables external bus release. Bit 7 BRLE 0 Description External bus release is disabled. BREQ, BACK, and BREQO can be used as I/O ports. (Initial value) External bus release is enabled. 1 Bit 6--BREQO Pin Enable (BREQOE): Outputs a signal that requests the external bus master to drop the bus request signal (BREQ) in the external bus release state, when an internal bus master performs an external space access, or when a refresh request is generated. Bit 6 BREQOE 0 1 Description BREQO output disabled. BREQO can be used as I/O port. BREQO output enabled. (Initial value) Bit 5--Reserved: This bit cannot be modified and is always read as 0. Bit 4--Reserved: Only 0 should be written to this bit. Bit 3--Reserved: Only 1 should be written to this bit. Bit 2--Reserved: Only 0 should be written to this bit. 147 Bit 1--Write Data Buffer Enable (WDBE): Selects whether or not the write buffer function is used for an external write cycle. Bit 1 WDBE 0 1 Description Write data buffer function not used Write data buffer function used (Initial value) Bit 0--WAIT Pin Enable (WAITE): Selects enabling or disabling of wait input by the WAIT pin. Bit 0 WAITE 0 1 Description Wait input by WAIT pin disabled. WAIT pin can be used as I/O port. Wait input by WAIT pin enabled (Initial value) 7.2.6 Bit Pin Function Control Register (PFCR) : 7 -- 0 R/W 6 -- 0 R/W 5 BUZZE 0 R/W 4 -- 0 R/W 3 AE3 1/0 R/W 2 AE2 1/0 R/W 1 AE1 0 R/W 0 AE0 1/0 R/W Initial value : R/W : PFCR is an 8-bit readable/writable register that performs address output control in external expanded mode. PFCR is initialized to H'0D/H'00 by a reset and in hardware standby mode. It retains its previous state in software standby mode. Bits 7 and 6--Reserved: Only 0 should be written to these bits. Bit 5--BUZZ Output Enable (BUZZE): Enables or disables BUZZ output from the PF1 pin. For details, see section 12.2.4, Pin Function Control Register (PFCR). Bit 4--Reserved: Only 0 should be written to this bit. Bits 3 to 0--Address Output Enable 3 to 0 (AE3 to AE0): These bits select enabling or disabling of address outputs A8 to A23 in ROMless expanded mode and modes with ROM. When a pin is enabled for address output, the address is output regardless of the corresponding DDR setting. When a pin is disabled for address output, it becomes an output port when the corresponding DDR bit is set to 1. 148 Bit 3 AE3 0 Bit 2 AE2 0 Bit 1 AE1 0 Bit 0 AE0 0 1 Description A8-A23 address output disabled (Initial value*) A8 address output enabled; A9-A23 address output disabled A8, A9 address output enabled; A10-A23 address output disabled A8-A10 address output enabled; A11-A23 address output disabled A8-A11 address output enabled; A12-A23 address output disabled A8-A12 address output enabled; A13-A23 address output disabled A8-A13 address output enabled; A14-A23 address output disabled A8-A14 address output enabled; A15-A23 address output disabled A8-A15 address output enabled; A16-A23 address output disabled A8-A16 address output enabled; A17-A23 address output disabled A8-A17 address output enabled; A18-A23 address output disabled A8-A18 address output enabled; A19-A23 address output disabled A8-A19 address output enabled; A20-A23 address output disabled A8-A20 address output enabled; A21-A23 address output disabled (Initial value*) A8-A21 address output enabled; A22, A23 address output disabled A8-A23 address output enabled 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Note: * In expanded mode with ROM, bits AE3 to AE0 are initialized to B'0000. In ROMless expanded mode, bits AE3 to AE0 are initialized to B'1101. Address pins A0 to A7 are made address outputs by setting the corresponding DDR bits to 1. 149 7.3 7.3.1 Overview of Bus Control Area Partitioning In advanced mode, the bus controller partitions the 16 Mbytes address space into eight areas, 0 to 7, in 2-Mbyte units, and performs bus control for external space in area units. In normal mode*, it controls a 64-kbyte address space comprising part of area 0. Figure 7-2 shows an outline of the memory map. Note: * Not available in the H8S/2626 Series or H8S/2623 Series. H'000000 Area 0 (2 Mbytes) H'1FFFFF H'200000 Area 1 (2 Mbytes) H'3FFFFF H'400000 Area 2 (2 Mbytes) H'5FFFFF H'600000 Area 3 (2 Mbytes) H'7FFFFF H'800000 Area 4 (2 Mbytes) H'9FFFFF H'A00000 Area 5 (2 Mbytes) H'BFFFFF H'C00000 Area 6 (2 Mbytes) H'DFFFFF H'E00000 Area 7 (2 Mbytes) H'FFFFFF (1) Advanced mode H'0000 H'FFFF (2) Normal mode* Note: * Not available in the H8S/2626 Series or H8S/2623 Series. Figure 7-2 Overview of Area Partitioning 150 7.3.2 Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller. (1) Bus Width: A bus width of 8 or 16 bits can be selected with ADWCR. An area for which an 8-bit bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected functions as a16-bit access space. If all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16-bit access, 16-bit bus mode is set. When the burst ROM interface is designated, 16-bit bus mode is always set. (2) Number of Access States: Two or three access states can be selected with ASTCR. An area for which 2-state access is selected functions as a 2-state access space, and an area for which 3state access is selected functions as a 3-state access space. With the burst ROM interface, the number of access states may be determined without regard to ASTCR. When 2-state access space is designated, wait insertion is disabled. (3) Number of Program Wait States: When 3-state access space is designated by ASTCR, the number of program wait states to be inserted automatically is selected with WCRH and WCRL. From 0 to 3 program wait states can be selected. Table 7-3 shows the bus specifications for each basic bus interface area. 151 Table 7-3 ABWCR ABWn 0 Bus Specifications for Each Area (Basic Bus Interface) ASTCR ASTn 0 1 WCRH, WCRL Wn1 -- 0 Wn0 -- 0 1 1 0 1 Bus Specifications (Basic Bus Interface) Bus Width 16 Program Wait Access States States 2 3 0 0 1 2 3 8 2 3 0 0 1 2 3 1 0 1 -- 0 -- 0 1 1 0 1 7.3.3 Memory Interfaces The H8S/2626 Series and H8S/2623 Series memory interfaces comprise a basic bus interface that allows direct connection or ROM, SRAM, and so on, and a burst ROM interface that allows direct connection of burst ROM. The memory interface can be selected independently for each area. An area for which the basic bus interface is designated functions as normal space, and an area for which the burst ROM interface is designated functions as burst ROM space. 152 7.3.4 Interface Specifications for Each Area The initial state of each area is basic bus interface, 3-state access space. The initial bus width is selected according to the operating mode. The bus specifications described here cover basic items only, and the sections on each memory interface (7.4, Basic Bus Interface, and 7.5, Burst ROM Interface) should be referred to for further details. Area 0: Area 0 includes on-chip ROM, and in ROM-disabled expansion mode, all of area 0 is external space. In ROM-enabled expansion mode, the space excluding on-chip ROM is external space. Either basic bus interface or burst ROM interface can be selected for area 0. Areas 1 to 6: In external expansion mode, all of areas 1 to 6 is external space. Only the basic bus interface can be used for areas 1 to 6. Area 7: Area 7 includes the on-chip RAM and internal I/O registers. In external expansion mode, the space excluding the on-chip RAM and internal I/O registers is external space. The on-chip RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes external space. Only the basic bus interface can be used for the area 7. 153 7.4 7.4.1 Basic Bus Interface Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 7-3). 7.4.2 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and when accessing external space, controls whether the upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space) and the data size. 8-Bit Access Space: Figure 7-3 illustrates data alignment control for the 8-bit access space. With the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of data that can be accessed at one time is one byte: a word transfer instruction is performed as two byte accesses, and a longword transfer instruction, as four byte accesses. Upper data bus Lower data bus D15 D8 D7 D0 Byte size 1st bus cycle 2nd bus cycle 1st bus cycle Longword size 2nd bus cycle 3rd bus cycle 4th bus cycle Word size Figure 7-3 Access Sizes and Data Alignment Control (8-Bit Access Space) 154 16-Bit Access Space: Figure 7-4 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword transfer instruction is executed as two word transfer instructions. In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. The upper data bus is used for an even address, and the lower data bus for an odd address. Lower data bus Upper data bus D15 D8 D7 D0 Byte size Byte size Word size Longword size 1st bus cycle 2nd bus cycle * Even address * Odd address Figure 7-4 Access Sizes and Data Alignment Control (16-Bit Access Space) 155 7.4.3 Valid Strobes Table 7-4 shows the data buses used and valid strobes for the access spaces. In a read, the RD signal is valid without discrimination between the upper and lower halves of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half. Table 7-4 Area 8-bit access space Data Buses Used and Valid Strobes Access Read/ Size Write Byte Read Write Read Address -- -- Even Odd Write Even Odd Word Read Write -- -- HWR LWR RD Valid Strobe RD HWR RD Valid Invalid Valid Hi-Z Valid Upper Data Bus (D15 to D8) Valid Lower data bus (D7 to D0) Invalid Hi-Z Invalid Valid Hi-Z Valid Valid Valid 16-bit access Byte space HWR, LWR Valid Notes: Hi-Z: High impedance. Invalid: Input state; input value is ignored. 156 7.4.4 Basic Timing 8-Bit 2-State Access Space: Figure 7-5 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is fixed high. Wait states cannot be inserted. Bus cycle T1 o T2 Address bus AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR Write D15 to D8 High Valid D7 to D0 High impedance Figure 7-5 Bus Timing for 8-Bit 2-State Access Space 157 8-Bit 3-State Access Space: Figure 7-6 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is fixed high. Wait states can be inserted. Bus cycle T1 o T2 T3 Address bus AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR Write D15 to D8 High Valid High impedance D7 to D0 Figure 7-6 Bus Timing for 8-Bit 3-State Access Space 158 16-Bit 2-State Access Space: Figures 7-7 to 7-9 show bus timings for a 16-bit 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states cannot be inserted. Bus cycle T1 o T2 Address bus AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR Write D15 to D8 High Valid D7 to D0 High impedance Figure 7-7 Bus Timing for 16-Bit 2-State Access Space (1) (Even Address Byte Access) 159 Bus cycle T1 o T2 Address bus AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 High impedance D7 to D0 Valid Figure 7-8 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access) 160 Bus cycle T1 o T2 Address bus AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Figure 7-9 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access) 161 16-Bit 3-State Access Space: Figures 7-10 to 7-12 show bus timings for a 16-bit 3-state access space. When a 16-bit access space is accessed , the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states can be inserted. Bus cycle T1 o T2 T3 Address bus AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR Write D15 to D8 High Valid High impedance D7 to D0 Figure 7-10 Bus Timing for 16-Bit 3-State Access Space (1) (Even Address Byte Access) 162 Bus cycle T1 o T2 T3 Address bus AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 High impedance D7 to D0 Valid Figure 7-11 Bus Timing for 16-Bit 3-State Access Space (2) (Odd Address Byte Access) 163 Bus cycle T1 o T2 T3 Address bus AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Figure 7-12 Bus Timing for 16-Bit 3-State Access Space (3) (Word Access) 164 7.4.5 Wait Control When accessing external space, the H8S/2626 Series or H8S/2623 Series can extend the bus cycle by inserting one or more wait states (Tw). There are two ways of inserting wait states: program wait insertion and pin wait insertion using the WAIT pin. Program Wait Insertion From 0 to 3 wait states can be inserted automatically between the T2 state and T3 state on an individual area basis in 3-state access space, according to the settings of WCRH and WCRL. Pin Wait Insertion Setting the WAITE bit in BCRL to 1 enables wait insertion by means of the WAIT pin. Program wait insertion is first carried out according to the settings in WCRH and WCRL. Then , if the WAIT pin is low at the falling edge of o in the last T2 or Tw state, a Tw state is inserted. If the WAIT pin is held low, Tw states are inserted until it goes high. This is useful when inserting four or more Tw states, or when changing the number of Tw states for different external devices. The WAITE bit setting applies to all areas. 165 Figure 7-13 shows an example of wait state insertion timing. By program wait T1 o T2 Tw By WAIT pin Tw Tw T3 WAIT Address bus AS RD Read Data bus Read data HWR, LWR Write Data bus Write data Note: indicates the timing of WAIT pin sampling. Figure 7-13 Example of Wait State Insertion Timing The settings after a reset are: 3-state access, 3 program wait state insertion, and WAIT input disabled. 166 7.5 7.5.1 Burst ROM Interface Overview With the H8S/2626 Series and H8S/2623 Series, external space area 0 can be designated as burst ROM space, and burst ROM interfacing can be performed. The burst ROM space interface enables 16-bit configuration ROM with burst access capability to be accessed at high speed. Area 0 can be designated as burst ROM space by means of the BRSTRM bit in BCRH. Consecutive burst accesses of a maximum of 4 words or 8 words can be performed for CPU instruction fetches only. One or two states can be selected for burst access. 7.5.2 Basic Timing The number of states in the initial cycle (full access) of the burst ROM interface is in accordance with the setting of the AST0 bit in ASTCR. Also, when the AST0 bit is set to 1, wait state insertion is possible. One or two states can be selected for the burst cycle, according to the setting of the BRSTS1 bit in BCRH. Wait states cannot be inserted. When area 0 is designated as burst ROM space, it becomes 16-bit access space regardless of the setting of the ABW0 bit in ABWCR. When the BRSTS0 bit in BCRH is cleared to 0, burst access of up to 4 words is performed; when the BRSTS0 bit is set to 1, burst access of up to 8 words is performed. The basic access timing for burst ROM space is shown in figures 7-14 (a) and (b). The timing shown in figure 7-14 (a) is for the case where the AST0 and BRSTS1 bits are both set to 1, and that in figure 7-14 (b) is for the case where both these bits are cleared to 0. 167 Full access T1 o T2 T3 T1 Burst access T2 T1 T2 Address bus Only lower address changed AS RD Data bus Read data Read data Read data Figure 7-14 (a) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1) 168 Full access T1 T2 Burst access T1 T1 o Address bus Only lower address changed AS RD Data bus Read data Read data Read data Figure 7-14 (b) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0) 7.5.3 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) of the burst ROM interface. See section 7.4.5, Wait Control. Wait states cannot be inserted in a burst cycle. 169 7.6 7.6.1 Idle Cycle Operation When the H8S/2626 Series or H8S/2623 Series accesses external space , it can insert a 1-state idle cycle (TI) between bus cycles in the following two cases: (1) when read accesses between different areas occur consecutively, and (2) when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, with a long output floating time, and high-speed memory, I/O interfaces, and so on. (1) Consecutive Reads between Different Areas If consecutive reads between different areas occur while the ICIS1 bit in BCRH is set to 1, an idle cycle is inserted at the start of the second read cycle. Figure 7-15 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM, each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted, and a data collision is prevented. Bus cycle A T1 o Address bus CS* (area A) CS* (area B) RD Data bus T2 T3 Bus cycle B T1 T2 o Address bus CS* (area A) Bus cycle A T1 T2 T3 Bus cycle B TI T1 T2 ; CS* (area B) RD Data bus Data collision (b) Idle cycle inserted (Initial value ICIS1 = 1) Long output floating time (a) Idle cycle not inserted (ICIS1 = 0) Note: * The CS signals are generated off-chip. Figure 7-15 Example of Idle Cycle Operation (1) 170 (2) Write after Read If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle cycle is inserted at the start of the write cycle. Figure 7-16 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented. Bus cycle A T1 o Address bus CS* (area A) CS* (area B) RD T2 T3 Bus cycle B T1 T2 o Address bus CS* (area A) CS* (area B) RD Bus cycle A T1 T2 T3 Bus cycle B TI T1 T2 Possibility of overlap between CS (area B) and RD (a) Idle cycle not inserted (ICIS1 = 0) (b) Idle cycle inserted (Initial value ICIS1 = 1) Note: * The CS signals are generated off-chip. Figure 7-16 Example of Idle Cycle Operation (2) 171 7.6.2 Pin States in Idle Cycle Table 7-5 shows pin states in an idle cycle. Table 7-5 Pins A23 to A0 D15 to D0 AS RD HWR LWR Pin States in Idle Cycle Pin State Contents of next bus cycle High impedance High High High High 172 7.7 Write Data Buffer Function The H8S/2626 Series and H8S/2623 Series have a write data buffer function in the external data bus. Using the write data buffer function enables external writes to be executed in parallel with internal accesses. The write data buffer function is made available by setting the WDBE bit in BCRL to 1. Figure 7-17 shows an example of the timing when the write data buffer function is used. When this function is used, if an external write continues for 2 states or longer, and there is an internal access next, only an external write is executed in the first state, but from the next state onward an internal access (on-chip memory or internal I/O register read/write) is executed in parallel with the external write rather than waiting until it ends. On-chip memory read Internal I/O register read External write cycle T1 T2 TW TW T3 Internal address bus Internal memory Internal read signal Internal I/O register address A23 to A0 External space write External address HWR, LWR D15 to D0 Figure 7-17 Example of Timing when Write Data Buffer Function is Used 173 7.8 7.8.1 Bus Release Overview The H8S/2626 Series and H8S/2623 Series can release the external bus in response to a bus request from an external device. In the external bus released state, the internal bus master continues to operate as long as there is no external access. If an internal bus master wants to make an external access in the external bus released state, it can issue a bus request off-chip. 7.8.2 Operation In external expansion mode, the bus can be released to an external device by setting the BRLE bit in BCRL to 1. Driving the BREQ pin low issues an external bus request to the H8S/2626 Series or H8S/2623 Series. When the BREQ pin is sampled, at the prescribed timing the BACK pin is driven low, and the address bus, data bus, and bus control signals are placed in the highimpedance state, establishing the external bus-released state. In the external bus released state, an internal bus master can perform accesses using the internal bus. When an internal bus master wants to make an external access, it temporarily defers activation of the bus cycle, and waits for the bus request from the external bus master to be dropped. If the BREQOE bit in BCRL is set to 1, when an internal bus master wants to make an external access in the external bus released state, the BREQO pin is driven low and a request can be made off-chip to drop the bus request. When the BREQ pin is driven high, the BACK pin is driven high at the prescribed timing and the external bus released state is terminated. If an external bus release request and internal bus master external access occur simultaneously, the order of priority is as follows: (High) External bus release > Internal bus master external access (Low) 174 7.8.3 Pin States in External Bus Released State Table 7-6 shows pin states in the external bus released state. Table 7-6 Pins A23 to A0 D15 to D0 AS RD HWR LWR Pin States in Bus Released State Pin State High impedance High impedance High impedance High impedance High impedance High impedance 175 7.8.4 Transition Timing Figure 7-18 shows the timing for transition to the bus-released state. CPU cycle CPU cycle T0 o T1 T2 External bus released state High impedance Address bus Address High impedance Data bus High impedance AS High impedance RD High impedance HWR, LWR BREQ BACK BREQO * Minimum 1 state [1] [2] [3] [4] [5] [6] [1] [2] [3] [4] [5] [6] Low level of BREQ pin is sampled at rise of T2 state. BACK pin is driven low at end of CPU read cycle, releasing bus to external bus master. BREQ pin state is still sampled in external bus released state. High level of BREQ pin is sampled. BACK pin is driven high, ending bus release cycle. BREQO signal goes high 1.5 clocks after BACK signal goes high. Note: * Output only when BREQOE is set to 1. Figure 7-18 Bus-Released State Transition Timing 176 7.8.5 Usage Note If MSTPCR is set to H'FFFFFF or H'EFFFFF and a transition is made to sleep mode, the external bus release function will halt. Therefore, these values should not be set in MSTPCR if the external bus release function is to be used in sleep mode. 7.9 7.9.1 Bus Arbitration Overview The H8S/2626 Series and H8S/2623 Series have a bus arbiter that arbitrates bus master operations. There are two bus masters, the CPU and DTC, which perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal. The selected bus master then takes possession of the bus and begins its operation. 7.9.2 Operation The bus arbiter detects the bus masters' bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master making the request. If there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. The order of priority of the bus masters is as follows: (High) DTC > CPU (Low) An internal bus access by an internal bus master, and external bus release, can be executed in parallel. In the event of simultaneous external bus release request, and internal bus master external access request generation, the order of priority is as follows: (High) External bus release > Internal bus master external access (Low) 177 7.9.3 Bus Transfer Timing Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. There are specific times at which each bus master can relinquish the bus. CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DTC, the bus arbiter transfers the bus to the bus master that issued the request. The timing for transfer of the bus is as follows: * The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in discrete operations, as in the case of a longword-size access, the bus is not transferred between the operations. See Appendix A.5, Bus States During Instruction Execution, for timings at which the bus is not transferred. * If the CPU is in sleep mode, it transfers the bus immediately. DTC: The DTC sends the bus arbiter a request for the bus when an activation request is generated. The DTC can release the bus after a vector read, a register information read (3 states), a single data transfer, or a register information write (3 states). It does not release the bus during a register information read (3 states), a single data transfer, or a register information write (3 states). 7.10 Resets and the Bus Controller In a reset, the H8S/2626 Series or H8S/2623 Series, including the bus controller, enters the reset state at that point, and an executing bus cycle is discontinued. 178 Section 8 Data Transfer Controller (DTC) 8.1 Overview The H8S/2626 Series and H8S/2623 Series include a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. 8.1.1 Features The features of the DTC are: * Transfer possible over any number of channels Transfer information is stored in memory One activation source can trigger a number of data transfers (chain transfer) * Wide range of transfer modes Normal, repeat, and block transfer modes available Incrementing, decrementing, and fixing of source and destination addresses can be selected * Direct specification of 16-Mbyte address space possible 24-bit transfer source and destination addresses can be specified * Transfer can be set in byte or word units * A CPU interrupt can be requested for the interrupt that activated the DTC An interrupt request can be issued to the CPU after one data transfer ends An interrupt request can be issued to the CPU after the specified data transfers have completely ended * Activation by software is possible * Module stop mode can be set The initial setting enables DTC registers to be accessed. DTC operation is halted by setting module stop mode. 179 8.1.2 Block Diagram Figure 8-1 shows a block diagram of the DTC. The DTC's register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register information. Note: * When the DTC is used, the RAME bit in SYSCR must be set to 1. Internal address bus Interrupt controller DTC Register information On-chip RAM CPU interrupt request Legend MRA, MRB CRA, CRB SAR DAR DTCERA to DTCERG DTVECR DTC service request : DTC mode registers A and B : DTC transfer count registers A and B : DTC source address register : DTC destination address register : DTC enable registers A to G : DTC vector register Figure 8-1 Block Diagram of DTC 180 MRA MRB CRA CRB DAR SAR Interrupt request Control logic DTCERA to DTCERG DTVECR Internal data bus 8.1.3 Register Configuration Table 8-1 summarizes the DTC registers. Table 8-1 Name DTC mode register A DTC mode register B DTC source address register DTC destination address register DTC transfer count register A DTC transfer count register B DTC enable registers DTC vector register Module stop control register DTC Registers Abbreviation MRA MRB SAR DAR CRA CRB DTCER DTVECR MSTPCRA R/W --* 2 --* 2 --* 2 --* 2 --* 2 --* 2 R/W R/W R/W Initial Value Undefined Undefined Undefined Undefined Undefined Undefined H'00 H'00 H'3F Address* 1 --* 3 --* 3 --* 3 --* 3 --* 3 --* 3 H'FE16 to H'FE1C H'FE1F H'FDE8 Notes: *1 Lower 16 bits of the address. *2 Registers within the DTC cannot be read or written to directly. *3 Register information is located in on-chip RAM addresses H'EBC0 to H'EFBF. It cannot be located in external memory space. When the DTC is used, the RAME bit in SYSCR must be set to 1. 181 8.2 8.2.1 Bit Register Descriptions DTC Mode Register A (MRA) : 7 SM1 Undefined -- 6 SM0 Undefined -- 5 DM1 Undefined -- 4 DM0 Undefined -- 3 MD1 Undefined -- 2 MD0 Undefined -- 1 DTS Undefined -- 0 Sz Undefined -- Initial value : R/W : MRA is an 8-bit register that controls the DTC operating mode. Bits 7 and 6--Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is to be incremented, decremented, or left fixed after a data transfer. Bit 7 SM1 0 1 Bit 6 SM0 -- 0 1 Description SAR is fixed SAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) SAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) Bits 5 and 4--Destination Address Mode 1 and 0 (DM1, DM0): These bits specify whether DAR is to be incremented, decremented, or left fixed after a data transfer. Bit 5 DM1 0 1 Bit 4 DM0 -- 0 1 Description DAR is fixed DAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) DAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) 182 Bits 3 and 2--DTC Mode (MD1, MD0): These bits specify the DTC transfer mode. Bit 3 MD1 0 Bit 2 MD0 0 1 1 0 1 Description Normal mode Repeat mode Block transfer mode -- Bit 1--DTC Transfer Mode Select (DTS): Specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode. Bit 1 DTS 0 1 Description Destination side is repeat area or block area Source side is repeat area or block area Bit 0--DTC Data Transfer Size (Sz): Specifies the size of data to be transferred. Bit 0 Sz 0 1 Description Byte-size transfer Word-size transfer 183 8.2.2 Bit DTC Mode Register B (MRB) : 7 CHNE Undefined -- 6 DISEL Undefined -- 5 -- Undefined -- 4 -- Undefined -- 3 -- Undefined -- 2 -- Undefined -- 1 -- Undefined -- 0 -- Undefined -- Initial value: R/W : MRB is an 8-bit register that controls the DTC operating mode. Bit 7--DTC Chain Transfer Enable (CHNE): Specifies chain transfer. With chain transfer, a number of data transfers can be performed consecutively in response to a single transfer request. In data transfer with CHNE set to 1, determination of the end of the specified number of transfers, clearing of the interrupt source flag, and clearing of DTCER is not performed. Bit 7 CHNE 0 1 Description End of DTC data transfer (activation waiting state is entered) DTC chain transfer (new register information is read, then data is transferred) Bit 6--DTC Interrupt Select (DISEL): Specifies whether interrupt requests to the CPU are disabled or enabled after a data transfer. Bit 6 DISEL 0 1 Description After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is 0 (the DTC clears the interrupt source flag of the activating interrupt to 0) After a data transfer ends, the CPU interrupt is enabled (the DTC does not clear the interrupt source flag of the activating interrupt to 0) Bits 5 to 0--Reserved: These bits have no effect on DTC operation in the H8S/2626 Series and H8S/2623 Series, and should always be written with 0. 184 8.2.3 Bit DTC Source Address Register (SAR) : 23 22 21 20 19 4 3 2 1 0 Initial value: R/W : Unde- Unde- Unde- Unde- Undefined fined fined fined fined ---------- Unde- Unde- Unde- Unde- Undefined fined fined fined fined ---------- SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address. 8.2.4 Bit DTC Destination Address Register (DAR) : 23 22 21 20 19 4 3 2 1 0 Initial value : R/W : Unde- Unde- Unde- Unde- Undefined fined fined fined fined ---------- Unde- Unde- Unde- Unde- Undefined fined fined fined fined ---------- DAR is a 24-bit register that designates the destination address of data to be transferred by the DTC. For word-size transfer, specify an even destination address. 8.2.5 Bit DTC Transfer Count Register A (CRA) : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W : Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined -------------------------------- CRAH CRAL CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65,536). It is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits (CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the contents of CRAH are sent when the count reaches H'00. This operation is repeated. 185 8.2.6 Bit DTC Transfer Count Register B (CRB) : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W : Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined -------------------------------- CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. 8.2.7 Bit DTC Enable Registers (DTCER) : 7 DTCE7 0 R/W 6 DTCE6 0 R/W 5 DTCE5 0 R/W 4 DTCE4 0 R/W 3 DTCE3 0 R/W 2 DTCE2 0 R/W 1 DTCE1 0 R/W 0 DTCE0 0 R/W Initial value: R/W : The DTC enable registers comprise seven 8-bit readable/writable registers, DTCERA to DTCERG, with bits corresponding to the interrupt sources that can control enabling and disabling of DTC activation. These bits enable or disable DTC service for the corresponding interrupt sources. The DTC enable registers are initialized to H'00 by a reset and in hardware standby mode. Bit n--DTC Activation Enable (DTCEn) Bit n DTCEn 0 Description DTC activation by this interrupt is disabled [Clearing conditions] * * 1 When the DISEL bit is 1 and the data transfer has ended When the specified number of transfers have ended (Initial value) DTC activation by this interrupt is enabled [Holding condition] When the DISEL bit is 0 and the specified number of transfers have not ended (n = 7 to 0) A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence between interrupt sources and DTCE bits is shown in table 8-4, together with the vector number generated for each interrupt controller. 186 For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR for reading and writing. If all interrupts are masked, multiple activation sources can be set at one time by writing data after executing a dummy read on the relevant register. 8.2.8 Bit DTC Vector Register (DTVECR) : 7 0 R/(W)*1 6 0 5 0 4 0 3 0 2 0 1 0 0 0 SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 Initial value: R/W : R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 Notes: *1 Only 1 can be written to the SWDTE bit. *2 Bits DTVEC6 to DTVEC0 can be written to when SWDTE = 0. DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by software, and sets a vector number for the software activation interrupt. DTVECR is initialized to H'00 by a reset and in hardware standby mode. Bit 7--DTC Software Activation Enable (SWDTE): Enables or disables DTC activation by software. Bit 7 SWDTE 0 Description DTC software activation is disabled [Clearing conditions] * * When the DISEL bit is 0 and the specified number of transfers have not ended When 0 s written to the DISEL bit after a software-activated data transfer end interrupt (SWDTEND) request has been sent to the CPU (Initial value) 1 DTC software activation is enabled [Holding conditions] * * * When the DISEL bit is 1 and data transfer has ended When the specified number of transfers have ended During data transfer due to software activation Bits 6 to 0--DTC Software Activation Vectors 6 to 0 (DTVEC6 to DTVEC0): These bits specify a vector number for DTC software activation. The vector address is expressed as H'0400 + ((vector number) << 1). <<1 indicates a one-bit leftshift. For example, when DTVEC6 to DTVEC0 = H'10, the vector address is H'0420. 187 8.2.9 Bit Module Stop Control Register A (MSTPCRA) 7 MSTPA7 0 R/W 6 MSTPA6 0 R/W 5 MSTPA5 1 R/W 4 MSTPA4 1 R/W 3 MSTPA3 1 R/W 2 MSTPA2 1 R/W 1 MSTPA1 1 R/W 0 MSTPA0 1 R/W Initial value R/W MSTPCRA is an 8-bit readable/writable register that performs module stop mode control. When the MSTPA6 bit in MSTPCRA is set to 1, the DTC operation stops at the end of the bus cycle and a transition is made to module stop mode. However, 1 cannot be written in the MSTPA6 bit while the DTC is operating. For details, see sections 21A.5, 21B.5, Module Stop Mode. MSTPCRA is initialized to H'3F by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 6--Module Stop (MSTPA6): Specifies the DTC module stop mode. Bit 6 MSTPA6 0 1 Description DTC module stop mode cleared DTC module stop mode set (Initial value) 188 8.3 8.3.1 Operation Overview When activated, the DTC reads register information that is already stored in memory and transfers data on the basis of that register information. After the data transfer, it writes updated register information back to memory. Pre-storage of register information in memory makes it possible to transfer data over any required number of channels. Setting the CHNE bit to 1 makes it possible to perform a number of transfers with a single activation. Figure 8-2 shows a flowchart of DTC operation. Start Read DTC vector Next transfer Read register information Data transfer Write register information CHNE=1 No Yes Transfer Counter= 0 or DISEL= 1 No Clear an activation flag Yes Clear DTCER End Interrupt exception handling Figure 8-2 Flowchart of DTC Operation 189 The DTC transfer mode can be normal mode, repeat mode, or block transfer mode. The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the transfer destination address. After each transfer, SAR and DAR are independently incremented, decremented, or left fixed. Table 8-2 outlines the functions of the DTC. Table 8-2 DTC Functions Address Registers Transfer Mode * Normal mode One transfer request transfers one byte or one word Memory addresses are incremented or decremented by 1 or 2 Up to 65,536 transfers possible Repeat mode One transfer request transfers one byte or one word Memory addresses are incremented or decremented by 1 or 2 After the specified number of transfers (1 to 256), the initial state resumes and operation continues Block transfer mode One transfer request transfers a block of the specified size Block size is from 1 to 256 bytes or words Up to 65,536 transfers possible A block area can be designated at either the source or destination Activation Source * * * * * * IRQ TPU TGI SCI TXI or RXI A/D converter ADI Software HCAN RM0 Transfer Source 24 bits Transfer Destination 24 bits * * 190 8.3.2 Activation Sources The DTC operates when activated by an interrupt or by a write to DTVECR by software. An interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER bit. An interrupt becomes a DTC activation source when the corresponding bit is set to 1, and a CPU interrupt source when the bit is cleared to 0. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the activation source or corresponding DTCER bit is cleared. Table 8-3 shows activation source and DTCER clearance. The activation source flag, in the case of RXI0, for example, is the RDRF flag of SCI0. Table 8-3 Activation Source and DTCER Clearance When the DISEL Bit Is 1, or when the Specified Number of Transfers Have Ended The SWDTE bit remains set to 1 An interrupt is issued to the CPU Interrupt activation The corresponding DTCER bit remains set to 1 The activation source flag is cleared to 0 The corresponding DTCER bit is cleared to 0 The activation source flag remains set to 1 A request is issued to the CPU for the activation source interrupt When the DISEL Bit Is 0 and the Specified Number of Activation Source Transfers Have Not Ended Software activation The SWDTE bit is cleared to 0 Figure 8-3 shows a block diagram of activation source control. For details see section 5, Interrupt Controller. Source flag cleared Clear controller Clear DTCER Clear request Select On-chip supporting module IRQ interrupt Interrupt request Selection circuit DTC DTVECR Interrupt controller Interrupt mask CPU Figure 8-3 Block Diagram of DTC Activation Source Control 191 When an interrupt has been designated a DTC activation source, existing CPU mask level and interrupt controller priorities have no effect. If there is more than one activation source at the same time, the DTC operates in accordance with the default priorities. 8.3.3 DTC Vector Table Figure 8-4 shows the correspondence between DTC vector addresses and register information. Table 8-4 shows the correspondence between activation and vector addresses. When the DTC is activated by software, the vector address is obtained from: H'0400 + (DTVECR[6:0] << 1) (where << 1 indicates a 1-bit left shift). For example, if DTVECR is H'10, the vector address is H'0420. The DTC reads the start address of the register information from the vector address set for each activation source, and then reads the register information from that start address. The register information can be placed at predetermined addresses in the on-chip RAM. The start address of the register information should be an integral multiple of four. The configuration of the vector address is the same in both normal* and advanced modes, a 2-byte unit being used in both cases. These two bytes specify the lower bits of the address in the on-chip RAM. Note: * Not available in the H8S/2626 Series or H8S/2623 Series. DTC vector address Register information start address Register information Chain transfer Figure 8-4 Correspondence between DTC Vector Address and Register Information 192 Table 8-4 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs Origin of Interrupt Source Software Vector Number DTVECR Vector Address H'0400+ (DTVECR [6:0] <<1) H'0420 H'0422 H'0424 H'0426 H'0428 H'042A H'042C H'042E H'0438 H'0440 H'0442 H'0444 H'0446 H'0450 H'0452 H'0458 H'045A Interrupt Source Write to DTVECR DTCE* -- Priority High IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 Reserved External pin 16 17 18 19 20 21 22 23 DTCEA7 DTCEA6 DTCEA5 DTCEA4 DTCEA3 DTCEA2 DTCEA1 DTCEA0 DTCEB6 DTCEB5 DTCEB4 DTCEB3 DTCEB2 DTCEB1 DTCEB0 DTCEC7 DTCEC6 Low ADI (A/D conversion end) TGI0A (GR0A compare match/ input capture) TGI0B (GR0B compare match/ input capture) TGI0C (GR0C compare match/ input capture) TGI0D (GR0D compare match/ input capture) TGI1A (GR1A compare match/ input capture) TGI1B (GR1B compare match/ input capture) TGI2A (GR2A compare match/ input capture) TGI2B (GR2B compare match/ input capture) A/D TPU channel 0 28 32 33 34 35 TPU channel 1 40 41 TPU channel 2 44 45 193 Interrupt Source TGI3A (GR3A compare match/ input capture) TGI3B (GR3B compare match/ input capture) TGI3C (GR3C compare match/ input capture) TGI3D (GR3D compare match/ input capture) TGI4A (GR4A compare match/ input capture) TGI4B (GR4B compare match/ input capture) TGI5A (GR5A compare match/ input capture) TGI5B (GR5B compare match/ input capture) Reserved Origin of Interrupt Source TPU channel 3 Vector Number 48 49 50 51 Vector Address H'0460 H'0462 H'0464 H'0466 H'0470 H'0472 H'0478 H'047A H'0480 H'0482 H'0488 H'048A H'0490 H'0492 H'0494 H'0496 H'04A2 H'04A4 H'04AA H'04AC H'04B2 H'04B4 H'04D4 DTCE* DTCEC5 DTCEC4 DTCEC3 DTCEC2 DTCEC1 DTCEC0 DTCED5 DTCED4 DTCED3 DTCED2 DTCED1 DTCED0 DTCEE7 DTCEE6 DTCEE5 DTCEE4 DTCEE3 DTCEE2 DTCEE1 DTCEE0 DTCEF7 DTCEF6 DTCEG5 Priority High TPU channel 4 56 57 TPU channel 5 60 61 -- 64 65 68 69 72 73 74 75 RXI0 (reception complete 0) TXI0 (transmit data empty 0) RXI1 (reception complete 1) TXI1 (transmit data empty 1) RXI2 (reception complete 2) TXI2 (transmit data empty 2) RM0 SCI channel 0 SCI channel 1 SCI channel 2 HCAN 81 82 85 86 89 90 106 Low Note: * DTCE bits with no corresponding interrupt are reserved, and should be written with 0. 194 8.3.4 Location of Register Information in Address Space Figure 8-5 shows how the register information should be located in the address space. Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register information (contents of the vector address). In the case of chain transfer, register information should be located in consecutive areas. Locate the register information in the on-chip RAM (addresses: H'FFEBC0 to H'FFEFBF). Lower address Register information start address 0 MRA MRB CRA MRA MRB CRA 4 bytes SAR DAR CRB Register information for 2nd transfer in chain transfer 1 2 SAR DAR CRB Register information 3 Chain transfer Figure 8-5 Location of Register Information in Address Space 195 8.3.5 Normal Mode In normal mode, one operation transfers one byte or one word of data. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a CPU interrupt can be requested. Table 8-5 lists the register information in normal mode and figure 8-6 shows memory mapping in normal mode. Table 8-5 Name DTC source address register DTC destination address register DTC transfer count register A DTC transfer count register B Register Information in Normal Mode Abbreviation SAR DAR CRA CRB Function Designates source address Designates destination address Designates transfer count Not used SAR Transfer DAR Figure 8-6 Memory Mapping in Normal Mode 196 8.3.6 Repeat Mode In repeat mode, one operation transfers one byte or one word of data. From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated. In repeat mode the transfer counter value does not reach H'00, and therefore CPU interrupts cannot be requested when DISEL = 0. Table 8-6 lists the register information in repeat mode and figure 8-7 shows memory mapping in repeat mode. Table 8-6 Name DTC source address register DTC destination address register DTC transfer count register AH DTC transfer count register AL DTC transfer count register B Register Information in Repeat Mode Abbreviation SAR DAR CRAH CRAL CRB Function Designates source address Designates destination address Holds number of transfers Designates transfer count Not used SAR or DAR Repeat area Transfer DAR or SAR Figure 8-7 Memory Mapping in Repeat Mode 197 8.3.7 Block Transfer Mode In block transfer mode, one operation transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size counter and the address register specified as the block area is restored. The other address register is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a CPU interrupt is requested. Table 8-7 lists the register information in block transfer mode and figure 8-8 shows memory mapping in block transfer mode. Table 8-7 Name DTC source address register DTC destination address register DTC transfer count register AH DTC transfer count register AL DTC transfer count register B Register Information in Block Transfer Mode Abbreviation SAR DAR CRAH CRAL CRB Function Designates source address Designates destination address Holds block size Designates block size count Transfer count 198 First block SAR or DAR * * * Block area Transfer DAR or SAR Nth block Figure 8-8 Memory Mapping in Block Transfer Mode 199 8.3.8 Chain Transfer Setting the CHNE bit to 1 enables a number of data transfers to be performed consectutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 8-9 shows the memory map for chain transfer. Source Destination Register information CHNE = 1 DTC vector address Register information start address Register information CHNE = 0 Source Destination Figure 8-9 Chain Transfer Memory Map In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt source flag for the activation source is not affected. 200 8.3.9 Operation Timing Figures 8-10 to 8-12 show an example of DTC operation timing. o DTC activation request DTC request Data transfer Vector read Address Transfer information read Read Write Transfer information write Figure 8-10 DTC Operation Timing (Example in Normal Mode or Repeat Mode) o DTC activation request DTC request Vector read Address Transfer information read Data transfer Read Write Read Write Transfer information write Figure 8-11 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2) 201 o DTC activation request DTC request Data transfer Vector read Address Transfer information read Read Write Read Write Data transfer Transfer Transfer information information write read Transfer information write Figure 8-12 DTC Operation Timing (Example of Chain Transfer) 8.3.10 Number of DTC Execution States Table 8-8 lists execution statuses for a single DTC data transfer, and table 8-9 shows the number of states required for each execution status. Table 8-8 DTC Execution Statuses Vector Read I 1 1 1 Register Information Read/Write Data Read J K 6 6 6 1 1 N Data Write L 1 1 N Internal Operations M 3 3 3 Mode Normal Repeat Block transfer N: Block size (initial setting of CRAH and CRAL) 202 Table 8-9 Number of States Required for Each Execution Status OnChip RAM 32 1 SI SJ -- 1 OnChip ROM 16 1 1 -- On-Chip I/O Registers 8 2 -- -- 16 2 -- -- Object to be Accessed Bus width Access states Execution status Vector read Register information read/write Byte data read Word data read Byte data write Word data write External Devices 8 2 4 -- 3 16 2 3 3+m -- 6+2m 2 -- -- SK SK SL SL 1 1 1 1 1 1 1 1 1 2 4 2 4 2 2 2 2 2 4 2 4 3+m 2 3+m 3+m 3+m 3+m 6+2m 2 3+m 2 6+2m 2 Internal operation SM The number of execution states is calculated from the formula below. Note that means the sum of all transfers activated by one activation event (the number in which the CHNE bit is set to 1, plus 1). Number of execution states = I * (SI + 1) + (J * SJ + K * SK + L * SL ) + M * SM For example, when the DTC vector address table is located in on-chip ROM, normal mode is set, and data is transferred from the on-chip ROM to an internal I/O register, the time required for the DTC operation is 14 states. The time from activation to the end of the data write is 11 states. 203 8.3.11 Procedures for Using DTC Activation by Interrupt: The procedure for using the DTC with interrupt activation is as follows: [1] Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. [2] Set the start address of the register information in the DTC vector address. [3] Set the corresponding bit in DTCER to 1. [4] Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC is activated when an interrupt used as an activation source is generated. [5] After the end of one data transfer, or after the specified number of data transfers have ended, the DTCE bit is cleared to 0 and a CPU interrupt is requested. If the DTC is to continue transferring data, set the DTCE bit to 1. Activation by Software: The procedure for using the DTC with software activation is as follows: [1] Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. [2] Set the start address of the register information in the DTC vector address. [3] Check that the SWDTE bit is 0. [4] Write 1 to SWDTE bit and the vector number to DTVECR. [5] Check the vector number written to DTVECR. [6] After the end of one data transfer, if the DISEL bit is 0 and a CPU interrupt is not requested, the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the SWDTE bit to 1. When the DISEL bit is 1, or after the specified number of data transfers have ended, the SWDTE bit is held at 1 and a CPU interrupt is requested. 204 8.3.12 Examples of Use of the DTC (1) Normal Mode An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. [1] Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the SCI RDR address in SAR, the start address of the RAM area where the data will be received in DAR, and 128 (H'0080) in CRA. CRB can be set to any value. [2] Set the start address of the register information at the DTC vector address. [3] Set the corresponding bit in DTCER to 1. [4] Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception complete (RXI) interrupt. Since the generation of a receive error during the SCI reception operation will disable subsequent reception, the CPU should be enabled to accept receive error interrupts. [5] Each time reception of one byte of data ends on the SCI, the RDRF flag in SSR is set to 1, an RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag is automatically cleared to 0. [6] When CRA becomes 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The interrupt handling routine should perform wrap-up processing. 205 (2) Chain Transfer An example of DTC chain transfer is shown in which pulse output is performed using the PPG. Chain transfer can be used to perform pulse output data transfer and PPG output trigger cycle updating. Repeat mode transfer to the PPG's NDR is performed in the first half of the chain transfer, and normal mode transfer to the TPU's TGR in the second half. This is because clearing of the activation source and interrupt generation at the end of the specified number of transfers are restricted to the second half of the chain transfer (transfer when CHNE = 0). [1] Perform settings for transfer to the PPG's NDR. Set MRA to source address incrementing (SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), repeat mode (MD1 = 0, MD0 = 1), and word size (Sz = 1). Set the source side as a repeat area (DTS = 1). Set MRB to chain mode (CHNE = 1, DISEL = 0). Set the data table start address in SAR, the NDRH address in DAR, and the data table size in CRAH and CRAL. CRB can be set to any value. [2] Perform settings for transfer to the TPU's TGR. Set MRA to source address incrementing (SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), normal mode (MD1 = MD0 = 0), and word size (Sz = 1). Set the data table start address in SAR, the TGRA address in DAR, and the data table size in CRA. CRB can be set to any value. [3] Locate the TPU transfer register information consecutively after the NDR transfer register information. [4] Set the start address of the NDR transfer register information to the DTC vector address. [5] Set the bit corresponding to TGIA in DTCER to 1. [6] Set TGRA as an output compare register (output disabled) with TIOR, and enable the TGIA interrupt with TIER. [7] Set the initial output value in PODR, and the next output value in NDR. Set bits in DDR and NDER for which output is to be performed to 1. Using PCR, select the TPU compare match to be used as the output trigger. [8] Set the CST bit in TSTR to 1, and start the TCNT count operation. [9] Each time a TGRA compare match occurs, the next output value is transferred to NDR and the set value of the next output trigger period is transferred to TGRA. The activation source TGFA flag is cleared. [10] When the specified number of transfers are completed (the TPU transfer CRA value is 0), the TGFA flag is held at 1, the DTCE bit is cleared to 0, and a TGIA interrupt request is sent to the CPU. Termination processing should be performed in the interrupt handling routine. 206 (3) Software Activation An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation. The transfer source address is H'1000 and the destination address is H'2000. The vector number is H'60, so the vector address is H'04C0. [1] Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE = 0). Set the transfer source address (H'1000) in SAR, the destination address (H'2000) in DAR, and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB. [2] Set the start address of the register information at the DTC vector address (H'04C0). [3] Check that the SWDTE bit in DTVECR is 0. Check that there is currently no transfer activated by software. [4] Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is H'E0. [5] Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this indicates that the write failed. This is presumably because an interrupt occurred between steps 3 and 4 and led to a different software activation. To activate this transfer, go back to step 3. [6] If the write was successful, the DTC is activated and a block of 128 bytes of data is transferred. [7] After the transfer, an SWDTEND interrupt occurs. The interrupt handling routine should clear the SWDTE bit to 0 and perform other wrap-up processing. 207 8.4 Interrupts An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and interrupt controller priority level control. In the case of activation by software, a software activated data transfer end interrupt (SWDTEND) is generated. When the DISEL bit is 1 and one data transfer has ended, or the specified number of transfers have ended, after data transfer ends, the SWDTE bit is held at 1 and an SWDTEND interrupt is generated. The interrupt handling routine should clear the SWDTE bit to 0. When the DTC is activated by software, an SWDTEND interrupt is not generated during a data transfer wait or during data transfer even if the SWDTE bit is set to 1. 8.5 Usage Notes Module Stop: When the MSTPA6 bit in MSTPCRA is set to 1, the DTC clock stops, and the DTC enters the module stop state. However, 1 cannot be written in the MSTPA6 bit while the DTC is operating. On-Chip RAM: The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip RAM. When the DTC is used, the RAME bit in SYSCR must not be cleared to 0. DTCE Bit Setting: For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts are masked, multiple activation sources can be set at one time by writing data after executing a dummy read on the relevant register. 208 Section 9 I/O Ports 9.1 Overview The H8S/2626 Series and H8S/2623 Series have seven I/O ports (ports 1 and A to F), and two input-only ports (ports 4 and 9). Table 9-1 summarizes the port functions. The pins of each port also have other functions. Each I/O port includes a data direction register (DDR) that controls input/output, a data register (DR) that stores output data, and a port register (PORT) used to read the pin states. The input-only ports do not have a DR or DDR register. Ports A to E have a built-in pull-up MOS function, and in addition to DR and DDR, have a MOS input pull-up control register (PCR) to control the on/off state of MOS input pull-up. Ports A to C include an open-drain control register (ODR) that controls the on/off state of the output buffer PMOS. Ports 10 to 13, A0 to A3, and B to E can drive a single TTL load and 50 pF capacitive load when used as expansion bus control signal output pins. In other cases these ports, together with ports 14 to 17 and 3, can drive a single TTL load and 30 pF capacitive load. All the I/O ports can drive a Darlington transistor when in output mode. Ports 1, A, B, and C can drive an LED (10 mA sink current). See Appendix C, I/O Port Block Diagrams, for a block diagram of each port. 209 Table 9-1 Port Functions Pins Mode 4 Mode 5 Mode 6 Mode 7 8-bit I/O port also functioning as TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, TIOCB2), PPG output pins (PO15 to PO8), and interrupt input pins (IRQ0, IRQ1) Port Description Port 1 * 8-bit I/O port * Schmitttriggered input (P16 and P14) P17/PO15/TIOCB2/TCLKD 8-bit I/O port also functioning as TPU I/O P16/PO14/TIOCA2/IRQ1 pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, P15/PO13/TIOCB1/TCLKC TIOCA1, TIOCB1, TIOCA2, TIOCB2), PPG P14/PO12/TIOCA1/IRQ0 output pins (PO15 to PO8), interrupt input pins (IRQ0, IRQ1), and address outputs P13/PO11/TIOCD0/ (A20 to A23) TCLKB/A23 P12/PO10/TIOCC0/ TCLKA/A22 P11/PO9/TIOCB0/A21 P10/PO8/TIOCA0/A20 Port 4 * 8-bit input port P47/AN7 P46/AN6 P45/AN5 P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0 8-bit input port also functioning as A/D converter analog inputs (AN7 to AN0) Port 9 * 8-bit input port P97/AN15/DA3*1 P96/AN14/DA2*1 P95/AN13 P94/AN12 P93/AN11 P92/AN10 P91/AN9 P90/AN8 8-bit input port also functioning as A/D converter analog inputs (AN15 to AN8) and D/A converter analog outputs (DA3, DA2) 210 Port Description Port A * 6-bit I/O *2 port * Built-in MOS input pull-up PA5 PA4 Pins Mode 4 Mode 5 Mode 6 Mode 7 6-bit I/O port also functioning as SCI (channel 2) I/O pins (TxD2, RxD2, SCK2) PA3/A19/SCK2 PA2/A18/RxD2 6-bit I/O port also functioning as SCI (channel 2) I/O pins (TxD2, RxD2, SCK2), and address outputs (A19 to A16) * Open-drain PA1/A17/TxD2 PA0/A16 output capability Port B * 8-bit I/O port * Built-in MOS input pull-up * Open-drain output capability PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3/A11/TIOCD3 PB2/A10/TIOCC3 PB1/A9/TIOCB3 PB0/A8/TIOCA3 8-bit I/O port also functioning as TPU I/O pins (TIOCB5, TIOCA5, TIOCB4, TIOCA4, TIOCD3, TIOCC3, TIOCB3, TIOCA3) and address outputs (A15 to A8) 8-bit I/O port also functioning as TPU I/O pins (TIOCB5, TIOCA5, TIOCB4, TIOCA4, TIOCD3, TIOCC3, TIOCB3, TIOCA3) 8-bit I/O port also functioning as SCI (channel 0, 1) I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1, SCK1) and interrupt input pins (IRQ4, IRQ5) Port C * 8-bit I/O port * Built-in MOS input pull-up * Open-drain output capability PC7/A7 PC6/A6 PC5/A5/SCK1/IRQ5 PC4/A4/RxD1 PC3/A3/TxD1 PC2/A2/SCK0/IRQ4 PC1/A1/RxD0 PC0/A0/TxD0 Address output (A7 to A0) 8-bit I/O port also functioning as SCI (channel 0, 1) I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1, SCK1), interrupt input pins (IRQ4, IRQ5), and address outputs (A7 to A0) Port D * 8-bit I/O port * Built-in MOS input pull-up PD7/D15 PD6/D14 PD5/D13 PD4/D12 PD3/D11 PD2/D10 PD1/D9 PD0/D8 Data bus input/output I/O port 211 Port Description Port E * 8-bit I/O port * Built-in MOS input pull-up PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 Port F * 8-bit I/O port PF7/o Pins Mode 4 Mode 5 Mode 6 Mode 7 I/O port In 8-bit bus mode: I/O port In 16-bit bus mode: data bus input/output When DDR = 0: input port When DDR = 1 (after reset): o output When DDR = 0 (after reset): input port When DDR = 1: o output PF6/AS PF5/RD PF4/HWR PF3/LWR/ADTRG/IRQ3 PF2/WAIT/BREQO AS, RD, HWR, LWR output ADTRG, IRQ3 input I/O port ADTRG, IRQ3 input When WAITE = 0 and BREQOE = 0 (after reset): I/O port When WAITE = 1 and BREQOE = 0: WAIT input When WAITE = 0 and BREQOE = 1: BREQO input I/O port PF1/BACK/BUZZ*3 PF0/BREQ/IRQ2 I/O port, When BRLE = 1: BREQ input, BACK output, BUZZ output, BUZZ output, IRQ2 input IRQ2 input When BRLE = 0 (after reset): I/O port Notes: *1 DA3 and DA2 are outputs in the H8S/2626 Series only. *2 In the H8S/2626 Series, PA5 and PA4 are OSC2 and OSC1, respectively. *3 BUZZ output pin in the H8S/2626 Series only. 212 9.2 9.2.1 Port 1 Overview Port 1 is an 8-bit I/O port. Port 1 pins also function as PPG output pins (PO15 to PO8), TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and TIOCB2), external interrupt pins (IRQ0 and IRQ1), and address bus output pins (A23 to A20). Port 1 pin functions change according to the operating mode. Figure 9-1 shows the port 1 pin configuration. Port 1 pins Pin functions in modes 4 to 6 P17 (I/O) / PO15 (output) / TIOCB2 (I/O) / TCLKD (input) P16 (I/O) / PO14 (output) / TIOCA2 (I/O) / IRQ1 (input) P15 (I/O) / PO13 (output) / TIOCB1 (I/O) / TCLKC (input) P14 (I/O) / PO12 (output) / TIOCA1 (I/O) / IRQ0 (input) Port 1 P13 (I/O) / PO11 (output) / TIOCD0 (I/O) / TCLKB (input) / A23 (output) P12 (I/O) / PO10 (output) / TIOCC0 (I/O) / TCLKA (input) / A22 (output) P11 (I/O) / PO9 (output) / TIOCB0 (I/O) / A21 (output) P10 (I/O) / PO8 (output) / TIOCA0 (I/O) / A20 (output) Pin functions in mode 7 P17 (I/O) / PO15 (output) / TIOCB2 (I/O) / TCLKD (input) P16 (I/O) / PO14 (output) / TIOCA2 (I/O) / IRQ1 (input) P15 (I/O) / PO13 (output) / TIOCB1 (I/O) / TCLKC (input) P14 (I/O) / PO12 (output) / TIOCA1 (I/O) / IRQ0 (input) P13 (I/O) / PO11 (output) / TIOCD0 (I/O) / TCLKB (input) P12 (I/O) / PO10 (output) / TIOCC0 (I/O) / TCLKA (input) P11 (I/O) / PO9 (output) / TIOCB0 (I/O) P10 (I/O) / PO8 (output) / TIOCA0 (I/O) Figure 9-1 Port 1 Pin Functions 213 9.2.2 Register Configuration Table 9-2 shows the port 1 register configuration. Table 9-2 Name Port 1 data direction register Port 1 data register Port 1 register Port 1 Registers Abbreviation P1DDR P1DR PORT1 R/W W R/W R Initial Value H'00 H'00 Undefined Address* H'FE30 H'FF00 H'FFB0 Note: * Lower 16 bits of the address. Port 1 Data Direction Register (P1DDR) Bit : 7 6 5 4 3 2 1 0 P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value : R/W : 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 1. P1DDR cannot be read; if it is, an undefined value will be read. Setting a P1DDR bit to 1 makes the corresponding port 1 pin an output pin, while clearing the bit to 0 makes the pin an input pin. P1DDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. Port 1 Data Register (P1DR) Bit : 7 P17DR Initial value : R/W : 0 R/W 6 P16DR 0 R/W 5 P15DR 0 R/W 4 P14DR 0 R/W 3 P13DR 0 R/W 2 P12DR 0 R/W 1 P11DR 0 R/W 0 P10DR 0 R/W P1DR is an 8-bit readable/writable register that stores output data for the port 1 pins (P17 to P10). P1DR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. 214 Port 1 Register (PORT1) Bit : 7 P17 Initial value : R/W : --* R 6 P16 --* R 5 P15 --* R 4 P14 --* R 3 P13 --* R 2 P12 --* R 1 P11 --* R 0 P10 --* R Note: * Determined by state of pins P17 to P10. PORT1 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port 1 pins (P17 to P10) must always be performed on P1DR. If a port 1 read is performed while P1DDR bits are set to 1, the P1DR values are read. If a port 1 read is performed while P1DDR bits are cleared to 0, the pin states are read. After a reset and in hardware standby mode, PORT1 contents are determined by the pin states, as P1DDR and P1DR are initialized. PORT1 retains its prior state in software standby mode. 215 9.2.3 Pin Functions Port 1 pins also function as PPG output pins (PO15 to PO8), TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and TIOCB2), external interrupt input pins (IRQ0 and IRQ1), and address bus output pins (A23 to A20). Port 1 pin functions are shown in table 9-3. Table 9-3 Pin P17/PO15/ TIOCB2/TCLKD Port 1 Pin Functions Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the TPU channel 2 setting (by bits MD3 to MD0 in TMDR2, bits IOB3 to IOB0 in TIOR2, and bits CCLR1 and CCLR0 in TCR2), bits TPSC2 to TPSC0 in TCR0 and TCR5, bit NDER15 in NDERH, and bit P17DDR. TPU Channel 2 Setting P17DDR NDER15 Pin function Table Below (1) -- -- TIOCB2 output 0 -- P17 input TCLKD input * 2 Table Below (2) 1 0 P17 output 1 1 PO15 output TIOCB2 input * 1 Notes: *1 TIOCB2 input when MD3 to MD0 = B'0000 or B'01xx, and IOB3 = 1. *2 TCLKD input when the setting for either TCR0 or TCR5 is: TPSC2 to TPSC0 = B'111. TCLKD input when channels 2 and 4 are set to phase counting mode. TPU Channel 2 Setting MD3 to MD0 IOB3 to IOB0 (2) B'0000 B'0100 B'1xxx -- -- (1) B'0001 to B'0011 B'0101 to B'0111 -- Output compare output (2) B'0010 -- B'xx00 (2) (1) B'0011 Other than B'xx00 (2) B'0000, B'01xx CCLR1, CCLR0 Output function -- -- -- -- Other than B'10 PWM mode 2 output B'10 -- x: Don't care 216 Pin P16/PO14/ TIOCA2/IRQ1 Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the TPU channel 2 setting (by bits MD3 to MD0 in TMDR2, bits IOA3 to IOA0 in TIOR2, and bits CCLR1 and CCLR0 in TCR2), bit NDER14 in NDERH, and bit P16DDR. TPU Channel 2 Setting P16DDR NDER14 Pin function Table Below (1) -- -- TIOCA2 output 0 -- P16 input Table Below (2) 1 0 P16 output 1 1 PO14 output TIOCA2 input * 1 IRQ1 input TPU Channel 2 Setting MD3 to MD0 IOA3 to IOA0 (2) B'0000 B'0100 B'1xxx -- -- (1) (2) B'001x (1) B'0010 (1) B'0011 (2) B'0000, B'01xx B'0001 to B'xx00 B'0011 B'0101 to B'0111 -- Output compare output -- -- -- Other than B'xx00 CCLR1, CCLR0 Output function Other than B'01 PWM mode 2 output B'01 -- PWM mode 1 output * 2 x: Don't care Notes: *1 TIOCA2 input when MD3 to MD0 = B'0000 or B'01xx, and IOA3 = 1. *2 TIOCB2 output is disabled. 217 Pin P15/PO13/ TIOCB1/TCLKC Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the TPU channel 1 setting (by bits MD3 to MD0 in TMDR1, bits IOB3 to IOB0 in TIOR1, and bits CCLR1 and CCLR0 in TCR1), bits TPSC2 to TPSC0 in TCR0, TCR2, TCR4, and TCR5, bit NDER13 in NDERH, and bit P15DDR. TPU Channel 1 Setting P15DDR NDER13 Pin function Table Below (1) -- -- TIOCB1 output 0 -- P15 input Table Below (2) 1 0 P15 output 1 1 PO13 output TIOCB1 input * 1 TCLKC input * 2 Notes: *1 TIOCB1 input when MD3 to MD0 = B'0000 or B'01xx, and IOB3 to IOB0 = B'10xx. *2 TCLKC input when the setting for either TCR0 or TCR2 is: TPSC2 to TPSC0 = B'110; or when the setting for either TCR4 or TCR5 is TPSC2 to TPSC0 = B'101. TCLKC input when channels 2 and 4 are set to phase counting mode. TPU Channel 1 Setting MD3 to MD0 IOB3 to IOB0 (2) B'0000 B'0100 B'1xxx -- (1) B'0001 to B'0011 B'0101 to B'0111 -- (2) B'0010 -- B'xx00 (2) (1) B'0011 Other than B'xx00 (2) B'0000, B'01xx CCLR1, CCLR0 Output function -- -- Other than B'10 PWM mode 2 output B'10 -- Output compare output -- -- -- x: Don't care 218 Pin P14/PO12/ TIOCA1/IRQ0 Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the TPU channel 1 setting (by bits MD3 to MD0 in TMDR1, bits IOA3 to IOA0 in TIOR1, and bits CCLR1 and CCLR0 in TCR1), bit NDER12 in NDERH, and bit P14DDR. TPU Channel 1 Setting P14DDR NDER12 Pin function Table Below (1) -- -- TIOCA1 output 0 -- P14 input Table Below (2) 1 0 P14 output 1 1 PO12 output TIOCA1 input * 1 IRQ0 input TPU Channel 1 Setting MD3 to MD0 IOA3 to IOA0 (2) B'0000 B'0100 B'1xxx -- -- (1) (2) B'001x (1) B'0010 Other than B'xx00 -- PWM mode 1 output* 2 (1) B'0011 (2) B'0000, B'01xx B'0001 to B'xx00 B'0011 B'0101 to B'0111 -- Output compare output -- -- Other than B'xx00 CCLR1, CCLR0 Output function Other than B'01 PWM mode 2 output B'01 -- x: Don't care Notes: *1 TIOCA1 input when MD3 to MD0 = B'0000 or B'01xx, and IOA3 to IOA0 = B'10xx. *2 TIOCB1 output is disabled. 219 Pin P13/PO11/ TIOCD0/TCLKB/ A23 Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOD3 to IOD0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2 to TPSC0 in TCR0 to TCR2, bits AE3 to AE0 in PFCR, bit NDER11 in NDERH, and bit P13DDR. Operating mode AE3 to AE0 TPU Channel 0 Setting P13DDR NDER11 Pin function Table Below (1) -- -- TIOCD0 output 0 -- Modes 4 to 6 B'0000 to B'1110 Table Below (2) 1 0 1 1 PO11 output B'1111 -- -- -- A23 output P13 input P13 output TIOCD0 input * 1 TCLKB input * 2 Operating mode AE3 to AE0 TPU Channel 0 Setting P13DDR NDER11 Pin function Table Below (1) -- -- TIOCD0 output 0 -- Mode 7 -- Table Below (2) 1 0 P13 output TIOCD0 input * 1 TCLKB input * 2 1 1 PO11 output P13 input Notes: *1 TIOCD0 input when MD3 to MD0 = B'0000, and IOD3 to IOD0 = B'10xx. *2 TCLKB input when the setting for TCR0 to TCR2 is: TPSC2 to TPSC0 = B'101. TCLKB input when channels 1 and 5 are set to phase counting mode. 220 Pin P13/PO11/ TIOCD0/TCLKB/ A23 (cont) Selection Method and Pin Functions TPU Channel 0 Setting MD3 to MD0 IOD3 to IOD0 (2) B'0000 B'0000 B'0100 B'1xxx -- (1) B'0001 to B'0011 B'0101 to B'0111 -- (2) B'0010 -- (2) B'xx00 (1) B'0011 (2) Other than B'xx00 CCLR2 to CCLR0 Output function -- -- Other than B'110 PWM mode 2 output B'110 -- Output compare output -- -- -- x: Don't care 221 Pin P12/PO10/ TIOCC0/TCLKA/ A22 Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOC3 to IOC0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2 to TPSC0 in TCR0 to TCR5, bits AE3 to AE0 in PFCR, bit NDER10 in NDERH, and bit P12DDR. Operating mode AE3 to AE0 TPU Channel 0 Setting P12DDR NDER10 Pin function Table Below (1) -- -- TIOCC0 output 0 -- P12 input Modes 4 to 6 B'0000 to B'1110 Table Below (2) 1 0 P12 output TIOCC0 input * 1 TCLKA input * 2 1 1 PO10 output B'1111 -- -- -- A22 output Operating mode AE3 to AE0 TPU Channel 0 Setting P12DDR NDER10 Pin function Table Below (1) -- -- TIOCC0 output 0 -- Mode 7 -- Table Below (2) 1 0 P12 output TIOCC0 input * 1 TCLKA input * 2 1 1 PO10 output P12 input 222 Pin P12/PO10/ TIOCC0/TCLKA/ A22 (cont) Selection Method and Pin Functions TPU Channel 0 Setting MD3 to MD0 IOC3 to IOC0 (2) B'0000 B'0000 B'0100 B'1xxx -- (1) (2) B'001x (1) B'0010 (1) B'0011 Other than B'xx00 (2) B'0001 to B'xx00 B'0011 B'0101 to B'0111 -- -- -- CCLR2 to CCLR0 Output function Other than B'101 PWM mode 2 output B'101 -- Output compare output -- PWM mode 1 output* 3 -- x: Don't care Notes: *1 TIOCC0 input when MD3 to MD0 = B'0000, and IOC3 to IOC0 = B'10xx. *2 TCLKA input when the setting for TCR0 to TCR5 is: TPSC2 to TPSC0 = B'100. TCLKA input when channels 1 and 5 are set to phase counting mode. *3 TIOCD0 output is disabled. When BFA = 1 or BFB = 1 in TMDR0, output is disabled and setting (2) applies. 223 Pin Selection Method and Pin Functions P11/PO9/TIOCB0/ The pin function is switched as shown below according to the combination of A21 the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, and bits IOB3 to IOB0 in TIOR0H, and bits CCLR2 to CCLR0 in TCR0, bits AE3 to AE0 in PFCR, bit NDER9 in NDERH, and bit P11DDR. Operating mode AE3 to AE0 TPU Channel 0 Setting P11DDR NDER9 Pin function Table Below (1) -- -- TIOCB0 output 0 -- P11 input Modes 4 to 6 B'0000 to B'1101 Table Below (2) 1 0 P11 output 1 1 PO9 output B'1110 to B'1111 -- -- -- A21 output TIOCB0 input * Operating mode AE3 to AE0 TPU Channel 0 Setting P11DDR NDER9 Pin function Table Below (1) -- -- TIOCB0 output 0 -- Mode 7 -- Table Below (2) 1 0 P11 output TIOCB0 input * 1 1 PO9 output P11 input Note: * TIOCB0 input when MD3 to MD0 = B'0000, and IOB3 to IOB0 = B'10xx. 224 Pin Selection Method and Pin Functions P11/PO9/TIOCB0/ TPU Channel A21 (cont) 0 Setting MD3 to MD0 IOB3 to IOB0 (2) B'0000 B'0000 B'0100 B'1xxx -- (1) B'0001 to B'0011 B'0101 to B'0111 -- (2) B'0010 -- (2) B'xx00 (1) B'0011 (2) Other than B'xx00 CCLR2 to CCLR0 Output function -- -- Other than B'010 PWM mode 2 output B'010 -- Output compare output -- -- -- x: Don't care 225 Pin Selection Method and Pin Functions P10/PO8/TIOCA0/ The pin function is switched as shown below according to the combination of A20 the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOA3 to IOA0 in TIOR0H, and bits CCLR2 to CCLR0 in TCR0), bits AE3 to AE0 in PFCR, bit NDER8 in NDERH, and bit P10DDR. Operating mode AE3 to AE0 TPU Channel 0 Setting P10DDR NDER8 Pin function Table Below (1) -- -- TIOCA0 output 0 -- P10 input Modes 4 to 6 B'0000 to B'1110 Table Below (2) 1 0 P10 output 1 1 PO8 output B'1101 to B'1111 -- -- -- A20 output TIOCA0 input * 1 Operating mode AE3 to AE0 TPU Channel 0 Setting P10DDR NDER8 Pin function Table Below (1) -- -- TIOCA0 output 0 -- Mode 7 -- Table Below (2) 1 0 P10 output TIOCA0 input * 1 1 1 PO8 output P10 input 226 Pin Selection Method and Pin Functions P10/PO8/TIOCA0/ TPU Channel A20 (cont) 0 Setting MD3 to MD0 IOA3 to IOA0 (2) B'0000 B'0000 B'0100 B'1xxx -- (1) (2) B'001x (1) B'0010 (1) B'0011 Other than B'xx00 (2) B'0001 to B'xx00 B'0011 B'0101 to B'0111 -- -- -- CCLR2 to CCLR0 Output function Other than B'001 PWM mode 2 output B'001 -- Output compare output -- PWM mode 1 output* 2 -- x: Don't care Notes: *1 TIOCA0 input when MD3 to MD0 = B'0000, and IOA3 to IOA0 = B'10xx. *2 TIOCB0 output is disabled. 227 9.3 9.3.1 Port 4 Overview Port 4 is an 8-bit input-only port. Port 4 pins also function as A/D converter analog input pins (AN0 to AN7). Port 4 pin functions are the same in all operating modes. Figure 9-2 shows the port 4 pin configuration. Port 4 pins P47 (input) / AN7 (input) P46 (input) / AN6 (input) P45 (input) / AN5 (input) Port 4 P44 (input) / AN4 (input) P43 (input) / AN3 (input) P42 (input) / AN2 (input) P41 (input) / AN1 (input) P40 (input) / AN0 (input) Figure 9-2 Port 4 Pin Functions 228 9.3.2 Register Configuration Table 9-4 shows the port 4 register configuration. Port 4 is an input-only port, and does not have a data direction register or data register. Table 9-4 Name Port 4 register Port 4 Registers Abbreviation PORT4 R/W R Initial Value Undefined Address* H'FFB3 Note: * Lower 16 bits of the address. Port 4 Register (PORT4): The pin states are always read when a port 4 read is performed. Bit : 7 P47 Initial value : R/W : --* R 6 P46 --* R 5 P45 --* R 4 P44 --* R 3 P43 --* R 2 P42 --* R 1 P41 --* R 0 P40 --* R Note: * Determined by state of pins P47 to P40. 9.3.3 Pin Functions Port 4 pins also function as A/D converter analog input pins (AN0 to AN7). 229 9.4 9.4.1 Port 9 Overview Port 9 is an 8-bit input-only port. Port 9 pins also function as A/D converter analog input pins (AN8 to AN15) and D/A converter analog output pins (DA3, DA2). Port 9 pin functions are the same in all operating modes. Figure 9-3 shows the port 9 pin configuration. Port 9 pins P97 (input) / AN15 (input) / DA3 (output)* P96 (input) / AN14 (input) / DA2 (output)* P95 (input) / AN13 (input) Port 9 P94 (input) / AN12 (input) P93 (input) / AN11 (input) P92 (input) / AN10 (input) P91 (input) / AN9 (input) P90 (input) / AN8 (input) Note: * DA3 and DA2 are outputs in the H8S/2626 Series only. Figure 9-3 Port 9 Pin Functions 230 9.4.2 Register Configuration Table 9-5 shows the port 9 register configuration. Port 9 is an input-only port, and does not have a data direction register or data register. Table 9-5 Name Port 9 register Port 9 Registers Abbreviation PORT9 R/W R Initial Value Undefined Address* H'FFB8 Note: * Lower 16 bits of the address. Port 9 Register (PORT9): The pin states are always read when a port 9 read is performed. Bit : 7 P97 Initial value : R/W : --* R 6 P96 --* R 5 P95 --* R 4 P94 --* R 3 P93 --* R 2 P92 --* R 1 P91 --* R 0 P90 --* R Note: * Determined by state of pins P97 to P90. 9.4.3 Pin Functions Port 9 pins also function as A/D converter analog input pins (AN8 to AN15) and D/A converter analog output pins (DA3, DA2). 231 9.5 9.5.1 Port A Overview Port A is a 6-bit I/O port. Port A pins also function as address bus outputs and SCI2 I/O pins (SCK2, RxD2, and TxD2). The pin functions change according to the operating mode. Port A has a built-in MOS input pull-up function that can be controlled by software. Figure 9-4 shows the port A pin configuration. Port A pins PA5* PA4* Port A PA3/A19/SCK2 PA2/A18/RxD2 PA1/A17/TxD2 PA0/A16 Pin functions in modes 4 to 6 PA5 (I/O) PA4 (I/O) PA3 (I/O) / A19 (output) / SCK2 (I/O) PA2 (I/O) / A18 (output) / RxD2 (input) PA1 (I/O) / A17 (output) / TxD2 (output) PA0 (I/O) / A16 (output) Pin functions in mode 7 PA5 (I/O) PA4 (I/O) PA3 (I/O) / SCK2 (output) PA2 (I/O) / RxD2 (input) PA1 (I/O) / TxD2 (output) PA0 (I/O) Note: * In the H8S/2626 Series, PA5 and PA4 are OSC2 and OSC1, respectively. Figure 9-4 Port A Pin Functions 232 9.5.2 Register Configuration Table 9-6 shows the port A register configuration. Table 9-6 Name Port A data direction register Port A data register Port A register Port A MOS pull-up control register Port A open-drain control register Port A Registers Abbreviation PADDR PADR PORTA PAPCR PAODR R/W W R/W R R/W R/W Initial Value* 2 H'0 H'0 Undefined H'0 H'0 Address* 1 H'FE39 H'FF09 H'FFB9 H'FE40 H'FE47 Notes: *1 Lower 16 bits of the address. *2 Value of bits 3 to 0. Port A Data Direction Register (PADDR) Bit : 7 -- 6 -- 5 4 3 2 PA2DDR 1 PA1DDR 0 PA0DDR PA5DDR* PA4DDR* PA3DDR Initial value : Undefined Undefined R/W : -- -- 0 W 0 W 0 W 0 W 0 W 0 W Note: * In the H8S/2626 Series bits 5 and 4 are reserved, and will return an undefined value if read. PADDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port A. PADDR cannot be read; if it is, an undefined value will be read. Bits 7 and 6 are reserved; they return an undetermined value if read. PADDR is initialized to H'0 (bits 5 to 0) by a reset, and in hardware standby mode. It retains its prior state in software standby mode. The OPE bit in SBYCR is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode. * Modes 4 to 6 The corresponding port A pins become address outputs in accordance with the setting of bits AE3 to AE0 in PFCR, irrespective of the value of bits PA5DDR to PA0DDR. When pins are not used as address outputs, setting a PADDR bit to 1 makes the corresponding port A pin an output port, while clearing the bit to 0 makes the pin an input port. 233 * Mode 7 Setting a PADDR bit to 1 makes the corresponding port A pin an output port, while clearing the bit to 0 makes the pin an input port. Port A Data Register (PADR) Bit : 7 -- 6 -- 5 4 3 PA3DR 0 R/W 2 PA2DR 0 R/W 1 PA1DR 0 R/W 0 PA0DR 0 R/W PA5DR* PA4DR* 0 R/W 0 R/W Initial value : Undefined Undefined R/W : -- -- Note: * In the H8S/2626 Series bits 5 and 4 are reserved, and will return an undefined value if read. PADR is an 8-bit readable/writable register that stores output data for the port A pins (PA5 to PA0). Bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified. PADR is initialized to H'0 (bits 5 to 0) by a reset, and in hardware standby mode. It retains its prior state in software standby mode. Port A Register (PORTA) Bit : 7 -- 6 -- 5 PA5* --* R 1 2 4 PA4* --* R 1 2 3 PA3 --* R 1 2 PA2 --* R 1 1 PA1 --* R 1 0 PA0 --* 1 R Initial value : Undefined Undefined R/W : -- -- Notes: *1 Determined by state of pins PA5 to PA0. *2 In the H8S/2626 Series bits 5 and 4 are reserved, and will return an undefined value if read. PORTA is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port A pins (PA5 to PA0) must always be performed on PADR. Bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified. If a port A read is performed while PADDR bits are set to 1, the PADR values are read. If a port A read is performed while PADDR bits are cleared to 0, the pin states are read. After a reset and in hardware standby mode, PORTA contents are determined by the pin states, as PADDR and PADR are initialized. PORTA retains its prior state in software standby mode. 234 Port A MOS Pull-Up Control Register (PAPCR) Bit : 7 -- 6 -- 5 4 3 2 PA2PCR 1 PA1PCR 0 PA0PCR PA5PCR* PA4PCR* PA3PCR Initial value : Undefined Undefined R/W : -- -- 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Note: * In the H8S/2626 Series bits 5 and 4 are reserved, and will return an undefined value if read. PAPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port A on an individual bit basis. Bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified. In modes 4 to 6, if a pin is in the input state in accordance with the settings in PFCR, in the SCI's SCMR, SMR, and SCR, and in DDR, setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up for that pin. In mode 7, if a pin is in the input state in accordance with the settings in the SCI's SCMR, SMR, and SCR, and in DDR, setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up for that pin. PAPCR is initialized to H'0 (bits 5 to 0) by a reset, and in hardware standby mode. It retains its prior state in software standby mode. Port A Open Drain Control Register (PAODR) Bit : 7 -- 6 -- 5 4 3 2 PA2ODR 1 PA1ODR 0 PA0ODR PA5ODR* PA4ODR* PA3ODR Initial value : Undefined Undefined R/W : -- -- 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Note: * In the H8S/2626 Series bits 5 and 4 are reserved, and will return an undefined value if read. PAODR is an 8-bit readable/writable register that controls whether PMOS is on or off for each port A pin (PA5 to PA0). Bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified. When pins are not address outputs in accordance with the setting of bits AE3 to AE0 in PFCR, setting a PAODR bit makes the corresponding port A pin an NMOS open-drain output, while clearing the bit to 0 makes the pin a CMOS output. PAODR is initialized to H'0 (bits 3 to 0) by a reset, and in hardware standby mode. It retains its prior state in software standby mode. 235 9.5.3 Pin Functions Port A pins also function as SCI input/output pins (TxD2, RxD2, SCK2) and address bus output pins (A19 to A16). Port A pin functions are shown in table 9-7. Table 9-7 Pin PA5* Port A Pin Functions Selection Method and Pin Functions The pin function is switched as shown below according to bit PA5DDR. PA5DDR Pin function 0 PA5 input 1 PA5 output Note: * In the H8S/2626 Series, PA5 is OSC2. PA4* The pin function is switched as shown below according to bit PA4DDR. PA4DDR Pin function 0 PA4 input 1 PA4 output Note: * In the H8S/2626 Series, PA4 is OSC1. PA3/A19/SCK2 The pin function is switched as shown below according to the operating mode, bits AE3 to AE0 in PFCR, bit C/A in SMR and bits CKE0 and CKE1 in SCR of SCI2, and bit PA3DDR. Operating mode AE3 to AE0 CKE1 C/A CKE0 PA3DDR Pin function 0 PA3 input 0 1 PA3 output 0 1 -- SCK2 output Modes 4 to 6 B'0000 to B'1011 0 1 -- -- SCK2 output 1 -- -- -- SCK2 input B'1100 to B'1111 -- -- -- -- A19 output Operating mode CKE1 C/A CKE0 PA3DDR Pin function 0 PA3 input 0 1 PA3 output 0 0 Mode 7 1 1 1 -- SCK2 output -- -- SCK2 output -- -- -- SCK2 input 236 Pin PA2/A18/RxD2 Selection Method and Pin Functions The pin function is switched as shown below according to the operating mode, bits AE3 to AE0 in PFCR, bit RE in SCR of SCI2, and bit PA2DDR. Operating mode AE3 to AE0 RE PA2DDR Pin function 0 PA2 input Modes 4 to 6 B'0000 to B'1011 0 1 PA2 output 1 -- RxD2 input B'1011 to B'1111 -- -- A18 output Operating mode RE PA2DDR Pin function 0 PA2 input 0 Mode 7 1 1 PA2 output -- RxD2 input PA1/A17/TxD2 The pin function is switched as shown below according to the operating mode, bits AE3 to AE0 in PFCR, bit TE in SCR of SCI2, and bit PA1DDR. Operating mode AE3 to AE0 TE PA1DDR Pin function 0 PA1 input Modes 4 to 6 B'0000 to B'1001 0 1 PA1 output 1 -- TxD2 output B'1010 to B'1111 -- -- A17 output Operating mode TE PA1DDR Pin function 0 PA1 input 0 Mode 7 1 1 PA1 output -- TxD2 output 237 Pin PA0/A16 Selection Method and Pin Functions The pin function is switched as shown below according to the operating mode, bits AE3 to AE0 in PFCR, and bit PA0DDR. Operating mode AE3 to AE0 PA0DDR Pin function 0 PA0 input Modes 4 to 6 B'0000 to B'1000 1 PA0 output B'1001 to B'1111 -- A16 output Operating mode PA0DDR Pin function 0 PA0 input Mode 7 1 PA0 output 238 9.5.4 MOS Input Pull-Up Function Port A has a built-in MOS input pull-up function that can be controlled by software. MOS input pull-up can be specified as on or off on an individual bit basis. In modes 4 to 6, if a pin is in the input state in accordance with the settings in PFCR, in the SCI's SCMR, SMR, and SCR, and in DDR, setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up for that pin. In mode 7, if a pin is in the input state in accordance with the settings in the SCI's SCMR, SMR, and SCR, and in DDR, setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a reset, and in hardware standby mode. The prior state is retained in software standby mode. Table 9-8 summarizes the MOS input pull-up states. Table 9-8 Pin States Address output or SCI output Other than above MOS Input Pull-Up States (Port A) Power-On Reset OFF Hardware Standby Mode OFF Software Standby Mode OFF ON/OFF In Other Operations OFF ON/OFF Legend: OFF : MOS input pull-up is always off. ON/OFF : On when PADDR = 0 and PAPCR = 1; otherwise off. 239 9.6 9.6.1 Port B Overview Port B is an 8-bit I/O port. Port B pins also function as TPU I/O pins (TIOCA3, TIOCB3, TIOCC3, TIOCD3, TIOCA4, TIOCB4, TIOCA5, TIOCB5) and as address outputs; the pin functions change according to the operating mode. Port B has a built-in MOS input pull-up function that can be controlled by software. Figure 9-5 shows the port B pin configuration. Port B pins PB7 / A15/TIOCB5 PB6 / A14/TIOCA5 PB5 / A13/TIOCB4 PB4 / A12/TIOCA4 Port B PB3 / A11/TIOCD3 PB2 / A10/TIOCC3 PB1 / A9 /TIODB3 PB0 / A8 /TIOCA3 Pin functions in modes 4 to 6 PB7 (I/O) / A15 (output) / TIOCB5 (I/O) PB6 (I/O) / A14 (output) / TIOCA5 (I/O) PB5 (I/O) / A13 (output) / TIOCB4 (I/O) PB4 (I/O) / A12 (output) / TIOCA4 (I/O) PB3 (I/O) / A11 (output) / TIOCD3 (I/O) PB2 (I/O) / A10 (output) / TIOCC3 (I/O) PB1 (I/O) / A9 (output) / TIOCB3 (I/O) PB0 (I/O) / A8 (output) / TIOCA3 (I/O) Pin functions in mode 7 PB7 (I/O) / TIOCB5 (I/O) PB6 (I/O) / TIOCA5 (I/O) PB5 (I/O) / TIOCB4 (I/O) PB4 (I/O) / TIOCA4 (I/O) PB3 (I/O) / TIOCD3 (I/O) PB2 (I/O) / TIOCC3 (I/O) PB1 (I/O) / TIOCB3 (I/O) PB0 (I/O) / TIOCA3 (I/O) Figure 9-5 Port B Pin Functions 240 9.6.2 Register Configuration Table 9-9 shows the port B register configuration. Table 9-9 Name Port B data direction register Port B data register Port B register Port B MOS pull-up control register Port B open-drain control register Note: * Lower 16 bits of the address. Port B Registers Abbreviation PBDDR PBDR PORTB PBPCR PBODR R/W W R/W R R/W R/W Initial Value H'00 H'00 Undefined H'00 H'00 Address* H'FE3A H'FF0A H'FFBA H'FE41 H'FE48 Port B Data Direction Register (PBDDR) Bit : 7 6 5 4 3 2 1 0 PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Initial value : R/W : 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W PBDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port B. PBDDR cannot be read; if it is, an undefined value will be read. PBDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. The OPE bit in SBYCR is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode. * Modes 4 to 6 The corresponding port B pins become address outputs in accordance with the setting of bits AE3 to AE0 in PFCR, irrespective of the value of the PBDDR bits. When pins are not used as address outputs, setting a PBDDR bit to 1 makes the corresponding port B pin an output port, while clearing the bit to 0 makes the pin an input port. * Mode 7 Setting a PBDDR bit to 1 makes the corresponding port B pin an output port, while clearing the bit to 0 makes the pin an input port. 241 Port B Data Register (PBDR) Bit : 7 PB7DR Initial value : R/W : 0 R/W 6 PB6DR 0 R/W 5 PB5DR 0 R/W 4 PB4DR 0 R/W 3 PB3DR 0 R/W 2 PB2DR 0 R/W 1 PB1DR 0 R/W 0 PB0DR 0 R/W PBDR is an 8-bit readable/writable register that stores output data for the port B pins (PB7 to PB0). PBDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. Port B Register (PORTB) Bit : 7 PB7 Initial value : R/W : --* R 6 PB6 --* R 5 PB5 --* R 4 PB4 --* R 3 PB3 --* R 2 PB2 --* R 1 PB1 --* R 0 PB0 --* R Note: * Determined by state of pins PB7 to PB0. PORTB is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port B pins (PB7 to PB0) must always be performed on PBDR. If a port B read is performed while PBDDR bits are set to 1, the PBDR values are read. If a port B read is performed while PBDDR bits are cleared to 0, the pin states are read. After a reset and in hardware standby mode, PORTB contents are determined by the pin states, as PBDDR and PBDR are initialized. PORTB retains its prior state in software standby mode. 242 Port B MOS Pull-Up Control Register (PBPCR) Bit : 7 6 5 4 3 2 1 0 PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR Initial value : R/W : 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W PBPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port B on an individual bit basis. In modes 4 to 6, if a pin is in the input state in accordance with the settings in PFCR, in the TPU's TIOR, and in DDR, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for that pin. In mode 7, if a pin is in the input state in accordance with the settings in the TPU's TIOR and in DDR, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for that pin. PBPCR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. Port B Open Drain Control Register (PBODR) Bit : 7 6 5 4 3 2 1 0 PB7ODR PB6ODR PB5ODR PB4ODR PB3ODR PB2ODR PB1ODR PB0ODR Initial value : R/W : 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W PBODR is an 8-bit readable/writable register that controls the PMOS on/off state for each port B pin (PB7 to PB0). When pins are not address outputs in accordance with the setting of bits AE3 to AE0 in PFCR, setting a PBODR bit makes the corresponding port B pin an NMOS open-drain output, while clearing the bit to 0 makes the pin a CMOS output. PBODR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. 9.6.3 Pin Functions Port B pins also function as TPU input/output pins (TIOCA3, TIOCB3, TIOCC3, TIOCD3, TIOCA4, TIOCB4, TIOCA5, TIOCB5) and address bus output pins (A15 to A8). Port B pin functions are shown in table 9-10. 243 Table 9-10 Port B Pin Functions Pin PB7/A15/ TIOCB5 Selection Method and Pin Functions The pin function is switched as shown below according to the operating mode, bits AE3 to AE0 in PFCR, the TPU channel 5 settings by bits MD3 to MD0 in TMDR5, bits IOB3 to IOB0 in TIOR5, and bits CCLR1 and CCLR0 in TCR5, and bit PB7DDR. Operating mode AE3 to AE0 TPU channel 5 settings PB7DDR Pin function (1) in table below -- TIOCB5 output 0 PB7 input Modes 4 to 6 B'0000 to B'0111 (2) in table below 1 PB7 output B'1000 to B'1111 -- -- A15 output TIOCB5 input* Operating mode TPU channel 5 settings PB7DDR Pin function (1) in table below -- TIOCB5 output Mode 7 (2) in table below 0 PB7 input 1 PB7 output TIOCB5 input* TPU channel 5 settings MD3 to MD0 IOB3 to IOB0 (2) (1) (2) B'0010 -- (2) (1) B'0011 (2) B'0000, B'01xx B'0000, B'0100, B'1xxx -- -- B'0001 to B'0011, B'0101 to B'0111 -- Output compare output B'xx00 Not B'xx00 CCLR1, CCLR0 Output function -- -- -- -- Not B'10 PWM mode 2 output B'10 -- x: Don't care Note: * TIOCB5 input when MD3 to MD0 = B'0000 or B'01xx, and IOB3 = 1. 244 Pin PB6/A14/ TIOCA5 Selection Method and Pin Functions The pin function is switched as shown below according to the operating mode, bits AE3 to AE0 in PFCR, the TPU channel 5 settings by bits MD3 to MD0 in TMDR5, bits IOA3 to IOA0 in TIOR5, and bits CCLR1 and CCLR0 in TCR5, and bit PB6DDR. Operating mode AE3 to AE0 TPU channel 5 settings PB6DDR Pin function (1) in table below -- TIOCA5 output 0 PB6 input Modes 4 to 6 B'0000 to B'0110 (2) in table below 1 PB6 output 1 B'0111 to B'1111 -- -- A14 output TIOCA5 input* Operating mode TPU channel 5 settings PB6DDR Pin function (1) in table below -- TIOCA5 output Mode 7 (2) in table below 0 PB6 input 1 PB6 output TIOCA5 input* 1 TPU channel 5 settings MD3 to MD0 IOA3 to IOA0 (2) (1) (2) B'001x B'xx00 (1) B'0010 Not B'xx00 (1) B'0011 (2) B'0000, B'01xx B'0000, B'0100, B'1xxx -- -- B'0001 to B'0011, B'0101 to B'0111 -- Output compare output Not B'xx00 CCLR1, CCLR0 Output function -- -- -- PWM mode 1 output* 2 Not B'01 PWM mode 2 output B'01 -- x: Don't care Notes: *1 TIOCA5 input when MD3 to MD0 = B'0000 or B'01xx, and IOA3 = 1. *2 TIOCB5 is disabled for output. 245 Pin PB5/A13/ TIOCB4 Selection Method and Pin Functions The pin function is switched as shown below according to the operating mode, bits AE3 to AE0 in PFCR, the TPU channel 4 settings by bits MD3 to MD0 in TMDR4, bits IOB3 to IOB0 in TIOR4, and bits CCLR1 and CCLR0 in TCR4, and bit PB5DDR. Operating mode AE3 to AE0 TPU channel 4 settings PB5DDR Pin function (1) in table below -- TIOCB4 output 0 PB5 input Modes 4 to 6 B'0000 to B'0101 (2) in table below 1 PB5 output B'0110 to B'1111 -- -- A13 output TIOCB4 input* Operating mode TPU channel 4 settings PB5DDR Pin function (1) in table below -- TIOCB4 output Mode 7 (2) in table below 0 PB5 input 1 PB5 output TIOCB4 input* TPU channel 5 settings MD3 to MD0 IOB3 to IOB0 (2) (1) (2) B'0010 -- (2) (1) B'0011 (2) B'0000, B'01xx B'0000, B'0100, B'1xxx -- 1 B'0001 to B'0011, B'0101 to B'0111 -- Output compare output B'xx00 Not B'xx00 CCLR1, CCLR0 Output function -- 1 -- 1 Not B'10 PWM mode 2 output B'10 1 x: Don't care Note: * TIOCB4 input when MD3 to MD0 = B'0000 or B'01xx, and IOB3 to IOB0 = B'10xx. 246 Pin PB4/A12/ TIOCA4 Selection Method and Pin Functions The pin function is switched as shown below according to the operating mode, bits AE3 to AE0 in PFCR, the TPU channel 5 settings by bits MD3 to MD0 in TMDR4, bits IOA3 to IOA0 in TIOR4, and bits CCLR1 and CCLR0 in TCR4, and bit PB4DDR. Operating mode AE3 to AE0 TPU channel 4 settings PB4DDR Pin function (1) in table below -- TIOCA4 output 0 PB4 input Modes 4 to 6 B'0000 to B'0100 (2) in table below 1 PB4 output 1 B'0101 to B'1111 -- -- A12 output TIOCA4 input* Operating mode TPU channel 4 settings PB4DDR Pin function (1) in table below -- TIOCA4 output Mode 7 (2) in table below 0 PB4 input 1 PB4 output TIOCA4 input* 1 TPU channel 4 settings MD3 to MD0 IOA3 to IOA0 (2) (1) (2) B'001x B'xx00 (1) B'0010 Not B'xx00 (1) B'0011 (2) B'0000, B'01xx B'0000, B'0100, B'1xxx -- -- B'0001 to B'0011, B'0101 to B'0111 -- Output compare output Not B'xx00 CCLR1, CCLR0 Output function -- -- -- PWM mode 1 output* 2 Not B'01 PWM mode 2 output B'01 -- x: Don't care Notes: *1 TIOCA4 input when MD3 to MD0 = B'0000 or B'01xx, and IOA3 to IOA0 = B'10xx. *2 TIOCB4 is disabled for output. 247 Pin PB3/A11/ TIOCD3 Selection Method and Pin Functions The pin function is switched as shown below according to the operating mode, bits AE3 to AE0 in PFCR, the TPU channel 3 settings by bits MD3 to MD0 in TMDR3, bits IOD3 to IOD0 in TIOR3L, and bits CCLR2 to CCLR0 in TCR3, and bit PB3DDR. Operating mode AE3 to AE0 TPU channel 3 settings PB3DDR Pin function (1) in table below -- TIOCD3 output 0 PB3 input Modes 4 to 6 B'0000 to B'0011 (2) in table below 1 PB3 output B'0100 to B'1111 -- -- A11 output TIOCD3 input* Operating mode TPU channel 3 settings PB3DDR Pin function (1) in table below -- TIOCD3 output Mode 7 (2) in table below 0 PB3 input 1 PB3 output TIOCD3 input* TPU channel 3 settings MD3 to MD0 IOD3 to IOD0 (2) B'0000 B'0000, B'0100, B'1xxx -- -- (1) (2) B'0010 -- (2) (1) B'0011 (2) B'0001 to B'0011, B'0101 to B'0111 -- Output compare output B'xx00 Not B'xx00 CCLR2 to CCLR0 Output function -- -- -- -- Not B'110 PWM mode 2 output B'110 -- x: Don't care Note * TIOCD3 input when MD3 to MD0 = B'0000 or B'01xx, and IOD3 to IOD0 = B'10xx. 248 Pin PB2/A10/ TIOCC3 Selection Method and Pin Functions The pin function is switched as shown below according to the operating mode, bits AE3 to AE0 in PFCR, the TPU channel 3 settings by bits MD3 to MD0 in TMDR3, bits IOC3 to IOC0 in TIOR3L, and bits CCLR2 to CCLR0 in TCR3, and bit PB2DDR. Operating mode AE3 to AE0 TPU channel 3 settings PB2DDR Pin function (1) in table below -- TIOCC3 output 0 PB2 input Modes 4 to 6 B'0000 to B'0010 (2) in table below 1 PB2 output 1 B'0011 to B'1111 -- -- A10 output TIOCC3 input* Operating mode TPU channel 3 settings PB2DDR Pin function (1) in table below -- TIOCC3 output Mode 7 (2) in table below 0 PB2 input 1 PB2 output TIOCC3 input* 1 TPU channel 3 settings MD3 to MD0 IOC3 to IOC0 (2) B'0000 B'0000, B'0100, B'1xxx -- -- (1) (2) B'001x B'xx00 (1) B'0010 Not B'xx00 (1) B'0011 (2) B'0001 to B'0011, B'0101 to B'0111 -- Output compare output Not B'xx00 CCLR2 to CCLR0 Output function -- -- -- PWM mode 1 output* 2 Not B'101 PWM mode 2 output B'101 -- x: Don't care Notes: *1 TIOCC3 input when MD3 to MD0 = B'0000, and IOC3 to IOC0 = B'10xx. *2 TIOCD3 is disabled for output. 249 Pin PB1/A9/ TIOCB3 Selection Method and Pin Functions The pin function is switched as shown below according to the operating mode, bits AE3 to AE0 in PFCR, the TPU channel 3 settings by bits MD3 to MD0 in TMDR3, bits IOB3 to IOB0 in TIOR3H, and bits CCLR2 to CCLR0 in TCR3, and bit PB1DDR. Operating mode AE3 to AE0 TPU channel 3 settings PB1DDR Pin function (1) in table below -- TIOCB3 output 0 PB1 input Modes 4 to 6 B'0000 to B'0001 (2) in table below 1 PB1 output B'0010 to B'1111 -- -- A9 output TIOCB3 input* Operating mode TPU channel 3 settings PB1DDR Pin function (1) in table below -- TIOCB3 output Mode 7 (2) in table below 0 PB1 input 1 PB1 output TIOCB3 input* TPU channel 3 settings MD3 to MD0 IOB3 to IOB0 (2) B'0000 B'0000, B'0100, B'1xxx -- -- (1) (2) B'0010 -- (2) (1) B'0011 (2) B'0001 to B'0011, B'0101 to B'0111 -- Output compare output B'xx00 Not B'xx00 CCLR2 to CCLR0 Output function -- -- -- -- Not B'010 PWM mode 2 output B'010 -- x: Don't care Note: * TIOCB3 input when MD3 to MD0 = B'0000, and IOB3 to IOB0 = B'10xx. 250 Pin PB0/A8/ TIOCA3 Selection Method and Pin Functions The pin function is switched as shown below according to the operating mode, bits AE3 to AE0 in PFCR, the TPU channel 3 settings by bits MD3 to MD0 in TMDR3, bits IOA3 to IOA0 in TIOR3H, and bits CCLR2 to CCLR0 in TCR3, and bit PB0DDR. Operating mode AE3 to AE0 TPU channel 3 settings PB0DDR Pin function (1) in table below -- TIOCA3 output 0 PB0 input Modes 4 to 6 B'0000 (2) in table below 1 PB0 output 1 B'0001 to B'1111 -- -- A8 output TIOCA3 input* Operating mode TPU channel 3 settings PB0DDR Pin function (1) in table below -- TIOCA3 output Mode 7 (2) in table below 0 PB0 input 1 PB0 output TIOCA3 input* 1 TPU channel 3 settings MD3 to MD0 IOA3 to IOA0 (2) B'0000 B'0000, B'0100, B'1xxx -- -- (1) (2) B'001x B'xx00 (1) B'0010 Not B'xx00 (1) B'0011 (2) B'0001 to B'0011, B'0101 to B'0111 -- Output compare output Not B'xx00 CCLR2 to CCLR0 Output function -- -- -- PWM mode 1 output* 2 Not B'001 PWM mode 2 output B'001 -- x: Don't care Notes: *1 TIOCA3 input when MD3 to MD0 = B'0000, and IOA3 to IOA0 = B'10xx. *2 TIOCB3 is disabled for output. 251 9.6.4 MOS Input Pull-Up Function Port B has a built-in MOS input pull-up function that can be controlled by software. MOS input pull-up can be specified as on or off on an individual bit basis. In modes 4 to 6, if a pin is in the input state in accordance with the settings in PFCR, in the TPU's TIOR, and in DDR, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for that pin. In mode 7, if a pin is in the input state in accordance with the settings in the TPU's TIOR and in DDR, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a reset, and in hardware standby mode. The prior state is retained in software standby mode. Table 9-11 summarizes the MOS input pull-up states. Table 9-11 MOS Input Pull-Up States (Port B) Pin States Address output or TPU output Other than above Power-On Reset OFF Hardware Standby Mode OFF Software Standby Mode OFF ON/OFF In Other Operations OFF ON/OFF Legend: OFF : MOS input pull-up is always off. ON/OFF : On when PBDDR = 0 and PBPCR = 1; otherwise off. 252 9.7 9.7.1 Port C Overview Port C is an 8-bit I/O port. Port C has an address bus output function, SCI I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1 and SCK1), and external interrupt input pins (IRQ4 and IRQ5), and the pin functions change according to the operating mode. Port C has a built-in MOS input pull-up function that can be controlled by software. Figure 9-6 shows the port C pin configuration. Port C pins PC7/A7 PC6/A6 PC5/A5/SCK1/IRQ5 Port C PC4/A4/RxD1 PC3/A3/TxD1 PC2/A2/SCK0/IRQ4 PC1/A1/RxD0 PC0/A0/TxD0 Pin functions in modes 4 and 5 A7 (output) A6 (output) A5 (output) A4 (output) A3 (output) A2 (output) A1 (output) A0 (output) Pin functions in mode 6 PC7 (input) / A7 (output) PC6 (input) / A6 (output) PC5 (input) / A5 (output) / SCK1 (I/O) / IRQ5 (input) PC4 (input) / A4 (output) / RxD1 (input) PC3 (input) / A3 (output) / TxD1 (output) PC2 (input) / A2 (output) / SCK0 (I/O) / IRQ4 (input) PC1 (input) / A1 (output) / RxD0 (input) PC0 (input) / A0 (output) / TxD0 (output) Pin functions in mode 7 PC7 (I/O) PC6 (I/O) PC5 (I/O) / SCK1 (I/O) / IRQ5 (input) PC4 (I/O) / RxD1 (input) PC3 (I/O) / TxD1 (output) PC2 (I/O) / SCK0 (I/O) / IRQ4 (input) PC1 (I/O) / RxD0 (input) PC0 (I/O) / TxD0 (output) Figure 9-6 Port C Pin Functions 253 9.7.2 Register Configuration Table 9-12 shows the port C register configuration. Table 9-12 Port C Registers Name Port C data direction register Port C data register Port C register Port C MOS pull-up control register Port C open-drain control register Note: * Lower 16 bits of the address. Abbreviation PCDDR PCDR PORTC PCPCR PCODR R/W W R/W R R/W R/W Initial Value H'00 H'00 Undefined H'00 H'00 Address* H'FE3B H'FF0B H'FFBB H'FE42 H'FE49 Port C Data Direction Register (PCDDR) Bit : 7 6 5 4 3 2 1 0 PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR Initial value : R/W : 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W PCDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port C. PCDDR cannot be read; if it is, an undefined value will be read. PCDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. As the SCI is initialized, pin states are determined by the PCDDR and PCDR specifications. The OPE bit in SBYCR is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode. * Modes 4 and 5 The corresponding port C pins are address outputs irrespective of the value of the PCDDR bits. * Mode 6 Setting a PCDDR bit to 1 makes the corresponding port C pin an address output, while clearing the bit to 0 makes the pin an input port. * Mode 7 Setting a PCDDR bit to 1 makes the corresponding port C pin an output port, while clearing the bit to 0 makes the pin an input port. 254 Port C Data Register (PCDR) Bit : 7 PC7DR Initial value : R/W : 0 R/W 6 PC6DR 0 R/W 5 PC5DR 0 R/W 4 PC4DR 0 R/W 3 PC3DR 0 R/W 2 PC2DR 0 R/W 1 PC1DR 0 R/W 0 PC0DR 0 R/W PCDR is an 8-bit readable/writable register that stores output data for the port C pins (PC7 to PC0). PCDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. Port C Register (PORTC) Bit : 7 PC7 Initial value : R/W : --* R 6 PC6 --* R 5 PC5 --* R 4 PC4 --* R 3 PC3 --* R 2 PC2 --* R 1 PC1 --* R 0 PC0 --* R Note: * Determined by state of pins PC7 to PC0. PORTC is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port C pins (PC7 to PC0) must always be performed on PCDR. If a port C read is performed while PCDDR bits are set to 1, the PCDR values are read. If a port C read is performed while PCDDR bits are cleared to 0, the pin states are read. After a reset and in hardware standby mode, PORTC contents are determined by the pin states, as PCDDR and PCDR are initialized. PORTC retains its prior state in software standby mode. 255 Port C MOS Pull-Up Control Register (PCPCR) Bit : 7 6 5 4 3 2 1 0 PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR Initial value : R/W : 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W PCPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port C on an individual bit basis. In modes 6 and 7, if a pin is in the input state in accordance with the settings in the SCI's SMR and SCR, and in PCDDR, setting the corresponding PCPCR bit to 1 turns on the MOS input pullup for that pin. PCPCR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. Port C Open Drain Control Register (PCODR) Bit : 7 6 5 4 3 2 1 0 PC7ODR PC6ODR PC5ODR PC4ODR PC3ODR PC2ODR PC1ODR PC0ODR Initial value : R/W : 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W PCODR is an 8-bit readable/writable register that controls the PMOS on/off status for each port C pin (PC7 to PC0). If the setting of bits AE3 to AE0 in PFCR is other than address output, setting a PCODR bit to 1 makes the corresponding port C pin an NMOS open-drain output, while clearing the bit to 0 makes the pin a CMOS output. PCODR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. 256 9.7.3 Pin Functions Port C pins also function as SCI I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1, and SCK1), interrupt input pins (IRQ4 and IRQ5), and address bus outputs. The pin functions differ between modes 4 and 5, mode 6, and mode 7. Port C pin functions are shown in table 9-13. Table 9-13 Port C Pin Functions Pin PC7/A7 Selection Method and Pin Functions The pin function is switched as shown below according to the operating mode and bit PC7DDR. Operating Mode PC7DDR Pin function Modes 4 and 5 -- A7 output 0 PC7 input Mode 6 1 A7 output 0 PC7 input Mode 7 1 PC7 output PC6/A6 The pin function is switched as shown below according to the operating mode and bit PC6DDR. Operating Mode PC6DDR Pin function Modes 4 and 5 -- A6 output 0 PC6 input Mode 6 1 A6 output 0 PC6 input Mode 7 1 PC6 output 257 Pin PC5/A5/SCK1/ IRQ5 Selection Method and Pin Functions The pin function is switched as shown below according to the operating mode, bit C/A in the SCI1's SMR, bits CKE0 and CKE1 in SCR, and bit PC5DDR. Operating Mode PC5DDR CKE1 C/A CKE0 Pin function Modes 4 and 5 -- -- -- -- A5 output 0 PC5 input 0 1 SCK1 output 0 1 -- SCK1 output 0 1 -- -- SCK1 input Mode 6 1 -- -- -- A5 output IRQ5 input Operating Mode CKE1 C/A CKE0 PC5DDR Pin function 0 PC5 input 0 1 PC5 output 0 0 Mode 7 1 1 1 -- SCK1 output IRQ5 input -- -- SCK1 output -- -- -- SCK1 input 258 Pin PC4/A4/RxD1 Selection Method and Pin Functions The pin function is switched as shown below according to the operating mode, bit RE in the SCI1's SCR, and bit PC4DDR. Operating Mode PC4DDR RE Pin function Modes 4 and 5 -- -- A4 output 0 PC4 input 0 1 RxD1 input Mode 6 1 -- A4 output Operating Mode RE PC4DDR Pin function 0 PC4 input 0 Mode 7 1 1 PC4 output -- RxD1 input PC3/A3/TxD1 The pin function is switched as shown below according to the operating mode, bit TE in the SCI1's SCR, and bit PC3DDR. Operating Mode PC3DDR TE Pin function Modes 4 and 5 -- -- A3 output 0 PC3 input 0 1 TxD1 output Mode 6 1 -- A3 output Operating Mode TE PC3DDR Pin function 0 PC3 input 0 Mode 7 1 1 PC3 output -- TxD1 output 259 Pin PC2/A2/SCK0/ IRQ4 Selection Method and Pin Functions The pin function is switched as shown below according to the operating mode, bit C/A in the SCI0's SMR, bits CKE0 and CKE1 in SCR, and bit PC2DDR. Operating Mode PC2DDR CKE1 C/A CKE0 Pin function Modes 4 and 5 -- -- -- -- A2 output 0 PC2 input 0 1 SCK0 output 0 1 -- SCK0 output 0 1 -- -- SCK0 input Mode 6 1 -- -- -- A2 output IRQ4 input Operating Mode CKE1 C/A CKE0 PC2DDR Pin function 0 PC2 input 0 1 PC2 output 0 0 Mode 7 1 1 1 -- SCK0 output IRQ4 input -- -- SCK0 output -- -- -- SCK0 input 260 Pin PC1/A1/RxD0 Selection Method and Pin Functions The pin function is switched as shown below according to the operating mode, bit RE in the SCI0's SCR, and bit PC1DDR. Operating Mode PC1DDR RE Pin function Modes 4 and 5 -- -- A1 output 0 PC1 input 0 1 RxD0 input Mode 6 1 -- A1 output Operating Mode RE PC1DDR Pin function 0 PC1 input 0 Mode 7 1 1 PC1 output -- RxD0 input PC0/A0/TxD0 The pin function is switched as shown below according to the operating mode, bit TE in the SCI0's SCR, and bit PC0DDR. Operating Mode PC0DDR TE Pin function Modes 4 and 5 -- -- A0 output 0 PC0 input 0 1 TxD0 output Mode 6 1 -- A0 output Operating Mode TE PC0DDR Pin function 0 PC0 input 0 Mode 7 1 1 PC0 output -- TxD0 output 261 9.7.4 MOS Input Pull-Up Function Port C has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 6 and 7, and can be specified as on or off on an individual bit basis. In modes 6 and 7, if a pin is in the input state in accordance with the settings in the SCI's SMR and SCR, of pins IRQ4 and IRQ5, and in PCDDR, setting the corresponding PCPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a reset, and in hardware standby mode. The prior state is retained in software standby mode. Table 9-14 summarizes the MOS input pull-up states. Table 9-14 MOS Input Pull-Up States (Port C) Pin States Address output Other than above Power-On Reset OFF Hardware Standby Mode OFF Software Standby Mode OFF ON/OFF In Other Operations OFF ON/OFF Legend: OFF : MOS input pull-up is always off. ON/OFF : On when PCDDR = 0 and PCPCR = 1; otherwise off. 262 9.8 9.8.1 Port D Overview Port D is an 8-bit I/O port. Port D has a data bus I/O function, and the pin functions change according to the operating mode. Port D has a built-in MOS input pull-up function that can be controlled by software. Figure 9-7 shows the port D pin configuration. Port D pins PD7 / D15 PD6 / D14 PD5 / D13 Port D PD4 / D12 PD3 / D11 PD2 / D10 PD1/ D9 PD0/ D8 Pin functions in modes 4 to 6 D15 (I/O) D14 (I/O) D13 (I/O) D12 (I/O) D11 (I/O) D10 (I/O) D9 D8 (I/O) (I/O) Pin functions in mode 7 PD7 (I/O) PD6 (I/O) PD5 (I/O) PD4 (I/O) PD3 (I/O) PD2 (I/O) PD1 (I/O) PD0 (I/O) Figure 9-7 Port D Pin Functions 263 9.8.2 Register Configuration Table 9-15 shows the port D register configuration. Table 9-15 Port D Registers Name Port D data direction register Port D data register Port D register Port D MOS pull-up control register Note: * Lower 16 bits of the address. Abbreviation PDDDR PDDR PORTD PDPCR R/W W R/W R R/W Initial Value H'00 H'00 Undefined H'00 Address* H'FE3C H'FF0C H'FFBC H'FE43 Port D Data Direction Register (PDDDR) Bit : 7 6 5 4 3 2 1 0 PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR Initial value : R/W : 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W PDDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port D. PDDDR cannot be read; if it is, an undefined value will be read. PDDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. * Modes 4 to 6 The input/output direction specification by PDDDR is ignored, and port D is automatically designated for data I/O. * Mode 7 Setting a PDDDR bit to 1 makes the corresponding port D pin an output port, while clearing the bit to 0 makes the pin an input port. 264 Port D Data Register (PDDR) Bit : 7 PD7DR Initial value : R/W : 0 R/W 6 PD6DR 0 R/W 5 PD5DR 0 R/W 4 PD4DR 0 R/W 3 PD3DR 0 R/W 2 PD2DR 0 R/W 1 PD1DR 0 R/W 0 PD0DR 0 R/W PDDR is an 8-bit readable/writable register that stores output data for the port D pins (PD7 to PD0). PDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. Port D Register (PORTD) Bit : 7 PD7 Initial value : R/W : --* R 6 PD6 --* R 5 PD5 --* R 4 PD4 --* R 3 PD3 --* R 2 PD2 --* R 1 PD1 --* R 0 PD0 --* R Note: * Determined by state of pins PD7 to PD0. PORTD is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port D pins (PD7 to PD0) must always be performed on PDDR. If a port D read is performed while PDDDR bits are set to 1, the PDDR values are read. If a port D read is performed while PDDDR bits are cleared to 0, the pin states are read. After a reset and in hardware standby mode, PORTD contents are determined by the pin states, as PDDDR and PDDR are initialized. PORTD retains its prior state in software standby mode. 265 Port D MOS Pull-Up Control Register (PDPCR) Bit : 7 6 5 4 3 2 1 0 PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR Initial value : R/W : 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W PDPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port D on an individual bit basis. When a PDDDR bit is cleared to 0 (input port setting) in mode 7, setting the corresponding PDPCR bit to 1 turns on the MOS input pull-up for the corresponding pin. PDPCR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. 9.8.3 Pin Functions In modes 4 to 6, port D pins automatically function as data bus input/output pins (D15 to D8). In mode 7, each pin in port D functions as an input/output port, and input or output can be specified individually for each pin. Port D pin functions are shown in table 9-16. Table 9-16 Port D Pin Functions Pin PD7/D15, PD6/D14, PD5/D13, PD4/D12, PD3/D11, PD2/D10, PD1/D9, PD0/D8 Selection Method and Pin Functions The pin function is switched as shown below according to the operating mode and PDDDR. Operating mode PDnDDR Pin function -- Data bus input/ output (D15 to D8) Modes 4 to 6 0 PDn input Mode 7 1 PDn output n = 7 to 0 266 9.8.4 MOS Input Pull-Up Function Port D has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in mode 7, and can be specified as on or off on an individual bit basis. When a PDDDR bit is cleared to 0 in mode 7, setting the corresponding PDPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a reset, and in hardware standby mode. The prior state is retained in software standby mode. Table 9-17 summarizes the MOS input pull-up states. Table 9-17 MOS Input Pull-Up States (Port D) Modes 4 to 6 7 Power-On Reset OFF Hardware Standby Mode OFF Software Standby Mode OFF ON/OFF In Other Operations OFF ON/OFF Legend: OFF : MOS input pull-up is always off. ON/OFF : On when PDDDR = 0 and PDPCR = 1; otherwise off. 267 9.9 9.9.1 Port E Overview Port E is an 8-bit I/O port. Port E has a data bus I/O function, and the pin functions change according to the operating mode and whether 8-bit or 16-bit bus mode is selected. Port E has a built-in MOS input pull-up function that can be controlled by software. Figure 9-8 shows the port E pin configuration. Port E pins PE7/ D7 PE6/ D6 PE5/ D5 Port E PE4/ D4 PE3/ D3 PE2/ D2 PE1/ D1 PE0/ D0 Pin functions in modes 4 to 6 PE7 (I/O) / D7 (I/O) PE6 (I/O) / D6 (I/O) PE5 (I/O) / D5 (I/O) PE4 (I/O) / D4 (I/O) PE3 (I/O) / D3 (I/O) PE2 (I/O) / D2 (I/O) PE1 (I/O) / D1 (I/O) PE0 (I/O) / D0 (I/O) Pin functions in mode 7 PE7 (I/O) PE6 (I/O) PE5 (I/O) PE4 (I/O) PE3 (I/O) PE2 (I/O) PE1 (I/O) PE0 (I/O) Figure 9-8 Port E Pin Functions 268 9.9.2 Register Configuration Table 9-18 shows the port E register configuration. Table 9-18 Port E Registers Name Port E data direction register Port E data register Port E register Port E MOS pull-up control register Note: * Lower 16 bits of the address. Abbreviation PEDDR PEDR PORTE PEPCR R/W W R/W R R/W Initial Value H'00 H'00 Undefined H'00 Address* H'FE3D H'FF0D H'FFBD H'FE44 Port E Data Direction Register (PEDDR) Bit : 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR Initial value : R/W : PEDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port E. PEDDR cannot be read; if it is, an undefined value will be read. PEDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. * Modes 4 to 6 When 8-bit bus mode has been selected, port E pins function as I/O ports. Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the pin an input port. When 16-bit bus mode has been selected, the input/output direction specification by PEDDR is ignored, and port E is designated for data I/O. For details of 8-bit and 16-bit bus modes, see section 7, Bus Controller. * Mode 7 Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the pin an input port. 269 Port E Data Register (PEDR) Bit : 7 PE7DR Initial value : R/W : 0 R/W 6 PE6DR 0 R/W 5 PE5DR 0 R/W 4 PE4DR 0 R/W 3 PE3DR 0 R/W 2 PE2DR 0 R/W 1 PE1DR 0 R/W 0 PE0DR 0 R/W PEDR is an 8-bit readable/writable register that stores output data for the port E pins (PE7 to PE0). PEDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. Port E Register (PORTE) Bit : 7 PE7 Initial value : R/W : --* R 6 PE6 --* R 5 PE5 --* R 4 PE4 --* R 3 PE3 --* R 2 PE2 --* R 1 PE1 --* R 0 PE0 --* R Note: * Determined by state of pins PE7 to PE0. PORTE is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port E pins (PE7 to PE0) must always be performed on PEDR. If a port E read is performed while PEDDR bits are set to 1, the PEDR values are read. If a port E read is performed while PEDDR bits are cleared to 0, the pin states are read. After a reset and in hardware standby mode, PORTE contents are determined by the pin states, as PEDDR and PEDR are initialized. PORTE retains its prior state in software standby mode. 270 Port E MOS Pull-Up Control Register (PEPCR) Bit : 7 6 5 4 3 2 1 0 PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR Initial value : R/W : 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W PEPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port E on an individual bit basis. When a PEDDR bit is cleared to 0 (input port setting) with 8-bit bus mode selected in modes 4 to 6, or in mode 7, setting the corresponding PEPCR bit to 1 turns on the MOS input pull-up for the corresponding pin. PEPCR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. 9.9.3 Pin Functions Port E pins also function as data bus input/output pins (D7 to D0). If at least one of areas 0 to 7 is designated as 16-bit bus space in modes 4 to 6, port E pins automatically function as data bus input/output pins. If all areas are designated as 8-bit bus space in modes 4 to 6, or in mode 7, each pin in port E functions as an input/output port, and input or output can be specified individually for each pin. Port E pin functions are shown in table 9-19. Table 9-19 Port E Pin Functions Pin PE7/D7, PE6/D6, PE5/D5, PE4/D4, PE3/D3, PE2/D2, PE1/D1, PE0/D0 Selection Method and Pin Functions The pin function is switched as shown below according to the operating mode, ABWCR in the bus controller, and PEDDR. Operating mode ABWCR PEnDDR Pin function 0 PEn input Modes 4 to 6 H'FF 1 PEn output Not H'FF -- Data bus input/output (D7 to D0) -- 0 PEn input Mode 7 -- 1 PEn output n = 7 to 0 271 9.9.4 MOS Input Pull-Up Function Port E has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 4 to 6 when 8-bit bus mode is selected, or in mode 7, and can be specified as on or off on an individual bit basis. When a PEDDR bit is cleared to 0 in modes 4 to 6 when 8-bit bus mode is selected, or in mode 7, setting the corresponding PEPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a reset, and in hardware standby mode. The prior state is retained in software standby mode. Table 9-20 summarizes the MOS input pull-up states. Table 9-20 MOS Input Pull-Up States (Port E) Modes 7 4 to 6 8-bit bus 16-bit bus OFF OFF Power-On Reset OFF Hardware Standby Mode OFF Software Standby Mode ON/OFF In Other Operations ON/OFF Legend: OFF : MOS input pull-up is always off. ON/OFF : On when PEDDR = 0 and PEPCR = 1; otherwise off. 272 9.10 9.10.1 Port F Overview Port F is an 8-bit I/O port. Port F pins also function as external interrupt input pins (IRQ2 and IRQ3), BUZZ output pin*, A/D trigger input pin (ADTRG), bus control signal input/output pins (AS, RD, HWR, LWR, WAIT, BREQO, BREQ, and BACK) and the system clock (o) output pin. Note: * BUZZ output pin in the H8S/2626 Series only. Figure 9-9 shows the port F pin configuration. Port F pins PF7 /o PF6 /AS PF5 /RD Port F PF4 /HWR PF3 /LWR/ADTRG/IRQ3 PF2 /WAIT/ BREQO PF1 /BACK/BUZZ* PF0 /BREQ/IRQ2 Pin functions in modes 4 to 6 PF7 (input) / o (output) AS (output) RD (output) HWR (output) PF3 (I/O) / LWR (output) / ADTRG (input) / IRQ3 (input) PF2 (I/O) / WAIT (input) / BREQO (output) PF1 (I/O) / BACK (output) / BUZZ (output)* PF0 (I/O) / BREQ (input) / IRQ2 (input) Pin functions in mode 7 PF7 (input) / o (output) PF6 (I/O) PF5 (I/O) PF4 (I/O) PF3 (I/O) / ADTRG (input) / IRQ3 (input) PF2 (I/O) PF1 (I/O) / BUZZ (output)* PF0 (I/O) / IRQ2 (input) Note: * BUZZ output pin in the H8S/2626 Series only. Figure 9-9 Port F Pin Functions 273 9.10.2 Register Configuration Table 9-21 shows the port F register configuration. Table 9-21 Port F Registers Name Port F data direction register Port F data register Port F register Abbreviation PFDDR PFDR PORTF R/W W R/W R Initial Value H'80/H'00* 2 H'00 Undefined Address* 1 H'FE3E H'FF0E H'FFBE Notes: *1 Lower 16 bits of the address. *2 Initial value depends on the mode. Port F Data Direction Register (PFDDR) Bit : 7 6 5 4 3 2 1 0 PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR Modes 4 to 6 Initial value : R/W Mode 7 Initial value : R/W : 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W : 1 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W PFDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port F. PFDDR cannot be read; if it is, an undefined value will be read. PFDDR is initialized by a reset, and in hardware standby mode, to H'80 in modes 4 to 6, and to H'00 in mode 7. It retains its prior state in software standby mode. The OPE bit in SBYCR is used to select whether the bus control output pins retain their output state or become high-impedance when a transition is made to software standby mode. * Modes 4 to 6 Pin PF7 functions as the o output pin when the corresponding PFDDR bit is set to 1, and as an input port when the bit is cleared to 0. The input/output direction specified by PFDDR is ignored for pins PF6 to PF3, which are automatically designated as bus control outputs (AS, RD, HWR, and LWR). Pins PF2 to PF0 are designated as bus control input/output pins (WAIT, BREQO, BACK, BREQ) by means of bus controller settings. At other times, setting a PFDDR bit to 1 makes the corresponding port F pin an output port, while clearing the bit to 0 makes the pin an input port. 274 * Mode 7 Setting a PFDDR bit to 1 makes the corresponding port F pin PF6 to PF0 an output port, or in the case of pin PF7, the o output pin. Clearing the bit to 0 makes the pin an input port. Port F Data Register (PFDR) Bit : 7 -- Initial value : R/W : 0 R/W 6 PF6DR 0 R/W 5 PF5DR 0 R/W 4 PF4DR 0 R/W 3 PF3DR 0 R/W 2 PF2DR 0 R/W 1 PF1DR 0 R/W 0 PF0DR 0 R/W PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF7 to PF0). PFDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. Bit 7 in PFDR is reserved, and only 0 may be written to it. Port F Register (PORTF) Bit : 7 PF7 Initial value : R/W : --* R 6 PF6 --* R 5 PF5 --* R 4 PF4 --* R 3 PF3 --* R 2 PF2 --* R 1 PF1 --* R 0 PF0 --* R Note: * Determined by state of pins PF7 to PF0. PORTF is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port F pins (PF7 to PF0) must always be performed on PFDR. If a port F read is performed while PFDDR bits are set to 1, the PFDR values are read. If a port F read is performed while PFDDR bits are cleared to 0, the pin states are read. After a reset and in hardware standby mode, PORTF contents are determined by the pin states, as PFDDR and PFDR are initialized. PORTF retains its prior state in software standby mode. 275 9.10.3 Pin Functions Port F pins also function as external interrupt input pins (IRQ2 and IRQ3), BUZZ output pin*, A/D trigger input pin (ADTRG), bus control signal input/output pins (AS, RD, HWR, LWR, WAIT, BREQO, BREQ, and BACK) and the system clock (o) output pin. The pin functions differ between modes 4 to 6, and mode 7. Port F pin functions are shown in table 9-22. Note: * BUZZ output pin in the H8S/2626 Series only. Table 9-22 Port F Pin Functions Pin PF7/o Selection Method and Pin Functions The pin function is switched as shown below according to bit PF7DDR. PF7DDR Pin function 0 PF7 input 1 o output PF6/AS The pin function is switched as shown below according to the operating mode and bit PF6DDR. Operating Mode PF6DDR Pin function Modes 4 to 6 -- AS output 0 PF6 input Mode 7 1 PF6 output PF5/RD The pin function is switched as shown below according to the operating mode and bit PF5DDR. Operating Mode PF5DDR Pin function Modes 4 to 6 -- RD output 0 PF5 input Mode 7 1 PF5 output PF4/HWR The pin function is switched as shown below according to the operating mode and bit PF4DDR. Operating Mode PF4DDR Pin function Modes 4 to 6 -- HWR output 0 PF4 input Mode 7 1 PF4 output 276 Pin PF3/LWR/ ADTRG/IRQ3 Selection Method and Pin Functions The pin function is switched as shown below according to the operating mode, the bus mode, A/D converter bits TRGS1 and TRGS0, and bit PF3DDR. Operating Mode Bus mode PF3DDR Pin function 16-bit bus mode -- LWR output Modes 4 to 6 8-bit bus mode 0 PF3 input 1 0 1 Mode 7 -- 1 PF3 output PF3 output PF3 input ADTRG input IRQ3 input 2 Notes: *1 ADTRG input when TRGS0 = TRGS1 = 1. *2 When used as an external interrupt input pin, do not use as an I/O pin for another function. PF2/WAIT/ BREQO The pin function is switched as shown below according to the combination of the operating mode, and bits BREQOE, WAITE, ABW5 to ABW2, and PF2DDR. Operating Mode BREQOE WAITE PF2DDR Pin function 0 PF2 input 0 1 PF2 output Modes 4 to 6 0 1 -- WAIT input 1 -- -- BREQO output 0 PF2 input Mode 7 -- -- 1 PF2 output PF1/BACK/ BUZZ* The pin function is switched as shown below according to the combination of the operating mode, and bits BRLE, BUZZE, and PF1DDR. Operating Mode BRLE BUZZE PF1DDR Pin function 0 PF1 input 0 1 Modes 4 to 6 0 1 -- PF1 BUZZ* output output 1 -- -- BACK output 0 PF1 input 0 1 Mode 7 -- 1 -- PF1 BUZZ* output output Note: * BUZZ output pin in the H8S/2626 Series only. 277 Pin PF0/BREQ/IRQ2 Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the operating mode, and bits BRLE and PF0DDR. Operating Mode BRLE PF0DDR Pin function 0 PF0 input Modes 4 to 6 0 1 PF0 output 1 -- BREQ input IRQ2 input 0 PF0 input Mode 7 -- 1 PF0 output 278 Section 10 16-Bit Timer Pulse Unit (TPU) 10.1 Overview The H8S/2626 Series and H8S/2623 Series have an on-chip 16-bit timer pulse unit (TPU) that comprises six 16-bit timer channels. 10.1.1 Features * Maximum 16-pulse input/output A total of 16 timer general registers (TGRs) are provided (four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5), each of which can be set independently as an output compare/input capture register TGRC and TGRD for channels 0 and 3 can also be used as buffer registers * Selection of 8 counter input clocks for each channel * The following operations can be set for each channel: Waveform output at compare match: Selection of 0, 1, or toggle output Input capture function: Selection of rising edge, falling edge, or both edge detection Counter clear operation: Counter clearing possible by compare match or input capture Synchronous operation: Multiple timer counters (TCNT) can be written to simultaneously Simultaneous clearing by compare match and input capture possible Register simultaneous input/output possible by counter synchronous operation PWM mode: Any PWM output duty can be set Maximum of 15-phase PWM output possible by combination with synchronous operation * Buffer operation settable for channels 0 and 3 Input capture register double-buffering possible Automatic rewriting of output compare register possible * Phase counting mode settable independently for each of channels 1, 2, 4, and 5 Two-phase encoder pulse up/down-count possible * Cascaded operation Channel 2 (channel 5) input clock operates as 32-bit counter by setting channel 1 (channel 4) overflow/underflow * Fast access via internal 16-bit bus Fast access is possible via a 16-bit bus interface 279 * 26 interrupt sources For channels 0 and 3, four compare match/input capture dual-function interrupts and one overflow interrupt can be requested independently For channels 1, 2, 4, and 5, two compare match/input capture dual-function interrupts, one overflow interrupt, and one underflow interrupt can be requested independently * Automatic transfer of register data Block transfer, 1-word data transfer, and 1-byte data transfer possible by data transfer controller (DTC) * Programmable pulse generator (PPG) output trigger can be generated Channel 0 to 3 compare match/input capture signals can be used as PPG output trigger * A/D converter conversion start trigger can be generated Channel 0 to 5 compare match A/input capture A signals can be used as A/D converter conversion start trigger * Module stop mode can be set As the initial setting, TPU operation is halted. Register access is enabled by exiting module stop mode. Table 10-1 lists the functions of the TPU. 280 Table 10-1 TPU Functions Item Count clock Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 o/1 o/4 o/16 o/64 TCLKA TCLKB TCLKC TCLKD TGR0A TGR0B TGR0C TGR0D TIOCA0 TIOCB0 TIOCC0 TIOCD0 TGR compare match or input capture o/1 o/4 o/16 o/64 o/256 TCLKA TCLKB TGR1A TGR1B -- TIOCA1 TIOCB1 o/1 o/4 o/16 o/64 o/1024 TCLKA TCLKB TCLKC TGR2A TGR2B -- TIOCA2 TIOCB2 o/1 o/4 o/16 o/64 o/256 o/1024 o/4096 TCLKA TGR3A TGR3B TGR3C TGR3D TIOCA3 TIOCB3 TIOCC3 TIOCD3 TGR compare match or input capture o/1 o/4 o/16 o/64 o/1024 TCLKA TCLKC TGR4A TGR4B -- TIOCA4 TIOCB4 o/1 o/4 o/16 o/64 o/256 TCLKA TCLKC TCLKD TGR5A TGR5B -- TIOCA5 TIOCB5 General registers General registers/ buffer registers I/O pins Counter clear function TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture Compare 0 output match 1 output output Toggle output Input capture function Synchronous operation PWM mode Phase counting mode Buffer operation -- -- -- -- -- -- 281 Item Channel 0 Channel 1 TGR compare match or input capture TGR1A compare match or input capture TGR1A/ TGR1B compare match or input capture 4 sources Channel 2 TGR compare match or input capture TGR2A compare match or input capture TGR2A/ TGR2B compare match or input capture 4 sources Channel 3 TGR compare match or input capture TGR3A compare match or input capture Channel 4 TGR compare match or input capture TGR4A compare match or input capture Channel 5 TGR compare match or input capture TGR5A compare match or input capture -- DTC TGR activation compare match or input capture A/D TGR0A converter compare trigger match or input capture PPG trigger TGR0A/ TGR0B compare match or input capture 5 sources * -- TGR3A/ TGR3B compare match or input capture 5 sources 4 sources Compare * match or input capture 3A Compare * match or input capture 3B Compare * match or * input capture 3C Compare match or input capture 3D Overflow Interrupt sources 4 sources Compare match or input capture 5A Compare match or input capture 5B Overflow Underflow Compare * match or input capture 0A Compare * match or input capture 0B Compare * match or * input capture 0C Compare match or input capture 0D Overflow Compare * match or input capture 1A Compare * match or input capture 1B Overflow * Underflow * Compare * match or input capture 2A Compare * match or input capture 2B Overflow Underflow * Compare * match or input capture 4A Compare * match or input capture 4B Overflow * Underflow * * * * * * * Legend : Possible -- : Not possible 282 10.1.2 Block Diagram Figure 10-1 shows a block diagram of the TPU. TIORH TIORL TMDR Channel 3 TSR TGRC TGRD TGRA TGRB TCNT Control logic for channels 3 to 5 Input/output pins TIOCA3 Channel 3: TIOCB3 TIOCC3 TIOCD3 TIOCA4 Channel 4: TIOCB4 TIOCA5 Channel 5: TIOCB5 Channel 5 TGRA TIOR TIORH TIORL TMDR Channel 0 TSR Clock input Internal clock: o/1 o/4 o/16 o/64 o/256 o/1024 o/4096 External clock: TCLKA TCLKB TCLKC TCLKD TIER TCR Module data bus TSTR TSYR Bus interface TGRB TCNT Interrupt request signals Channel 3: TGI3A TGI3B TGI3C TGI3D TCI3V Channel 4: TGI4A TGI4B TCI4V TCI4U Channel 5: TGI5A TGI5B TCI5V TCI5U TMDR Channel 4 TSR TIER TCR TGRA TIOR TMDR TSR TIER TCR TGRB TCNT Common Control logic Internal data bus A/D converter convertion start signal PPG output trigger signal TGRC TIER TCR TGRD TGRA TGRB TCNT Control logic for channels 0 to 2 TMDR Input/output pins TIOCA0 Channel 0: TIOCB0 TIOCC0 TIOCD0 TIOCA1 Channel 1: TIOCB1 TIOCA2 Channel 2: TIOCB2 Interrupt request signals Channel 0: TGI0A TGI0B TGI0C TGI0D TCI0V Channel 1: TGI1A TGI1B TCI1V TCI1U Channel 2: TGI2A TGI2B TCI2V TCI2U TMDR Channel 1 TSR TGRA TGRA TIOR Channel 2 TSR TIER TCR TIOR Legend TSTR: TSYR: TCR: TMDR: Timer start register Timer synchro register Timer control register Timer mode register TIOR (H, L): TIER: TSR: TGR (A, B, C, D): Timer I/O control registers (H, L) Timer interrupt enable register Timer status register Timer general registers (A, B, C, D) Figure 10-1 Block Diagram of TPU 283 TIER TCR TGRB TCNT TGRB TCNT 10.1.3 Pin Configuration Table 10-2 summarizes the TPU pins. Table 10-2 TPU Pins Channel All Name Clock input A Symbol TCLKA I/O Input Function External clock A input pin (Channels 1 and 5 phase counting mode A phase input) External clock B input pin (Channels 1 and 5 phase counting mode B phase input) External clock C input pin (Channels 2 and 4 phase counting mode A phase input) External clock D input pin (Channels 2 and 4 phase counting mode B phase input) TGR0A input capture input/output compare output/PWM output pin TGR0B input capture input/output compare output/PWM output pin TGR0C input capture input/output compare output/PWM output pin TGR0D input capture input/output compare output/PWM output pin TGR1A input capture input/output compare output/PWM output pin TGR1B input capture input/output compare output/PWM output pin TGR2A input capture input/output compare output/PWM output pin TGR2B input capture input/output compare output/PWM output pin Clock input B TCLKB Input Clock input C TCLKC Input Clock input D TCLKD Input 0 Input capture/out TIOCA0 compare match A0 Input capture/out TIOCB0 compare match B0 Input capture/out TIOCC0 compare match C0 Input capture/out TIOCD0 compare match D0 I/O I/O I/O I/O I/O I/O I/O I/O 1 Input capture/out TIOCA1 compare match A1 Input capture/out TIOCB1 compare match B1 2 Input capture/out TIOCA2 compare match A2 Input capture/out TIOCB2 compare match B2 284 Channel 3 Name Symbol I/O I/O I/O I/O I/O I/O I/O I/O I/O Function TGR3A input capture input/output compare output/PWM output pin TGR3B input capture input/output compare output/PWM output pin TGR3C input capture input/output compare output/PWM output pin TGR3D input capture input/output compare output/PWM output pin TGR4A input capture input/output compare output/PWM output pin TGR4B input capture input/output compare output/PWM output pin TGR5A input capture input/output compare output/PWM output pin TGR5B input capture input/output compare output/PWM output pin Input capture/out TIOCA3 compare match A3 Input capture/out TIOCB3 compare match B3 Input capture/out TIOCC3 compare match C3 Input capture/out TIOCD3 compare match D3 4 Input capture/out TIOCA4 compare match A4 Input capture/out TIOCB4 compare match B4 5 Input capture/out TIOCA5 compare match A5 Input capture/out TIOCB5 compare match B5 285 10.1.4 Register Configuration Table 10-3 summarizes the TPU registers. Table 10-3 TPU Registers Channel Name 0 Timer control register 0 Timer mode register 0 Timer I/O control register 0H Timer I/O control register 0L Abbreviation TCR0 TMDR0 TIOR0H TIOR0L R/W R/W R/W R/W R/W R/W R/(W)* R/W R/W R/W R/W R/W R/W R/W R/W R/W R/(W)* R/W R/W R/W R/W R/W R/W R/W R/(W)* R/W R/W R/W 2 2 2 Initial Value H'00 H'C0 H'00 H'00 H'40 H'C0 H'0000 H'FFFF H'FFFF H'FFFF H'FFFF H'00 H'C0 H'00 H'40 H'C0 H'0000 H'FFFF H'FFFF H'00 H'C0 H'00 H'40 H'C0 H'0000 H'FFFF H'FFFF Address* 1 H'FF10 H'FF11 H'FF12 H'FF13 H'FF14 H'FF15 H'FF16 H'FF18 H'FF1A H'FF1C H'FF1E H'FF20 H'FF21 H'FF22 H'FF24 H'FF25 H'FF26 H'FF28 H'FF2A H'FF30 H'FF31 H'FF32 H'FF34 H'FF35 H'FF36 H'FF38 H'FF3A Timer interrupt enable register 0 TIER0 Timer status register 0 Timer counter 0 Timer general register 0A Timer general register 0B Timer general register 0C Timer general register 0D 1 Timer control register 1 Timer mode register 1 Timer I/O control register 1 TSR0 TCNT0 TGR0A TGR0B TGR0C TGR0D TCR1 TMDR1 TIOR1 Timer interrupt enable register 1 TIER1 Timer status register 1 Timer counter 1 Timer general register 1A Timer general register 1B 2 Timer control register 2 Timer mode register 2 Timer I/O control register 2 TSR1 TCNT1 TGR1A TGR1B TCR2 TMDR2 TIOR2 Timer interrupt enable register 2 TIER2 Timer status register 2 Timer counter 2 Timer general register 2A Timer general register 2B TSR2 TCNT2 TGR2A TGR2B 286 Channel Name 3 Timer control register 3 Timer mode register 3 Timer I/O control register 3H Timer I/O control register 3L Abbreviation TCR3 TMDR3 TIOR3H TIOR3L R/W R/W R/W R/W R/W R/W R/(W)* R/W R/W R/W R/W R/W R/W R/W R/W R/W R/(W)* R/W R/W R/W R/W R/W R/W R/W R/(W)* R/W R/W R/W R/W R/W R/W 2 2 2 Initial Value H'00 H'C0 H'00 H'00 H'40 H'C0 H'0000 H'FFFF H'FFFF H'FFFF H'FFFF H'00 H'C0 H'00 H'40 H'C0 H'0000 H'FFFF H'FFFF H'00 H'C0 H'00 H'40 H'C0 H'0000 H'FFFF H'FFFF H'00 H'00 H'3F Address* 1 H'FE80 H'FE81 H'FE82 H'FE83 H'FE84 H'FE85 H'FE86 H'FE88 H'FE8A H'FE8C H'FE8E H'FE90 H'FE91 H'FE92 H'FE94 H'FE95 H'FE96 H'FE98 H'FE9A H'FEA0 H'FEA1 H'FEA2 H'FEA4 H'FEA5 H'FEA6 H'FEA8 H'FEAA H'FEB0 H'FEB1 H'FDE8 Timer interrupt enable register 3 TIER3 Timer status register 3 Timer counter 3 Timer general register 3A Timer general register 3B Timer general register 3C Timer general register 3D 4 Timer control register 4 Timer mode register 4 Timer I/O control register 4 TSR3 TCNT3 TGR3A TGR3B TGR3C TGR3D TCR4 TMDR4 TIOR4 Timer interrupt enable register 4 TIER4 Timer status register 4 Timer counter 4 Timer general register 4A Timer general register 4B 5 Timer control register 5 Timer mode register 5 Timer I/O control register 5 TSR4 TCNT4 TGR4A TGR4B TCR5 TMDR5 TIOR5 Timer interrupt enable register 5 TIER5 Timer status register 5 Timer counter 5 Timer general register 5A Timer general register 5B All Timer start register Timer synchro register Module stop control register A TSR5 TCNT5 TGR5A TGR5B TSTR TSYR MSTPCRA Notes: *1 Lower 16 bits of the address. *2 Only 0 can be written, for flag clearing. 287 10.2 10.2.1 Register Descriptions Timer Control Register (TCR) Channel 0: TCR0 Channel 3: TCR3 Bit : 7 CCLR2 Initial value : R/W : 0 R/W 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 CKEG1 0 R/W 3 CKEG0 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W Channel 1: TCR1 Channel 2: TCR2 Channel 4: TCR4 Channel 5: TCR5 Bit : 7 -- Initial value : R/W : 0 -- 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 CKEG1 0 R/W 3 CKEG0 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W The TCR registers are 8-bit registers that control the TCNT channels. The TPU has six TCR registers, one for each of channels 0 to 5. The TCR registers are initialized to H'00 by a reset, and in hardware standby mode. TCR register settings should be made only when TCNT operation is stopped. 288 Bits 7 to 5--Counter Clear 2 to 0 (CCLR2 to CCLR0): These bits select the TCNT counter clearing source. Channel 0, 3 Bit 7 CCLR2 0 Bit 6 CCLR1 0 Bit 5 CCLR0 0 1 1 0 1 Description TCNT clearing disabled (Initial value) TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation* 1 TCNT clearing disabled TCNT cleared by TGRC compare match/input capture* 2 TCNT cleared by TGRD compare match/input capture* 2 TCNT cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation* 1 1 0 0 1 1 0 1 Channel 1, 2, 4, 5 Bit 6 Bit 7 Reserved* 3 CCLR1 0 0 Bit 5 CCLR0 0 1 Description TCNT clearing disabled (Initial value) TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation* 1 1 0 1 Notes: *1 Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. *2 When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. *3 Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be modified. 289 Bits 4 and 3--Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved (e.g. o/4 both edges = o/2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is ignored and the phase counting mode setting has priority. Bit 4 CKEG1 0 Bit 3 CKEG0 0 1 1 -- Description Count at rising edge Count at falling edge Count at both edges (Initial value) Note: Internal clock edge selection is valid when the input clock is o/4 or slower. This setting is ignored if the input clock is o/1, or when overflow/underflow of another channel is selected. Bits 2 to 0--Time Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the TCNT counter clock. The clock source can be selected independently for each channel. Table 10-4 shows the clock sources that can be set for each channel. Table 10-4 TPU Clock Sources Overflow/ Underflow on Another Internal Clock Channel 0 1 2 3 4 5 o/1 o/4 o/16 o/64 o/256 o/1024 o/4096 External Clock TCLKA TCLKB TCLKC TCLKD Channel Legend : Setting Blank : No setting 290 Channel 0 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 Description Internal clock: counts on o/1 Internal clock: counts on o/4 Internal clock: counts on o/16 Internal clock: counts on o/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input (Initial value) 1 0 1 1 0 0 1 1 0 1 Channel 1 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 Description Internal clock: counts on o/1 Internal clock: counts on o/4 Internal clock: counts on o/16 Internal clock: counts on o/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Internal clock: counts on o/256 Counts on TCNT2 overflow/underflow (Initial value) 1 0 1 1 0 0 1 1 0 1 Note: This setting is ignored when channel 1 is in phase counting mode. Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Channel 2 Description Internal clock: counts on o/1 Internal clock: counts on o/4 Internal clock: counts on o/16 Internal clock: counts on o/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input Internal clock: counts on o/1024 (Initial value) Note: This setting is ignored when channel 2 is in phase counting mode. 291 Channel 3 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 Description Internal clock: counts on o/1 Internal clock: counts on o/4 Internal clock: counts on o/16 Internal clock: counts on o/64 External clock: counts on TCLKA pin input Internal clock: counts on o/1024 Internal clock: counts on o/256 Internal clock: counts on o/4096 (Initial value) 1 0 1 1 0 0 1 1 0 1 Channel 4 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 Description Internal clock: counts on o/1 Internal clock: counts on o/4 Internal clock: counts on o/16 Internal clock: counts on o/64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on o/1024 Counts on TCNT5 overflow/underflow (Initial value) 1 0 1 1 0 0 1 1 0 1 Note: This setting is ignored when channel 4 is in phase counting mode. Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Channel 5 Description Internal clock: counts on o/1 Internal clock: counts on o/4 Internal clock: counts on o/16 Internal clock: counts on o/64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on o/256 External clock: counts on TCLKD pin input (Initial value) Note: This setting is ignored when channel 5 is in phase counting mode. 292 10.2.2 Timer Mode Register (TMDR) Channel 0: TMDR0 Channel 3: TMDR3 Bit : 7 -- Initial value : R/W : 1 -- 6 -- 1 -- 5 BFB 0 R/W 4 BFA 0 R/W 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W Channel 1: TMDR1 Channel 2: TMDR2 Channel 4: TMDR4 Channel 5: TMDR5 Bit : 7 -- Initial value : R/W : 1 -- 6 -- 1 -- 5 -- 0 -- 4 -- 0 -- 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode for each channel. The TPU has six TMDR registers, one for each channel. The TMDR registers are initialized to H'C0 by a reset, and in hardware standby mode. TMDR register settings should be made only when TCNT operation is stopped. Bits 7 and 6--Reserved: These bits are always read as 1 and cannot be modified. Bit 5--Buffer Operation B (BFB): Specifies whether TGRB is to operate in the normal way, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRD, bit 5 is reserved. It is always read as 0 and cannot be modified. Bit 5 BFB 0 1 Description TGRB operates normally TGRB and TGRD used together for buffer operation (Initial value) 293 Bit 4--Buffer Operation A (BFA): Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot be modified. Bit 4 BFA 0 1 Description TGRA operates normally TGRA and TGRC used together for buffer operation (Initial value) Bits 3 to 0--Modes 3 to 0 (MD3 to MD0): These bits are used to set the timer operating mode. Bit 3 MD3* 1 0 Bit 2 MD2* 2 0 Bit 1 MD1 0 Bit 0 MD0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Description Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 -- (Initial value) *: Don't care Notes: *1 MD3 is a reserved bit. In a write, it should always be written with 0. *2 Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always be written to MD2. 294 10.2.3 Timer I/O Control Register (TIOR) Channel 0: TIOR0H Channel 1: TIOR1 Channel 2: TIOR2 Channel 3: TIOR3H Channel 4: TIOR4 Channel 5: TIOR5 Bit : 7 IOB3 Initial value : R/W : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W 1 IOA1 0 R/W 0 IOA0 0 R/W Channel 0: TIOR0L Channel 3: TIOR3L Bit : 7 IOD3 Initial value : R/W : 0 R/W 6 IOD2 0 R/W 5 IOD1 0 R/W 4 IOD0 0 R/W 3 IOC3 0 R/W 2 IOC2 0 R/W 1 IOC1 0 R/W 0 IOC0 0 R/W Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. The TIOR registers are 8-bit registers that control the TGR registers. The TPU has eight TIOR registers, two each for channels 0 and 3, and one each for channels 1, 2, 4, and 5. The TIOR registers are initialized to H'00 by a reset, and in hardware standby mode. Care is required since TIOR is affected by the TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified. 295 Bits 7 to 4-- I/O Control B3 to B0 (IOB3 to IOB0) I/O Control D3 to D0 (IOD3 to IOD0): Bits IOB3 to IOB0 specify the function of TGRB. Bits IOD3 to IOD0 specify the function of TGRD. Channel 0 Bit 7 Bit 6 Bit 5 Bit 4 IOB3 IOB2 IOB1 IOB0 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR0B is input capture register Capture input source is TIOCB0 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT1 source is channel count- up/count-down* 1 1/count clock *: Don't care Description TGR0B Output disabled is output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match 296 Channel 0 Bit 7 Bit 6 Bit 5 Bit 4 IOD3 IOD2 IOD1 IOD0 0 0 0 0 1 1 0 1 1 0 1 0 1 0 1 1 0 0 0 1 1 1 * * * Description TGR0D Output disabled is output Initial output is 0 compare output register* 2 (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match TGR0D Capture input is input source is capture TIOCD0 pin register* 2 Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT1 source is channel count-up/count-down* 1 1/count clock *: Don't care Notes: *1 When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and o/1 is used as the TCNT1 count clock, this setting is invalid and input capture is not generated. *2 When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register, this setting is invalid and input capture/output compare is not generated. 297 Channel 1 Bit 7 Bit 6 Bit 5 Bit 4 IOB3 IOB2 IOB1 IOB0 0 0 0 0 1 1 0 1 1 0 1 0 1 0 1 1 0 0 0 1 1 1 * * * Description TGR1B Output disabled is output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match TGR1B is input capture register Capture input source is TIOCB1 pin Input capture at rising edge Input capture at falling edge Input capture at both edges Input capture at generation of Capture input source is TGR0C TGR0C compare match/input compare match/ capture input capture *: Don't care Channel 2 Bit 7 Bit 6 Bit 5 Bit 4 IOB3 IOB2 IOB1 IOB0 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * 0 0 1 1 * Description TGR2B Output disabled is output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match TGR2B is input capture register Capture input source is TIOCB2 pin Input capture at rising edge Input capture at falling edge Input capture at both edges *: Don't care 298 Channel 3 Bit 7 Bit 6 Bit 5 Bit 4 IOB3 IOB2 IOB1 IOB0 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * Description TGR3B Output disabled is output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match TGR3B is input capture register Capture input source is TIOCB3 pin Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT4 source is channel count-up/count-down* 1 4/count clock *: Don't care 299 Channel 3 Bit 7 Bit 6 Bit 5 Bit 4 IOD3 IOD2 IOD1 IOD0 0 0 0 0 1 1 0 1 1 0 1 0 1 0 1 1 0 0 0 1 1 1 * * * Description TGR3D Output disabled is output Initial output is 0 compare output register* 2 (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match TGR3D Capture input is input source is capture TIOCD3 pin register* 2 Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT4 source is channel count-up/count-down* 1 4/count clock *: Don't care Notes: *1 When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and o/1 is used as the TCNT4 count clock, this setting is invalid and input capture is not generated. *2 When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer register, this setting is invalid and input capture/output compare is not generated. 300 Channel 4 Bit 7 Bit 6 Bit 5 Bit 4 IOB3 IOB2 IOB1 IOB0 0 0 0 0 1 1 0 1 1 0 1 0 1 0 1 1 0 0 0 1 1 1 * * * Description TGR4B Output disabled is output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match TGR4B is input capture register Capture input source is TIOCB4 pin Input capture at rising edge Input capture at falling edge Input capture at both edges Input capture at generation of Capture input source is TGR3C TGR3C compare match/ compare match/ input capture input capture *: Don't care Channel 5 Bit 7 Bit 6 Bit 5 Bit 4 IOB3 IOB2 IOB1 IOB0 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * 0 0 1 1 * Description TGR5B Output disabled is output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match TGR5B is input capture register Capture input source is TIOCB5 pin Input capture at rising edge Input capture at falling edge Input capture at both edges *: Don't care 301 Bits 3 to 0-- I/O Control A3 to A0 (IOA3 to IOA0) I/O Control C3 to C0 (IOC3 to IOC0): IOA3 to IOA0 specify the function of TGRA. IOC3 to IOC0 specify the function of TGRC. Channel 0 Bit 3 Bit 2 Bit 1 Bit 0 IOA3 IOA2 IOA1 IOA0 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR0A is input capture register Capture input source is TIOCA0 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT1 source is channel count-up/count-down 1/ count clock *: Don't care Description TGR0A Output disabled is output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match 302 Channel 0 Bit 3 Bit 2 Bit 1 Bit 0 IOC3 IOC2 IOC1 IOC0 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * Description TGR0C Output disabled is output Initial output is 0 compare output register* 1 (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match TGR0C Capture input is input source is capture TIOCC0 pin register* 1 Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT1 source is channel count-up/count-down 1/count clock Note: *: Don't care *1 When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register, this setting is invalid and input capture/output compare is not generated. 303 Channel 1 Bit 3 Bit 2 Bit 1 Bit 0 IOA3 IOA2 IOA1 IOA0 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * Description TGR1A Output disabled is output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match TGR1A is input capture register Capture input source is TIOCA1 pin Input capture at rising edge Input capture at falling edge Input capture at both edges Input capture at generation of Capture input source is TGR0A channel 0/TGR0A compare compare match/ match/input capture input capture *: Don't care Channel 2 Bit 3 Bit 2 Bit 1 Bit 0 IOA3 IOA2 IOA1 IOA0 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * 0 0 1 1 * Description TGR2A Output disabled is output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match TGR2A is input capture register Capture input source is TIOCA2 pin Input capture at rising edge Input capture at falling edge Input capture at both edges *: Don't care 304 Channel 3 Bit 3 Bit 2 Bit 1 Bit 0 IOA3 IOA2 IOA1 IOA0 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * Description TGR3A Output disabled is output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match TGR3A is input capture register Capture input source is TIOCA3 pin Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT4 source is channel count-up/count-down 4/count clock *: Don't care 305 Channel 3 Bit 3 Bit 2 Bit 1 Bit 0 IOC3 IOC2 IOC1 IOC0 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * Description TGR3C Output disabled is output Initial output is 0 compare output register* 1 (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match TGR3C Capture input is input source is capture TIOCC3 pin register* 1 Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT4 source is channel count-up/count-down 4/count clock Note: *: Don't care *1 When the BFA bit in TMDR3 is set to 1 and TGR3C is used as a buffer register, this setting is invalid and input capture/output compare is not generated. 306 Channel 4 Bit 3 Bit 2 Bit 1 Bit 0 IOA3 IOA2 IOA1 IOA0 0 0 0 0 1 1 0 1 1 0 1 0 1 0 1 1 0 0 0 1 1 1 * * * Description TGR4A Output disabled is output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match TGR4A is input capture register Capture input source is TIOCA4 pin Input capture at rising edge Input capture at falling edge Input capture at both edges Input capture at generation of Capture input source is TGR3A TGR3A compare match/input compare match/ capture input capture *: Don't care Channel 5 Bit 3 Bit 2 Bit 1 Bit 0 IOA3 IOA2 IOA1 IOA0 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * 0 0 1 1 * Description TGR5A Output disabled is output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match TGR5A is input capture register Capture input source is TIOCA5 pin Input capture at rising edge Input capture at falling edge Input capture at both edges *: Don't care 307 10.2.4 Timer Interrupt Enable Register (TIER) Channel 0: TIER0 Channel 3: TIER3 Bit : 7 TTGE Initial value : R/W : 0 R/W 6 -- 1 -- 5 -- 0 -- 4 TCIEV 0 R/W 3 TGIED 0 R/W 2 TGIEC 0 R/W 1 TGIEB 0 R/W 0 TGIEA 0 R/W Channel 1: TIER1 Channel 2: TIER2 Channel 4: TIER4 Channel 5: TIER5 Bit : 7 TTGE Initial value : R/W : 0 R/W 6 -- 1 -- 5 TCIEU 0 R/W 4 TCIEV 0 R/W 3 -- 0 -- 2 -- 0 -- 1 TGIEB 0 R/W 0 TGIEA 0 R/W The TIER registers are 8-bit registers that control enabling or disabling of interrupt requests for each channel. The TPU has six TIER registers, one for each channel. The TIER registers are initialized to H'40 by a reset, and in hardware standby mode. 308 Bit 7--A/D Conversion Start Request Enable (TTGE): Enables or disables generation of A/D conversion start requests by TGRA input capture/compare match. Bit 7 TTGE 0 1 Description A/D conversion start request generation disabled A/D conversion start request generation enabled (Initial value) Bit 6--Reserved: This bit is always read as 1 and cannot be modified. Bit 5--Underflow Interrupt Enable (TCIEU): Enables or disables interrupt requests (TCIU) by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1, 2, 4, and 5. In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified. Bit 5 TCIEU 0 1 Description Interrupt requests (TCIU) by TCFU disabled Interrupt requests (TCIU) by TCFU enabled (Initial value) Bit 4--Overflow Interrupt Enable (TCIEV): Enables or disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1. Bit 4 TCIEV 0 1 Description Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled (Initial value) Bit 3--TGR Interrupt Enable D (TGIED): Enables or disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified. Bit 3 TGIED 0 1 Description Interrupt requests (TGID) by TGFD bit disabled Interrupt requests (TGID) by TGFD bit enabled (Initial value) 309 Bit 2--TGR Interrupt Enable C (TGIEC): Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified. Bit 2 TGIEC 0 1 Description Interrupt requests (TGIC) by TGFC bit disabled Interrupt requests (TGIC) by TGFC bit enabled (Initial value) Bit 1--TGR Interrupt Enable B (TGIEB): Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. Bit 1 TGIEB 0 1 Description Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled (Initial value) Bit 0--TGR Interrupt Enable A (TGIEA): Enables or disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1. Bit 0 TGIEA 0 1 Description Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled (Initial value) 310 10.2.5 Timer Status Register (TSR) Channel 0: TSR0 Channel 3: TSR3 Bit : 7 -- Initial value : R/W : 1 -- 6 -- 1 -- 5 -- 0 -- 4 TCFV 0 R/(W)* 3 TGFD 0 R/(W)* 2 TGFC 0 R/(W)* 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* Note: * Only 0 can be written, for flag clearing. Channel 1: TSR1 Channel 2: TSR2 Channel 4: TSR4 Channel 5: TSR5 Bit : 7 TCFD Initial value : R/W : 1 R 6 -- 1 -- 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* 3 -- 0 -- 2 -- 0 -- 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* Note: * Only 0 can be written, for flag clearing. The TSR registers are 8-bit registers that indicate the status of each channel. The TPU has six TSR registers, one for each channel. The TSR registers are initialized to H'C0 by a reset, and in hardware standby mode. 311 Bit 7--Count Direction Flag (TCFD): Status flag that shows the direction in which TCNT counts in channels 1, 2, 4, and 5. In channels 0 and 3, bit 7 is reserved. It is always read as 1 and cannot be modified. Bit 7 TCFD 0 1 Description TCNT counts down TCNT counts up (Initial value) Bit 6--Reserved: This bit is always read as 1 and cannot be modified. Bit 5--Underflow Flag (TCFU): Status flag that indicates that TCNT underflow has occurred when channels 1, 2, 4, and 5 are set to phase counting mode. In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified. Bit 5 TCFU 0 1 Description [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) (Initial value) Bit 4--Overflow Flag (TCFV): Status flag that indicates that TCNT overflow has occurred. Bit 4 TCFV 0 Description [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 ) (Initial value) 312 Bit 3--Input Capture/Output Compare Flag D (TGFD): Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified. Bit 3 TGFD 0 Description [Clearing conditions] * * 1 * * (Initial value) When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC is 0 When 0 is written to TGFD after reading TGFD = 1 [Setting conditions] When TCNT = TGRD while TGRD is functioning as output compare register When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register Bit 2--Input Capture/Output Compare Flag C (TGFC): Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified. Bit 2 TGFC 0 Description [Clearing conditions] * * 1 * * (Initial value) When DTC is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0 When 0 is written to TGFC after reading TGFC = 1 [Setting conditions] When TCNT = TGRC while TGRC is functioning as output compare register When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register 313 Bit 1--Input Capture/Output Compare Flag B (TGFB): Status flag that indicates the occurrence of TGRB input capture or compare match. Bit 1 TGFB 0 Description [Clearing conditions] * * 1 * * (Initial value) When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] When TCNT = TGRB while TGRB is functioning as output compare register When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register Bit 0--Input Capture/Output Compare Flag A (TGFA): Status flag that indicates the occurrence of TGRA input capture or compare match. Bit 0 TGFA 0 Description [Clearing conditions] * * 1 * * (Initial value) When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] When TCNT = TGRA while TGRA is functioning as output compare register When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register 314 10.2.6 Timer Counter (TCNT) Channel 0: TCNT0 (up-counter) Channel 1: TCNT1 (up/down-counter*) Channel 2: TCNT2 (up/down-counter*) Channel 3: TCNT3 (up-counter) Channel 4: TCNT4 (up/down-counter*) Channel 5: TCNT5 (up/down-counter*) Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: * These counters can be used as up/down-counters only in phase counting mode or when counting overflow/underflow on another channel. In other cases they function as upcounters. The TCNT registers are 16-bit counters. The TPU has six TCNT counters, one for each channel. The TCNT counters are initialized to H'0000 by a reset, and in hardware standby mode. The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. 315 10.2.7 Bit Timer General Register (TGR) : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : R/W 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The TGR registers are 16-bit registers with a dual function as output compare and input capture registers. The TPU has 16 TGR registers, four each for channels 0 and 3 and two each for channels 1, 2, 4, and 5. TGRC and TGRD for channels 0 and 3 can also be designated for operation as buffer registers*. The TGR registers are initialized to H'FFFF by a reset, and in hardware standby mode. The TGR registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. Note: * TGR buffer register combinations are TGRA--TGRC and TGRB--TGRD. 316 10.2.8 Bit Timer Start Register (TSTR) : 7 -- 6 -- 0 -- 5 CST5 0 R/W 4 CST4 0 R/W 3 CST3 0 R/W 2 CST2 0 R/W 1 CST1 0 R/W 0 CST0 0 R/W Initial value : R/W : 0 -- TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 5. TSTR is initialized to H'00 by a reset, and in hardware standby mode. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter. Bits 7 and 6--Reserved: Should always be written with 0. Bits 5 to 0--Counter Start 5 to 0 (CST5 to CST0): These bits select operation or stoppage for TCNT. Bit n CSTn 0 1 Description TCNTn count operation is stopped TCNTn performs count operation (Initial value) n = 5 to 0 Note: If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 317 10.2.9 Bit Timer Synchro Register (TSYR) : 7 -- 6 -- 0 -- 5 SYNC5 0 R/W 4 SYNC4 0 R/W 3 SYNC3 0 R/W 2 SYNC2 0 R/W 1 SYNC1 0 R/W 0 SYNC0 0 R/W Initial value : R/W : 0 -- TSYR is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channel 0 to 4 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. TSYR is initialized to H'00 by a reset, and in hardware standby mode. Bits 7 and 6--Reserved: Should always be written with 0. Bits 5 to 0--Timer Synchro 5 to 0 (SYNC5 to SYNC0): These bits select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, synchronous presetting of multiple channels*1, and synchronous clearing through counter clearing on another channel* 2 are possible. Notes: *1 To set synchronous operation, the SYNC bits for at least two channels must be set to 1. *2 To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing source must also be set by means of bits CCLR2 to CCLR0 in TCR. Bit n SYNCn 0 1 Description TCNTn operates independently (TCNT presetting/clearing is unrelated to other channels) (Initial value) TCNTn performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible n = 5 to 0 318 10.2.10 Bit Module Stop Control Register A (MSTPCRA) : 7 6 5 4 3 2 1 0 MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value : R/W : 0 R/W 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W MSTPCRA is an 8-bit readable/writable register that performs module stop mode control. When the MSTPA5 bit in MSTPCRA is set to 1, TPU operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see sections 21A.5, 21B.5, Module Stop Mode. MSTPCRA is initialized to H'3F by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 5--Module Stop (MSTPA5): Specifies the TPU module stop mode. Bit 5 MSTPA5 0 1 Description TPU module stop mode cleared TPU module stop mode set (Initial value) 319 10.3 10.3.1 Interface to Bus Master 16-Bit Registers TCNT and TGR are 16-bit registers. As the data bus to the bus master is 16 bits wide, these registers can be read and written to in 16-bit units. These registers cannot be read or written to in 8-bit units; 16-bit access must always be used. An example of 16-bit register access operation is shown in figure 10-2. Internal data bus H Bus master Module data bus L Bus interface TCNTH TCNTL Figure 10-2 16-Bit Register Access Operation [Bus Master TCNT (16 Bits)] 10.3.2 8-Bit Registers Registers other than TCNT and TGR are 8-bit. As the data bus to the CPU is 16 bits wide, these registers can be read and written to in 16-bit units. They can also be read and written to in 8-bit units. 320 Examples of 8-bit register access operation are shown in figures 10-3 to 10-5. Internal data bus H Bus master Module data bus L Bus interface TCR Figure 10-3 8-Bit Register Access Operation [Bus Master TCR (Upper 8 Bits)] Internal data bus H Bus master Module data bus L Bus interface TMDR Figure 10-4 8-Bit Register Access Operation [Bus Master TMDR (Lower 8 Bits)] Internal data bus H Bus master Module data bus L Bus interface TCR TMDR Figure 10-5 8-Bit Register Access Operation [Bus Master TCR and TMDR (16 Bits)] 321 10.4 10.4.1 Operation Overview Operation in each mode is outlined below. Normal Operation: Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, synchronous counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Synchronous Operation: When synchronous operation is designated for a channel, TCNT for that channel performs synchronous presetting. That is, when TCNT for a channel designated for synchronous operation is rewritten, the TCNT counters for the other channels are also rewritten at the same time. Synchronous clearing of the TCNT counters is also possible by setting the timer synchronization bits in TSYR for channels designated for synchronous operation. Buffer Operation * When TGR is an output compare register When a compare match occurs, the value in the buffer register for the relevant channel is transferred to TGR. * When TGR is an input capture register When input capture occurs, the value in TCNT is transfer to TGR and the value previously held in TGR is transferred to the buffer register. Cascaded Operation: The channel 1 counter (TCNT1), channel 2 counter (TCNT2), channel 4 counter (TCNT4), and channel 5 counter (TCNT5) can be connected together to operate as a 32bit counter. PWM Mode: In this mode, a PWM waveform is output. The output level can be set by means of TIOR. A PWM waveform with a duty of between 0% and 100% can be output, according to the setting of each TGR register. Phase Counting Mode: In this mode, TCNT is incremented or decremented by detecting the phases of two clocks input from the external clock input pins in channels 1, 2, 4, and 5. When phase counting mode is set, the corresponding TCLK pin functions as the clock pin, and TCNT performs up- or down-counting. This can be used for two-phase encoder pulse input. 322 10.4.2 Basic Functions Counter Operation: When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on. * Example of count operation setting procedure Figure 10-6 shows an example of the count operation setting procedure. Operation selection Select counter clock [1] [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. Free-running counter [2] For periodic counter operation, select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR. [3] Designate the TGR selected in [2] as an output compare register by means of TIOR. [4] Set the periodic counter cycle in the TGR selected in [2]. Start count operation Periodic counter Select counter clearing source [2] Select output compare register [3] Set period [4] Start count operation [5] Figure 10-6 Example of Counter Operation Setting Procedure 323 * Free-running count operation and periodic count operation Immediately after a reset, the TPU's TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts upcount operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the TPU requests an interrupt. After overflow, TCNT starts counting up again from H'0000. Figure 10-7 illustrates free-running counter operation. TCNT value H'FFFF H'0000 Time CST bit TCFV Figure 10-7 Free-Running Counter Operation When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant channel performs periodic count operation. The TGR register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits CCLR2 to CCLR0 in TCR. After the settings have been made, TCNT starts up-count operation as periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000. If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an interrupt. After a compare match, TCNT starts counting up again from H'0000. 324 Figure 10-8 illustrates periodic counter operation. Counter cleared by TGR compare match TCNT value TGR H'0000 Time CST bit Flag cleared by software or DTC activation TGF Figure 10-8 Periodic Counter Operation Waveform Output by Compare Match: The TPU can perform 0, 1, or toggle output from the corresponding output pin using compare match. * Example of setting procedure for waveform output by compare match Figure 10-9 shows an example of the setting procedure for waveform output by compare match [1] Select initial value 0 output or 1 output, and compare match output value 0 output, 1 output, or toggle output, by means of TIOR. The set initial value is output at the TIOC pin until the first compare match occurs. [2] Set the timing for compare match generation in TGR. Set output timing [2] Output selection Select waveform output mode [1] [3] Set the CST bit in TSTR to 1 to start the count operation. Start count operation [3] Figure 10-9 Example of Setting Procedure for Waveform Output by Compare Match 325 * Examples of waveform output operation Figure 10-10 shows an example of 0 output/1 output. In this example TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level coincide, the pin level does not change. TCNT value H'FFFF TGRA TGRB H'0000 No change TIOCA TIOCB No change No change No change 1 output 0 output Time Figure 10-10 Example of 0 Output/1 Output Operation Figure 10-11 shows an example of toggle output. In this example TCNT has been designated as a periodic counter (with counter clearing performed by compare match B), and settings have been made so that output is toggled by both compare match A and compare match B. TCNT value Counter cleared by TGRB compare match H'FFFF TGRB TGRA H'0000 Time Toggle output Toggle output TIOCB TIOCA Figure 10-11 Example of Toggle Output Operation 326 Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. For channels 0, 1, 3, and 4, it is also possible to specify another channel's counter input clock or compare match signal as the input capture source. Note: When another channel's counter input clock is used as the input capture input for channels 0 and 3, o/1 should not be selected as the counter input clock used for input capture input. Input capture will not be generated if o/1 is selected. * Example of input capture operation setting procedure Figure 10-12 shows an example of the input capture operation setting procedure. Input selection [1] Designate TGR as an input capture register by means of TIOR, and select rising edge, falling edge, or both edges as the input capture source and input signal edge. [1] Select input capture input [2] Set the CST bit in TSTR to 1 to start the count operation. Start count [2] Figure 10-12 Example of Input Capture Operation Setting Procedure 327 * Example of input capture operation Figure 10-13 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT. TCNT value H'0180 H'0160 Counter cleared by TIOCB input (falling edge) H'0010 H'0005 H'0000 Time TIOCA TGRA H'0005 H'0160 H'0010 TIOCB TGRB H'0180 Figure 10-13 Example of Input Capture Operation 328 10.4.3 Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 5 can all be designated for synchronous operation. Example of Synchronous Operation Setting Procedure: Figure 10-14 shows an example of the synchronous operation setting procedure. Synchronous operation selection Set synchronous operation [1] Synchronous presetting Synchronous clearing Set TCNT [2] Clearing sourcegeneration channel? Yes Select counter clearing source Start count No [3] Set synchronous counter clearing Start count [4] [5] [5] [1] [2] [3] [4] [5] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation. When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters. Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc. Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source. Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation. Figure 10-14 Example of Synchronous Operation Setting Procedure 329 Example of Synchronous Operation: Figure 10-15 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGR0B compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing sources. Three-phase PWM waveforms are output from pins TIOC0A, TIOC1A, and TIOC2A. At this time, synchronous presetting, and synchronous clearing by TGR0B compare match, is performed for channel 0 to 2 TCNT counters, and the data set in TGR0B is used as the PWM cycle. For details of PWM modes, see section 10.4.6, PWM Modes. Synchronous clearing by TGR0B compare match TCNT0 to TCNT2 values TGR0B TGR1B TGR0A TGR2B TGR1A TGR2A H'0000 Time TIOC0A TIOC1A TIOC2A Figure 10-15 Example of Synchronous Operation 330 10.4.4 Buffer Operation Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Table 10-5 shows the register combinations used in buffer operation. Table 10-5 Register Combinations in Buffer Operation Channel 0 Timer General Register TGR0A TGR0B 3 TGR3A TGR3B Buffer Register TGR0C TGR0D TGR3C TGR3D * When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 10-16. Compare match signal Buffer register Timer general register Comparator TCNT Figure 10-16 Compare Match Buffer Operation 331 * When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 10-17. Input capture signal Timer general register Buffer register TCNT Figure 10-17 Input Capture Buffer Operation Example of Buffer Operation Setting Procedure: Figure 10-18 shows an example of the buffer operation setting procedure. Buffer operation [1] Designate TGR as an input capture register or output compare register by means of TIOR. [1] Select TGR function [2] Designate TGR for buffer operation with bits BFA and BFB in TMDR. [3] Set the CST bit in TSTR to 1 to start the count operation. Set buffer operation [2] Start count [3] Figure 10-18 Example of Buffer Operation Setting Procedure 332 Examples of Buffer Operation * When TGR is an output compare register Figure 10-19 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B. As buffer operation has been set, when compare match A occurs the output changes and the value in buffer register TGRC is simultaneously transferred to timer general register TGRA. This operation is repeated each time compare match A occurs. For details of PWM modes, see section 10.4.6, PWM Modes. TCNT value TGR0B H'0200 TGR0A H'0000 TGR0C H'0200 Transfer TGR0A H'0200 H'0450 H'0450 H'0520 Time H'0520 H'0450 TIOCA Figure 10-19 Example of Buffer Operation (1) 333 * When TGR is an input capture register Figure 10-20 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge. As buffer operation has been set, when the TCNT value is stored in TGRA upon occurrence of input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC. TCNT value H'0F07 H'09FB H'0532 H'0000 Time TIOCA TGRA H'0532 H'0F07 H'09FB TGRC H'0532 H'0F07 Figure 10-20 Example of Buffer Operation (2) 334 10.4.5 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 (channel 4) counter clock upon overflow/underflow of TCNT2 (TCNT5) as set in bits TPSC2 to TPSC0 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode. Table 10-6 shows the register combinations used in cascaded operation. Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid and the counter operates independently in phase counting mode. Table 10-6 Cascaded Combinations Combination Channels 1 and 2 Channels 4 and 5 Upper 16 Bits TCNT1 TCNT4 Lower 16 Bits TCNT2 TCNT5 Example of Cascaded Operation Setting Procedure: Figure 10-21 shows an example of the setting procedure for cascaded operation. Cascaded operation [1] Set bits TPSC2 to TPSC0 in the channel 1 (channel 4) TCR to B'111 to select TCNT2 (TCNT5) overflow/underflow counting. [1] Set cascading [2] Set the CST bit in TSTR for the upper and lower channel to 1 to start the count operation. Start count [2] Figure 10-21 Cascaded Operation Setting Procedure 335 Examples of Cascaded Operation: Figure 10-22 illustrates the operation when counting upon TCNT2 overflow/underflow has been set for TCNT1, TGR1A and TGR2A have been designated as input capture registers, and TIOC pin rising edge has been selected. When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of the 32-bit data are transferred to TGR1A, and the lower 16 bits to TGR2A. TCNT1 clock TCNT1 TCNT2 clock TCNT2 TIOCA1, TIOCA2 TGR1A H'03A2 H'FFFF H'0000 H'0001 H'03A1 H'03A2 TGR2A H'0000 Figure 10-22 Example of Cascaded Operation (1) Figure 10-23 illustrates the operation when counting upon TCNT2 overflow/underflow has been set for TCNT1, and phase counting mode has been designated for channel 2. TCNT1 is incremented by TCNT2 overflow and decremented by TCNT2 underflow. TCLKA TCLKB TCNT2 FFFD FFFE FFFF 0000 0001 0002 0001 0000 FFFF TCNT1 0000 0001 0000 Figure 10-23 Example of Cascaded Operation (2) 336 10.4.6 PWM Modes In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each TGR. Designating TGR compare match as the counter clearing source enables the period to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. There are two PWM modes, as described below. * PWM mode 1 PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. The output specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR is output from the TIOCA and TIOCC pins at compare matches A and C, and the output specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR is output at compare matches B and D. The initial output value is the value set in TGRA or TGRC. If the set values of paired TGRs are identical, the output value does not change when a compare match occurs. In PWM mode 1, a maximum 8-phase PWM output is possible. * PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a synchronization register compare match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty registers are identical, the output value does not change when a compare match occurs. In PWM mode 2, a maximum 15-phase PWM output is possible by combined use with synchronous operation. The correspondence between PWM output pins and registers is shown in table 10-7. 337 Table 10-7 PWM Output Registers and Output Pins Output Pins Channel 0 Registers TGR0A TGR0B TGR0C TGR0D 1 TGR1A TGR1B 2 TGR2A TGR2B 3 TGR3A TGR3B TGR3C TGR3D 4 TGR4A TGR4B 5 TGR5A TGR5B TIOCA5 TIOCA4 TIOCC3 TIOCA3 TIOCA2 TIOCA1 TIOCC0 PWM Mode 1 TIOCA0 PWM Mode 2 TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 TIOCB5 Note: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set. 338 Example of PWM Mode Setting Procedure: Figure 10-24 shows an example of the PWM mode setting procedure. PWM mode Select counter clock [1] [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source. Select counter clearing source [2] Select waveform output level [3] [3] Use TIOR to designate the TGR as an output compare register, and select the initial value and output value. [4] Set the cycle in the TGR selected in [2], and set the duty in the other the TGR. [5] Select the PWM mode with bits MD3 to MD0 in TMDR. Set TGR [4] Set PWM mode [5] [6] Set the CST bit in TSTR to 1 to start the count operation. Start count [6] Figure 10-24 Example of PWM Mode Setting Procedure Examples of PWM Mode Operation: Figure 10-25 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value. In this case, the value set in TGRA is used as the period, and the values set in TGRB registers as the duty. 339 TCNT value TGRA Counter cleared by TGRA compare match TGRB H'0000 Time TIOCA Figure 10-25 Example of PWM Mode Operation (1) Figure 10-26 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGR1B compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGR0A to TGR0D, TGR1A), to output a 5-phase PWM waveform. In this case, the value set in TGR1B is used as the cycle, and the values set in the other TGRs as the duty. Counter cleared by TGR1B compare match TCNT value TGR1B TGR1A TGR0D TGR0C TGR0B TGR0A H'0000 Time TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 Figure 10-26 Example of PWM Mode Operation (2) 340 Figure 10-27 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode. TCNT value TGRA TGRB rewritten TGRB H'0000 0% duty TGRB rewritten TGRB rewritten Time TIOCA Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB H'0000 100% duty TGRB rewritten Time TIOCA Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB H'0000 100% duty 0% duty TGRB rewritten Time TIOCA Figure 10-27 Example of PWM Mode Operation (3) 341 10.4.7 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions can be used. When overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when underflow occurs while TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of whether TCNT is counting up or down. Table 10-8 shows the correspondence between external clock pins and channels. Table 10-8 Phase Counting Mode Clock Input Pins External Clock Pins Channels When channel 1 or 5 is set to phase counting mode When channel 2 or 4 is set to phase counting mode A-Phase TCLKA TCLKC B-Phase TCLKB TCLKD Example of Phase Counting Mode Setting Procedure: Figure 10-28 shows an example of the phase counting mode setting procedure. [1] Select phase counting mode with bits MD3 to MD0 in TMDR. [2] Set the CST bit in TSTR to 1 to start the count operation. Phase counting mode Select phase counting mode [1] Start count [2] Figure 10-28 Example of Phase Counting Mode Setting Procedure 342 Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. * Phase counting mode 1 Figure 10-29 shows an example of phase counting mode 1 operation, and table 10-9 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 10-29 Example of Phase Counting Mode 1 Operation Table 10-9 Up/Down-Count Conditions in Phase Counting Mode 1 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level Legend : Rising edge : Falling edge Down-count TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Up-count 343 * Phase counting mode 2 Figure 10-30 shows an example of phase counting mode 2 operation, and table 10-10 summarizes the TCNT up/down-count conditions. TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) TCNT value Up-count Down-count Time Figure 10-30 Example of Phase Counting Mode 2 Operation Table 10-10 Up/Down-Count Conditions in Phase Counting Mode 2 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level Legend : Rising edge : Falling edge TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Don't care Don't care Don't care Up-count Don't care Don't care Don't care Down-count 344 * Phase counting mode 3 Figure 10-31 shows an example of phase counting mode 3 operation, and table 10-11 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 10-31 Example of Phase Counting Mode 3 Operation Table 10-11 Up/Down-Count Conditions in Phase Counting Mode 3 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level Legend : Rising edge : Falling edge TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Don't care Don't care Don't care Up-count Down-count Don't care Don't care Don't care 345 * Phase counting mode 4 Figure 10-32 shows an example of phase counting mode 4 operation, and table 10-12 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Down-count Up-count Time Figure 10-32 Example of Phase Counting Mode 4 Operation Table 10-12 Up/Down-Count Conditions in Phase Counting Mode 4 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level Legend : Rising edge : Falling edge Don't care Down-count Don't care TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Up-count 346 Phase Counting Mode Application Example: Figure 10-33 shows an example in which phase counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect the position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB. Channel 0 operates with TCNT counter clearing by TGR0C compare match; TGR0A and TGR0C are used for the compare match function, and are set with the speed control period and position control period. TGR0B is used for input capture, with TGR0B and TGR0D operating in buffer mode. The channel 1 counter input clock is designated as the TGR0B input capture source, and detection of the pulse width of 2-phase encoder 4-multiplication pulses is performed. TGR1A and TGR1B for channel 1 are designated for input capture, channel 0 TGR0A and TGR0C compare matches are selected as the input capture source, and store the up/down-counter values for the control periods. This procedure enables accurate position/speed detection to be achieved. 347 Channel 1 TCLKA TCLKB Edge detection circuit TCNT1 TGR1A (speed period capture) TGR1B (position period capture) TCNT0 + TGR0A (speed control period) - TGR0C (position control period) + - TGR0B (pulse width capture) TGR0D (buffer operation) Channel 0 Figure 10-33 Phase Counting Mode Application Example 348 10.5 10.5.1 Interrupts Interrupt Sources and Priorities There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The interrupt request is cleared by clearing the status flag to 0. Relative channel priorities can be changed by the interrupt controller, but the priority order within a channel is fixed. For details, see section 5, Interrupt Controller. Table 10-13 lists the TPU interrupt sources. 349 Table 10-13 TPU Interrupts Channel 0 Interrupt Source TGI0A TGI0B TGI0C TGI0D TCI0V 1 TGI1A TGI1B TCI1V TCI1U 2 TGI2A TGI2B TCI2V TCI2U 3 TGI3A TGI3B TGI3C TGI3D TCI3V 4 TGI4A TGI4B TCI4V TCI4U 5 TGI5A TGI5B TCI5V TCI5U Description TGR0A input capture/compare match TGR0B input capture/compare match TGR0C input capture/compare match TGR0D input capture/compare match TCNT0 overflow TGR1A input capture/compare match TGR1B input capture/compare match TCNT1 overflow TCNT1 underflow TGR2A input capture/compare match TGR2B input capture/compare match TCNT2 overflow TCNT2 underflow TGR3A input capture/compare match TGR3B input capture/compare match TGR3C input capture/compare match TGR3D input capture/compare match TCNT3 overflow TGR4A input capture/compare match TGR4B input capture/compare match TCNT4 overflow TCNT4 underflow TGR5A input capture/compare match TGR5B input capture/compare match TCNT5 overflow TCNT5 underflow DTC Activation Possible Possible Possible Possible Not possible Possible Possible Not possible Not possible Possible Possible Not possible Not possible Possible Possible Possible Possible Not possible Possible Possible Not possible Not possible Possible Possible Not possible Not possible Low Priority High Note: This table shows the initial state immediately after a reset. The relative channel priorities can be changed by the interrupt controller. 350 Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5. Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt request is cleared by clearing the TCFV flag to 0. The TPU has six overflow interrupts, one for each channel. Underflow Interrupt: An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt request is cleared by clearing the TCFU flag to 0. The TPU has four underflow interrupts, one each for channels 1, 2, 4, and 5. 10.5.2 DTC Activation The DTC can be activated by the TGR input capture/compare match interrupt for a channel. For details, see section 8, Data Transfer Controller (DTC). A total of 16 TPU input capture/compare match interrupts can be used as DTC activation sources, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5. 10.5.3 A/D Converter Activation The A/D converter can be activated by the TGRA input capture/compare match for a channel. If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a TGRA input capture/compare match on a particular channel, a request to start A/D conversion is sent to the A/D converter. If the TPU conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is started. In the TPU, a total of six TGRA input capture/compare match interrupts can be used as A/D converter conversion start sources, one for each channel. 351 10.6 10.6.1 Operation Timing Input/Output Timing TCNT Count Timing: Figure 10-34 shows TCNT count timing in internal clock operation, and figure 10-35 shows TCNT count timing in external clock operation. o Internal clock Falling edge Rising edge TCNT input clock TCNT N-1 N N+1 N+2 Figure 10-34 Count Timing in Internal Clock Operation o External clock Falling edge Rising edge Falling edge TCNT input clock TCNT N-1 N N+1 N+2 Figure 10-35 Count Timing in External Clock Operation 352 Output Compare Output Timing: A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin. After a match between TCNT and TGR, the compare match signal is not generated until the TCNT input clock is generated. Figure 10-36 shows output compare output timing. o TCNT input clock TCNT N N+1 TGR N Compare match signal TIOC pin Figure 10-36 Output Compare Output Timing Input Capture Signal Timing: Figure 10-37 shows input capture signal timing. o Input capture input Input capture signal TCNT N N+1 N+2 TGR N N+2 Figure 10-37 Input Capture Input Signal Timing 353 Timing for Counter Clearing by Compare Match/Input Capture: Figure 10-38 shows the timing when counter clearing by compare match occurrence is specified, and figure 10-39 shows the timing when counter clearing by input capture occurrence is specified. o Compare match signal Counter clear signal N H'0000 TCNT TGR N Figure 10-38 Counter Clear Timing (Compare Match) o Input capture signal Counter clear signal N H'0000 TCNT TGR N Figure 10-39 Counter Clear Timing (Input Capture) 354 Buffer Operation Timing: Figures 10-40 and 10-41 show the timing in buffer operation. o TCNT n n+1 Compare match signal TGRA, TGRB TGRC, TGRD n N N Figure 10-40 Buffer Operation Timing (Compare Match) o Input capture signal TCNT TGRA, TGRB TGRC, TGRD N N+1 n N N+1 n N Figure 10-41 Buffer Operation Timing (Input Capture) 355 10.6.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match: Figure 10-42 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and TGI interrupt request signal timing. o TCNT input clock TCNT N N+1 TGR N Compare match signal TGF flag TGI interrupt Figure 10-42 TGI Interrupt Timing (Compare Match) 356 TGF Flag Setting Timing in Case of Input Capture: Figure 10-43 shows the timing for setting of the TGF flag in TSR by input capture occurrence, and TGI interrupt request signal timing. o Input capture signal TCNT N TGR N TGF flag TGI interrupt Figure 10-43 TGI Interrupt Timing (Input Capture) 357 TCFV Flag/TCFU Flag Setting Timing: Figure 10-44 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and TCIV interrupt request signal timing. Figure 10-45 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and TCIU interrupt request signal timing. o TCNT input clock TCNT (overflow) Overflow signal TCFV flag H'FFFF H'0000 TCIV interrupt Figure 10-44 TCIV Interrupt Setting Timing o TCNT input clock TCNT (underflow) Underflow signal H'0000 H'FFFF TCFU flag TCIU interrupt Figure 10-45 TCIU Interrupt Setting Timing 358 Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC is activated, the flag is cleared automatically. Figure 10-46 shows the timing for status flag clearing by the CPU, and figure 10-47 shows the timing for status flag clearing by the DTC. TSR write cycle T1 T2 o Address TSR address Write signal Status flag Interrupt request signal Figure 10-46 Timing for Status Flag Clearing by CPU DTC read cycle T1 o T2 DTC write cycle T1 T2 Address Source address Destination address Status flag Interrupt request signal Figure 10-47 Timing for Status Flag Clearing by DTC Activation 359 10.7 Usage Notes Note that the kinds of operation and contention described below occur during TPU operation. Input Clock Restrictions: The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 10-48 shows the input clock conditions in phase counting mode. Overlap TCLKA (TCLKC) TCLKB (TCLKD) Phase Phase differdifference Overlap ence Pulse width Pulse width Pulse width Pulse width Notes: Phase difference and overlap : 1.5 states or more : 2.5 states or more Pulse width Figure 10-48 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode Caution on Period Setting: When counter clearing by compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: f= Where o (N + 1) f : Counter frequency o : Operating frequency N : TGR set value 360 Contention between TCNT Write and Clear Operations: If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 10-49 shows the timing in this case. TCNT write cycle T1 T2 o Address TCNT address Write signal Counter clear signal TCNT N H'0000 Figure 10-49 Contention between TCNT Write and Clear Operations 361 Contention between TCNT Write and Increment Operations: If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 10-50 shows the timing in this case. TCNT write cycle T1 T2 o Address TCNT address Write signal TCNT input clock N TCNT write data M TCNT Figure 10-50 Contention between TCNT Write and Increment Operations 362 Contention between TGR Write and Compare Match: If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is inhibited. A compare match does not occur even if the same value as before is written. Figure 10-51 shows the timing in this case. TGR write cycle T1 T2 o Address TGR address Write signal Compare match signal TCNT N N+1 Inhibited TGR N TGR write data M Figure 10-51 Contention between TGR Write and Compare Match 363 Contention between Buffer Register Write and Compare Match: If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the data prior to the write. Figure 10-52 shows the timing in this case. TGR write cycle T1 T2 o Address Buffer register address Write signal Compare match signal Buffer register write data Buffer register TGR N M N Figure 10-52 Contention between Buffer Register Write and Compare Match 364 Contention between TGR Read and Input Capture: If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer. Figure 10-53 shows the timing in this case. TGR read cycle T1 T2 o Address TGR address Read signal Input capture signal TGR X M Internal data bus M Figure 10-53 Contention between TGR Read and Input Capture 365 Contention between TGR Write and Input Capture: If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 10-54 shows the timing in this case. TGR write cycle T1 T2 o Address TGR address Write signal Input capture signal TCNT M TGR M Figure 10-54 Contention between TGR Write and Input Capture 366 Contention between Buffer Register Write and Input Capture: If the input capture signal is generated in the T2 state of a buffer write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 10-55 shows the timing in this case. Buffer register write cycle T1 T2 o Address Buffer register address Write signal Input capture signal TCNT N TGR Buffer register M N M Figure 10-55 Contention between Buffer Register Write and Input Capture 367 Contention between Overflow/Underflow and Counter Clearing: If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 10-56 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is set in TGR. o TCNT input clock TCNT Counter clear signal TGF Disabled TCFV H'FFFF H'0000 Figure 10-56 Contention between Overflow and Counter Clearing 368 Contention between TCNT Write and Overflow/Underflow: If there is an up-count or downcount in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 10-57 shows the operation timing when there is contention between TCNT write and overflow. TCNT write cycle T1 T2 o Address TCNT address Write signal TCNT write data H'FFFF M TCNT TCFV flag Figure 10-57 Contention between TCNT Write and Overflow Multiplexing of I/O Pins: In the H8S/2626 Series and H8S/2623 Series, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input pin with the TIOCB2 I/O pin. When an external clock is input, compare match output should not be performed from a multiplexed pin. Interrupts and Module Stop Mode: If module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DTC activation source. Interrupts should therefore be disabled before entering module stop mode. 369 370 Section 11 Programmable Pulse Generator (PPG) 11.1 Overview The H8S/2626 Series and H8S/2623 Series have an on-chip programmable pulse generator (PPG) that provides pulse outputs by using the 16-bit timer pulse unit (TPU) as a time base. The PPG pulse outputs are divided into 4-bit groups (group 3 and group 2) that can operate both simultaneously and independently. 11.1.1 Features PPG features are listed below. * 8-bit output data Maximum 8-bit data can be output, and output can be enabled on a bit-by-bit basis * Two output groups Output trigger signals can be selected in 4-bit groups to provide up to two different 4-bit outputs * Selectable output trigger signals Output trigger signals can be selected for each group from the compare match signals of four TPU channels * Non-overlap mode A non-overlap margin can be provided between pulse outputs * Can operate together with the data transfer controller (DTC) The compare match signals selected as output trigger signals can activate the DTC for sequential output of data without CPU intervention * Settable inverted output Inverted data can be output for each group * Module stop mode can be set As the initial setting, PPG operation is halted. Register access is enabled by exiting module stop mode 371 11.1.2 Block Diagram Figure 11-1 shows a block diagram of the PPG. Compare match signals NDERH Control logic PMR NDERL PCR PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Pulse output pins, group 3 PODRH Pulse output pins, group 2 Pulse output pins, group 1 PODRL Pulse output pins, group 0 NDRL NDRH Internal data bus Legend PMR PCR NDERH NDERL NDRH NDRL PODRH PODRL : PPG output mode register : PPG output control register : Next data enable register H : Next data enable register L : Next data register H : Next data register L : Output data register H : Output data register L Figure 11-1 Block Diagram of PPG 372 11.1.3 Pin Configuration Table 11-1 summarizes the PPG pins. Table 11-1 PPG Pins Name Pulse output 8 Pulse output 9 Pulse output 10 Pulse output 11 Pulse output 12 Pulse output 13 Pulse output 14 Pulse output 15 Symbol PO8 PO9 PO10 PO11 PO12 PO13 PO14 PO15 I/O Output Output Output Output Output Output Output Output Group 3 pulse output Function Group 2 pulse output 373 11.1.4 Registers Table 11-2 summarizes the PPG registers. Table 11-2 PPG Registers Name PPG output control register PPG output mode register Next data enable register H Next data enable register L* Output data register H Output data register L* Next data register H Next data register L* 4 Port 1 data direction register Module stop control register A 4 4 Abbreviation PCR PMR NDERH NDERL PODRH PODRL NDRH NDRL P1DDR MSTPCRA R/W R/W R/W R/W R/W R/(W)* R/(W)* R/W R/W W R/W 2 2 Initial Value H'FF H'F0 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'3F Address* 1 H'FE26 H'FE27 H'FE28 H'FE29 H'FE2A H'FE2B H'FE2C* 3 H'FE2E H'FE2D* 3 H'FE2F H'FE30 H'FDE8 Notes: *1 Lower 16 bits of the address. *2 Bits used for pulse output cannot be written to. *3 When the same output trigger is selected for pulse output groups 2 and 3 by the PCR setting, the NDRH address is H'FE2C. When the output triggers are different, the NDRH address is H'FE2E for group 2 and H'FE2C for group 3 Similarly, when the same output trigger is selected for pulse output groups 0 and 1 by the PCR setting, the NDRL address is H'FE2D. When the output triggers are different, the NDRL address is H'FE2F for group 0 and H'FE2D for group 1. *4 The H8S/2626 Series and H8S/2623 Series have no pins corresponding to PODRL (pulse output groups 0 and 1). 374 11.2 11.2.1 Register Descriptions Next Data Enable Registers H and L (NDERH, NDERL) NDERH Bit : 7 6 5 4 3 2 1 0 NDER8 0 R/W NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 Initial value : R/W NDERL Bit : 7 NDER7 Initial value : R/W : 0 R/W 6 NDER6 0 R/W 5 NDER5 0 R/W 4 NDER4 0 R/W 3 NDER3 0 R/W 2 NDER2 0 R/W 1 NDER1 0 R/W : 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 NDER0 0 R/W NDERH and NDERL are 8-bit readable/writable registers that enable or disable pulse output on a bit-by-bit basis. If a bit is enabled for pulse output by NDERH or NDERL, the NDR value is automatically transferred to the corresponding PODR bit when the TPU compare match event specified by PCR occurs, updating the output value. If pulse output is disabled, the bit value is not transferred from NDR to PODR and the output value does not change. NDERH and NDERL are each initialized to H'00 by a reset and in hardware standby mode. They are not initialized in software standby mode. NDERH Bits 7 to 0--Next Data Enable 15 to 8 (NDER15 to NDER8): These bits enable or disable pulse output on a bit-by-bit basis. Bits 7 to 0 NDER15 to NDER8 0 1 Description Pulse outputs PO15 to PO8 are disabled (NDR15 to NDR8 are not transferred to POD15 to POD8) (Initial value) Pulse outputs PO15 to PO8 are enabled (NDR15 to NDR8 are transferred to POD15 to POD8) 375 NDERL Bits 7 to 0--Next Data Enable 7 to 0 (NDER7 to NDER0): These bits enable or disable pulse output on a bit-by-bit basis. Bits 7 to 0 NDER7 to NDER0 0 1 Description Pulse outputs PO7 to PO0 are disabled (NDR7 to NDR0 are not transferred to POD7 to POD0) (Initial value) Pulse outputs PO7 to PO0 are enabled (NDR7 to NDR0 are transferred to POD7 to POD0) 11.2.2 Output Data Registers H and L (PODRH, PODRL) PODRH Bit : 7 POD15 Initial value : R/W PODRL Bit : 7 POD7 Initial value : R/W : 0 R/(W)* 6 POD6 0 R/(W)* 5 POD5 0 R/(W)* 4 POD4 0 R/(W)* 3 POD3 0 R/(W)* 2 POD2 0 R/(W)* 1 POD1 0 R/(W)* 0 POD0 0 R/(W)* : 0 R/(W)* 6 POD14 0 R/(W)* 5 POD13 0 R/(W)* 4 POD12 0 R/(W)* 3 POD11 0 R/(W)* 2 POD10 0 R/(W)* 1 POD9 0 R/(W)* 0 POD8 0 R/(W)* Note: * A bit that has been set for pulse output by NDER is read-only. PODRH and PODRL are 8-bit readable/writable registers that store output data for use in pulse output. However, the H8S/2626 Series and H8S/2623 Series have no pins corresponding to PODRL. 376 11.2.3 Next Data Registers H and L (NDRH, NDRL) NDRH and NDRL are 8-bit readable/writable registers that store the next data for pulse output. During pulse output, the contents of NDRH and NDRL are transferred to the corresponding bits in PODRH and PODRL when the TPU compare match event specified by PCR occurs. The NDRH and NDRL addresses differ depending on whether pulse output groups have the same output trigger or different output triggers. For details see section 11.2.4, Notes on NDR Access. NDRH and NDRL are each initialized to H'00 by a reset and in hardware standby mode. They are not initialized in software standby mode. 11.2.4 Notes on NDR Access The NDRH and NDRL addresses differ depending on whether pulse output groups have the same output trigger or different output triggers. Same Trigger for Pulse Output Groups: If pulse output groups 2 and 3 are triggered by the same compare match event, the NDRH address is H'FE2C. The upper 4 bits belong to group 3 and the lower 4 bits to group 2. Address H'FE2E consists entirely of reserved bits that cannot be modified and are always read as 1. Address H'FE2C Bit : 7 NDR15 Initial value : R/W : 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W Address H'FE2E Bit : 7 -- Initial value : R/W : 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- If pulse output groups 0 and 1 are triggered by the same compare match event, the NDRL address is H'FE2D. The upper 4 bits belong to group 1 and the lower 4 bits to group 0. Address H'FE2F consists entirely of reserved bits that cannot be modified and are always read as 1. However, the H8S/2626 Series and H8S/2623 Series have no output pins corresponding to pulse output groups 0 and 1. 377 Address H'FE2D Bit : 7 NDR7 Initial value : R/W : 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W Address H'FE2F Bit : 7 -- Initial value : R/W : 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Different Triggers for Pulse Output Groups: If pulse output groups 2 and 3 are triggered by different compare match events, the address of the upper 4 bits in NDRH (group 3) is H'FE2C and the address of the lower 4 bits (group 2) is H'FE2E. Bits 3 to 0 of address H'FE2C and bits 7 to 4 of address H'FE2E are reserved bits that cannot be modified and are always read as 1. Address H'FE2C Bit : 7 NDR15 Initial value : R/W : 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Address H'FE2E Bit : 7 -- Initial value : R/W : 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W If pulse output groups 0 and 1 are triggered by different compare match event, the address of the upper 4 bits in NDRL (group 1) is H'FE2D and the address of the lower 4 bits (group 0) is H'FE2F. Bits 3 to 0 of address H'FE2D and bits 7 to 4 of address H'FE2F are reserved bits that cannot be modified and are always read as 1. However, the H8S/2626 Series and H8S/2623 Series have no output pins corresponding to pulse output groups 0 and 1. 378 Address H'FE2D Bit : 7 NDR7 Initial value : R/W : 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Address H'FE2F Bit : 7 -- Initial value : R/W : 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W 11.2.5 Bit PPG Output Control Register (PCR) : 7 6 5 4 3 2 1 0 G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value : R/W : 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W PCR is an 8-bit readable/writable register that selects output trigger signals for PPG outputs on a group-by-group basis. PCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 and 6--Group 3 Compare Match Select 1 and 0 (G3CMS1, G3CMS0): These bits select the compare match that triggers pulse output group 3 (pins PO15 to PO12). Description Bit 7 G3CMS1 0 Bit 6 G3CMS0 0 1 1 0 1 Output Trigger for Pulse Output Group 3 Compare match in TPU channel 0 Compare match in TPU channel 1 Compare match in TPU channel 2 Compare match in TPU channel 3 (Initial value) 379 Bits 5 and 4--Group 2 Compare Match Select 1 and 0 (G2CMS1, G2CMS0): These bits select the compare match that triggers pulse output group 2 (pins PO11 to PO8). Description Bit 5 G2CMS1 0 Bit 4 G2CMS0 0 1 1 0 1 Output Trigger for Pulse Output Group 2 Compare match in TPU channel 0 Compare match in TPU channel 1 Compare match in TPU channel 2 Compare match in TPU channel 3 (Initial value) Bits 3 and 2--Group 1 Compare Match Select 1 and 0 (G1CMS1, G1CMS0): These bits select the compare match that triggers pulse output group 1 (pins PO7 to PO4). However, the H8S/2626 Series and H8S/2623 Series have no output pins corresponding to pulse output group 1. Description Bit 3 G1CMS1 0 Bit 2 G1CMS0 0 1 1 0 1 Output Trigger for Pulse Output Group 1 Compare match in TPU channel 0 Compare match in TPU channel 1 Compare match in TPU channel 2 Compare match in TPU channel 3 (Initial value) Bits 1 and 0--Group 0 Compare Match Select 1 and 0 (G0CMS1, G0CMS0): These bits select the compare match that triggers pulse output group 0 (pins PO3 to PO0). However, the H8S/2626 Series and H8S/2623 Series have no output pins corresponding to pulse output group 0. Description Bit 1 G0CMS1 0 Bit 0 G0CMS0 0 1 1 0 1 Output Trigger for Pulse Output Group 0 Compare match in TPU channel 0 Compare match in TPU channel 1 Compare match in TPU channel 2 Compare match in TPU channel 3 (Initial value) 380 11.2.6 Bit PPG Output Mode Register (PMR) : 7 G3INV 6 G2INV 1 R/W 5 G1INV 1 R/W 4 G0INV 1 R/W 3 G3NOV 0 R/W 2 G2NOV 0 R/W 1 G1NOV 0 R/W 0 G0NOV 0 R/W Initial value : R/W : 1 R/W PMR is an 8-bit readable/writable register that selects pulse output inversion and non-overlapping operation for each group. The output trigger period of a non-overlapping operation PPG output waveform is set in TGRB and the non-overlap margin is set in TGRA. The output values change at compare match A and B. For details, see section 11.3.4, Non-Overlapping Pulse Output. PMR is initialized to H'F0 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7--Group 3 Inversion (G3INV): Selects direct output or inverted output for pulse output group 3 (pins PO15 to PO12). Bit 7 G3INV 0 1 Description Inverted output for pulse output group 3 (low-level output at pin for a 1 in PODRH) Direct output for pulse output group 3 (high-level output at pin for a 1 in PODRH) (Initial value) Bit 6--Group 2 Inversion (G2INV): Selects direct output or inverted output for pulse output group 2 (pins PO11 to PO8). Bit 6 G2INV 0 1 Description Inverted output for pulse output group 2 (low-level output at pin for a 1 in PODRH) Direct output for pulse output group 2 (high-level output at pin for a 1 in PODRH) (Initial value) 381 Bit 5--Group 1 Inversion (G1INV): Selects direct output or inverted output for pulse output group 1 (pins PO7 to PO4). However, the H8S/2626 Series and H8S/2623 Series have no pins corresponding to pulse output group 1. Bit 5 G1INV 0 1 Description Inverted output for pulse output group 1 (low-level output at pin for a 1 in PODRL) Direct output for pulse output group 1 (high-level output at pin for a 1 in PODRL) (Initial value) Bit 4--Group 0 Inversion (G0INV): Selects direct output or inverted output for pulse output group 0 (pins PO3 to PO0). However, the H8S/2626 Series and H8S/2623 Series have no pins corresponding to pulse output group 0. Bit 4 G0INV 0 1 Description Inverted output for pulse output group 0 (low-level output at pin for a 1 in PODRL) Direct output for pulse output group 0 (high-level output at pin for a 1 in PODRL) (Initial value) Bit 3--Group 3 Non-Overlap (G3NOV): Selects normal or non-overlapping operation for pulse output group 3 (pins PO15 to PO12). Bit 3 G3NOV 0 1 Description Normal operation in pulse output group 3 (output values updated at compare match A in the selected TPU channel) (Initial value) Non-overlapping operation in pulse output group 3 (independent 1 and 0 output at compare match A or B in the selected TPU channel) Bit 2--Group 2 Non-Overlap (G2NOV): Selects normal or non-overlapping operation for pulse output group 2 (pins PO11 to PO8). Bit 2 G2NOV 0 1 Description Normal operation in pulse output group 2 (output values updated at compare match A in the selected TPU channel) (Initial value) Non-overlapping operation in pulse output group 2 (independent 1 and 0 output at compare match A or B in the selected TPU channel) 382 Bit 1--Group 1 Non-Overlap (G1NOV): Selects normal or non-overlapping operation for pulse output group 1 (pins PO7 to PO4). However, the H8S/2626 Series and H8S/2623 Series have no pins corresponding to pulse output group 1. Bit 1 G1NOV 0 1 Description Normal operation in pulse output group 1 (output values updated at compare match A in the selected TPU channel) (Initial value) Non-overlapping operation in pulse output group 1 (independent 1 and 0 output at compare match A or B in the selected TPU channel) Bit 0--Group 0 Non-Overlap (G0NOV): Selects normal or non-overlapping operation for pulse output group 0 (pins PO3 to PO0). However, the H8S/2626 Series and H8S/2623 Series have no pins corresponding to pulse output group 0. Bit 0 G0NOV 0 1 Description Normal operation in pulse output group 0 (output values updated at compare match A in the selected TPU channel) (Initial value) Non-overlapping operation in pulse output group 0 (independent 1 and 0 output at compare match A or B in the selected TPU channel) 383 11.2.7 Bit Port 1 Data Direction Register (P1DDR) : 7 6 5 4 3 2 1 0 P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value : R/W : 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 1. Port 1 is multiplexed with pins PO15 to PO8. Bits corresponding to pins used for PPG output must be set to 1. For further information about P1DDR, see section 9.2, Port 1. 11.2.8 Bit Module Stop Control Register A (MSTPCRA) : 7 6 5 4 3 2 1 0 MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value : R/W : 0 R/W 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W MSTPCRA is a 16-bit readable/writable register that performs module stop mode control. When the MSTPA3 bit in MSTPCRA is set to 1, PPG operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see sections 21A.5, 21B.5, Module Stop Mode. MSTPCRA is initialized to H'3F by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 3--Module Stop (MSTPA3): Specifies the PPG module stop mode. Bit 3 MSTPA3 0 1 Description PPG module stop mode cleared PPG module stop mode set (Initial value) 384 11.3 11.3.1 Operation Overview PPG pulse output is enabled when the corresponding bits in P1DDR and NDER are set to 1. In this state the corresponding PODR contents are output. When the compare match event specified by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output values. Figure 11-2 illustrates the PPG output operation and table 11-3 summarizes the PPG operating conditions. DDR NDER Q Output trigger signal C Q PODR D Pulse output pin Normal output/inverted output Q NDR D Internal data bus Figure 11-2 PPG Output Operation Table 11-3 PPG Operating Conditions NDER 0 DDR 0 1 1 0 1 Pin Function Generic input port Generic output port Generic input port (but the PODR bit is a read-only bit, and when compare match occurs, the NDR bit value is transferred to the PODR bit) PPG pulse output Sequential output of data of up to 16 bits is possible by writing new output data to NDR before the next compare match. For details of non-overlapping operation, see section 11.3.4, NonOverlapping Pulse Output. 385 11.3.2 Output Timing If pulse output is enabled, NDR contents are transferred to PODR and output when the specified compare match event occurs. Figure 11-3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A. o TCNT N N+1 TGRA N Compare match A signal NDRH n PODRH m n PO8 to PO15 m n Figure 11-3 Timing of Transfer and Output of NDR Contents (Example) 386 11.3.3 Normal Pulse Output Sample Setup Procedure for Normal Pulse Output: Figure 11-4 shows a sample procedure for setting up normal pulse output. Normal PPG output Select TGR functions Set TGRA value TPU setup Set counting operation Select interrupt request Set initial output data Enable pulse output Port and PPG setup Select output trigger Set next pulse output data TPU setup Start counter Compare match? Yes Set next pulse output data [10] [3] [4] [5] [6] [7] [8] [1] [2] [1] Set TIOR to make TGRA an output compare register (with output disabled) [2] Set the PPG output trigger period [3] Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR1 and CCLR0. [4] Enable the TGIA interrupt in TIER. The DTC can also be set up to transfer data to NDR. [5] Set the initial output values in PODR. [6] Set the DDR and NDER bits for the pins to be used for pulse output to 1. [7] Select the TPU compare match event to be used as the output trigger in PCR. [8] Set the next pulse output values in NDR. [9] Set the CST bit in TSTR to 1 to start the TCNT counter. [10] At each TGIA interrupt, set the next output values in NDR. [9] No Figure 11-4 Setup Procedure for Normal Pulse Output (Example) 387 Example of Normal Pulse Output (Example of Five-Phase Pulse Output): Figure 11-5 shows an example in which pulse output is used for cyclic five-phase pulse output. TCNT value TGRA TCNT Compare match H'0000 NDRH 80 C0 40 60 20 30 10 18 08 88 80 C0 40 Time PODRH 00 80 C0 40 60 20 30 10 18 08 88 80 C0 PO15 PO14 PO13 PO12 PO11 Figure 11-5 Normal Pulse Output Example (Five-Phase Pulse Output) [1] Set up the TPU channel to be used as the output trigger channel so that TGRA is an output compare register and the counter will be cleared by compare match A. Set the trigger period in TGRA and set the TGIEA bit in TIER to 1 to enable the compare match A (TGIA) interrupt. [2] Write H'F8 in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0 bits in PCR to select compare match in the TPU channel set up in the previous step to be the output trigger. Write output data H'80 in NDRH. [3] The timer counter in the TPU channel starts. When compare match A occurs, the NDRH contents are transferred to PODRH and output. The TGIA interrupt handling routine writes the next output data (H'C0) in NDRH. [4] Five-phase overlapping pulse output (one or two phases active at a time) can be obtained subsequently by writing H'40, H'60, H'20, H'30. H'10, H'18, H'08, H'88... at successive TGIA interrupts. If the DTC is set for activation by this interrupt, pulse output can be obtained without imposing a load on the CPU. 388 11.3.4 Non-Overlapping Pulse Output Sample Setup Procedure for Non-Overlapping Pulse Output: Figure 11-6 shows a sample procedure for setting up non-overlapping pulse output. Non-overlapping PPG output Select TGR functions Set TGR values TPU setup Set counting operation Select interrupt request Set initial output data Enable pulse output Select output trigger Set non-overlapping groups Set next pulse output data TPU setup Start counter Compare match? Yes Set next pulse output data [11] [3] [4] [5] [6] [7] [8] [1] [2] [1] Set TIOR to make TGRA and TGRB an output compare registers (with output disabled) [2] Set the pulse output trigger period in TGRB and the non-overlap margin in TGRA. [3] Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR1 and CCLR0. [4] Enable the TGIA interrupt in TIER. The DTC can also be set up to transfer data to NDR. [5] Set the initial output values in PODR. [6] Set the DDR and NDER bits for the pins to be used for pulse output to 1. [7] Select the TPU compare match event to be used as the pulse output trigger in PCR. [8] In PMR, select the groups that will operate in non-overlap mode. [9] Set the next pulse output values in NDR. [10] Set the CST bit in TSTR to 1 to start the TCNT counter. [11] At each TGIA interrupt, set the next output values in NDR. PPG setup [9] [10] No Figure 11-6 Setup Procedure for Non-Overlapping Pulse Output (Example) 389 Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary NonOverlapping Output): Figure 11-7 shows an example in which pulse output is used for fourphase complementary non-overlapping pulse output. TCNT value TGRB TCNT TGRA H'0000 NDRH 95 65 59 56 95 65 Time PODRH 00 95 05 65 41 59 50 56 14 95 05 65 Non-overlap margin PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Figure 11-7 Non-Overlapping Pulse Output Example (Four-Phase Complementary) 390 [1] Set up the TPU channel to be used as the output trigger channel so that TGRA and TGRB are output compare registers. Set the trigger period in TGRB and the non-overlap margin in TGRA, and set the counter to be cleared by compare match B. Set the TGIEA bit in TIER to 1 to enable the TGIA interrupt. [2] Write H'FF in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0 bits in PCR to select compare match in the TPU channel set up in the previous step to be the output trigger. Set the G3NOV and G2NOV bits in PMR to 1 to select non-overlapping output. Write output data H'95 in NDRH. [3] The timer counter in the TPU channel starts. When a compare match with TGRB occurs, outputs change from 1 to 0. When a compare match with TGRA occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed by the value set in TGRA). The TGIA interrupt handling routine writes the next output data (H'65) in NDRH. [4] Four-phase complementary non-overlapping pulse output can be obtained subsequently by writing H'59, H'56, H'95... at successive TGIA interrupts. If the DTC is set for activation by this interrupt, pulse output can be obtained without imposing a load on the CPU. 391 11.3.5 Inverted Pulse Output If the G3INV, G2INV, G1INV, and G0INV bits in PMR are cleared to 0, values that are the inverse of the PODR contents can be output. Figure 11-8 shows the outputs when G3INV and G2INV are cleared to 0, in addition to the settings of figure 11-7. TCNT value TGRB TCNT TGRA H'0000 NDRH 95 65 59 56 95 65 Time PODRL 00 95 05 65 41 59 50 56 14 95 05 65 PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Figure 11-8 Inverted Pulse Output (Example) 392 11.3.6 Pulse Output Triggered by Input Capture Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA functions as an input capture register in the TPU channel selected by PCR, pulse output will be triggered by the input capture signal. Figure 11-9 shows the timing of this output. o TIOC pin Input capture signal NDR N PODR M N PO M N Figure 11-9 Pulse Output Triggered by Input Capture (Example) 393 11.4 Usage Notes Operation of Pulse Output Pins: Pins PO8 to PO15 are also used for other peripheral functions such as the TPU. When output by another peripheral function is enabled, the corresponding pins cannot be used for pulse output. Note, however, that data transfer from NDR bits to PODR bits takes place, regardless of the usage of the pins. Pin functions should be changed only under conditions in which the output trigger event will not occur. Note on Non-Overlapping Output: During non-overlapping operation, the transfer of NDR bit values to PODR bits takes place as follows. * NDR bits are always transferred to PODR bits at compare match A. * At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred if their value is 1. Figure 11-10 illustrates the non-overlapping pulse output operation. DDR NDER Q Compare match A Compare match B Pulse output pin C Q PODR D Q NDR D Internal data bus Normal output/inverted output Figure 11-10 Non-Overlapping Pulse Output 394 Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before compare match A. The NDR contents should not be altered during the interval from compare match B to compare match A (the non-overlap margin). This can be accomplished by having the TGIA interrupt handling routine write the next data in NDR, or by having the TGIA interrupt activate the DTC. Note, however, that the next data must be written before the next compare match B occurs. Figure 11-11 shows the timing of this operation. Compare match A Compare match B Write to NDR NDR Write to NDR PODR 0 output 0/1 output Write to NDR Do not write here to NDR here 0 output 0/1 output Write to NDR Do not write here to NDR here Figure 11-11 Non-Overlapping Operation and NDR Write Timing 395 396 Section 12 Watchdog Timer 12.1 Overview A single on-chip watchdog timer channel (WDT0) is provided in the H8S/2623 Series, and two watchdog timer channels (WDT0 and WDT1) in the H8S/2626 Series. The WDT outputs an overflow signal (WDTOVF) if a system crash prevents the CPU from writing to the timer counter, allowing it to overflow. At the same time, the WDT can also generate an internal reset signal for the H8S/2626 Series or H8S/2623 Series. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows. 12.1.1 Features WDT features are listed below. * Switchable between watchdog timer mode and interval timer mode * WDTOVF output when in watchdog timer mode If the counter overflows, the WDT outputs WDTOVF. It is possible to select whether the LSI is internally reset or an NMI interrupt is generated at the same time. * Interrupt generation when in interval timer mode If the counter overflows, the WDT generates an interval timer interrupt. * WDT0 and WDT1 respectively allow eight and sixteen types of counter input clock to be selected The maximum interval of the WDT is given as a system clock cycle x 131072 x 256. A subclock may be selected for the input counter of WDT1. Where a subclock is selected, the maximum interval is given as a subclock cycle x 256 x 256. * Selected clock can be output from the BUZZ output pin (WDT1) 397 12.1.2 Block Diagram Figures 12-1 (a) and 12-1 (b) show block diagrams of the WDT. Overflow WOVI 0 (interrupt request signal) Interrupt control Clock Clock select WDTOVF Internal reset signal* Reset control o/2 o/64 o/128 o/512 o/2048 o/8192 o/32768 o/131072 Internal clock sources Internal bus RSTCSR TCNT TSCR Module bus Bus interface WDT Legend : Timer control/status register TCSR : Timer counter TCNT RSTCSR : Reset control/status register Note: * The type of internal reset signal depends on a register setting. Figure 12-1 (a) Block Diagram of WDT0 398 WOVI1 (Interrupt request signal) Internal NMI Interrupt request signal Internal reset signal* Interrupt control Reset control Overflow Clock Clock select o/2 o/64 o/128 o/512 o/2048 o/8192 o/32768 o/131072 Internal clock oSUB/2 oSUB/4 oSUB/8 oSUB/16 oSUB/32 oSUB/64 oSUB/128 oSUB/256 TCNT TCSR Module bus WDT Legend: TCSR : Timer control/status register TCNT : Timer counter Note: * An internal reset signal can be generated by setting the register. Bus interface Figure 12-1 (b) Block Diagram of WDT1 Internal bus BUZZ 399 12.1.3 Pin Configuration Table 12-1 describes the WDT output pin. Table 12-1 WDT Pin Name Watchdog timer overflow Buzzer output * Symbol WDTOVF BUZZ I/O Output Output Function Outputs counter overflow signal in watchdog timer mode Outputs clock selected by watchdog timer (WDT1) Note: * Cannot be used in the H8S/2623 Series. 12.1.4 Register Configuration Table 12-2 summarizes the WDT register configuration. These registers control clock selection, WDT mode switching, and the reset signal. Table 12-2 WDT Registers Address* 1 Channel Name 0 Abbreviation R/W R/(W)*3 R/W R/(W)* R/(W)* R/W R/W 3 3 Initial Value Write*2 Read H'18 H'00 H'1F H'00 H'00 H'0D/H'00 H'FF74 H'FF74 H'FF74 H'FF75 H'FF76 H'FF77 H'FFA2 H'FFA2 H'FFA2 H'FFA3 H'FDEB Timer control/status register 0 TCSR0 Timer counter 0 Reset control/status register TCNT0 RSTCSR 1* 4 Timer control/status register 1 TCSR1 Timer counter 1 TCNT1 PFCR All Pin function control register Notes: *1 *2 *3 *4 Lower 16 bits of the address. For details of write operations, see section 12.2.5, Notes on Register Access. Only a write of 0 is permitted to bit 7, to clear the flag. Cannot be used in the H8S/2623 Series. 400 12.2 12.2.1 Bit Register Descriptions Timer Counter (TCNT) : 7 6 5 4 3 2 1 0 Initial value : R/W : 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W TCNT is an 8-bit readable/writable* up-counter. When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from the internal clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from H'FF to H'00), either the watchdog timer overflow signal (WDTOVF) or an interval timer interrupt (WOVI) is generated, depending on the mode selected by the WT/IT bit in TCSR. TCNT is initialized to H'00 by a reset, in hardware standby mode, or when the TME bit is cleared to 0. It is not initialized in software standby mode. Note: * TCNT is write-protected by a password to prevent accidental overwriting. For details see section 12.2.5, Notes on Register Access. 12.2.2 TCSR0 Bit : 7 OVF Initial value : R/W : 0 R/(W)* 6 WT/IT 0 R/W 5 TME 0 R/W 4 -- 1 -- 3 -- 1 -- 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Timer Control/Status Register (TCSR) Note: * Only a 0 can be written, for flag clearing. TCSR1* 1 Bit : 7 OVF Initial value : R/W : 0 R/(W)* 2 6 WT/IT 0 R/W 5 TME 0 R/W 4 PSS 0 R/W 3 RST/NMI 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Notes: *1 Cannot be used in the H8S/2623 Series. *2 Only a 0 can be written, for flag clearing. 401 TCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to be input to TCNT, and the timer mode. TCSR0 (TCSR1) is initialized to H'18 (H'00) by a reset and in hardware standby mode. It is not initialized in software standby mode. Note: * TCSR is write-protected by a password to prevent accidental overwriting. For details see section 12.2.5, Notes on Register Access. Bit 7--Overflow Flag (OVF): Indicates that TCNT has overflowed from H'FF to H'00. Bit 7 OVF 0 Description [Clearing conditions] * Cleared when 0 is written to the TME bit (Only applies to WDT1) * Cleared by reading TCSR when OVF = 1, then writing 0 to OVF [Setting condition] When TCNT overflows (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset. (Initial value) 1 In interval tmer mode, to clear OVF flag in WOVI handling routine, read TCSR when OVF = 1, then write with 0 to OVF, as stated above. When WOVI is masked and OVF flag is poling, if contention between OVF flag set and TCSR read is occurred, OVF = 1 is read but OVF can not be cleared by writing with 0 to OVF. In this case, reading TCSR when OVF = 1 two times meet the requirements of OVF clear condition. Please read TCSR when OVF = 1 two times before writing with 0 to OVF. Bit 6--Timer Mode Select (WT/IT): Selects whether the WDT is used as a watchdog timer or interval timer. When TCNT overflows, WDT0 generates the WDTOVF signal when in watchdog timer mode, or a WOVI interrupt request to the CPU when in interval timer mode. WDT1 generates a reset or NMI interrupt request when in watchdog timer mode, or a WOVI interrupt request to the CPU when in interval timer mode. WDT0 Mode Select WDT0 WT/IT 0 1 Description Interval timer mode: WDT0 requests an interval timer interrupt (WOVI) from the CPU when the TCNT overflows. (Initial value) Watchdog timer mode: WDT0 outputs a WDTOVF signal when the TCNT overflows.* Note: * For details on a TCNT overflow in watchdog timer mode, see section 12.2.3, Reset Control/Status Register (RSTCSR). 402 WDT1 Mode Select* WDT1 WT/IT 0 1 Description Interval timer mode: WDT1 requests an interval timer interrupt (WOVI) from the CPU when the TCNT overflows. Watchdog timer mode: WDT1 requests a reset or an NMI interrupt from the CPU when the TCNT overflows. (Initial value) Note: * Cannot be used in the H8S/2623 Series. Bit 5--Timer Enable (TME): Selects whether TCNT runs or is halted. Bit 5 TME 0 1 Description TCNT is initialized to H'00 and halted TCNT counts (Initial value) WDT0 TCSR Bit 4--Reserved Bit: This bit is always read as 1 and cannot be modified. WDT1 TCSR Bit 4--Prescaler Select (PSS): This bit is used to select an input clock source for the TCNT of WDT1. See the descriptions of Clock Select 2 to 0 for details. This bit cannot be used in the H8S/2623 Series. WDT1 TCSR Bit 4 PSS 0 1 Description The TCNT counts frequency-division clock pulses of the o based prescaler (PSM). (Initial value) The TCNT counts frequency-division clock pulses of the o SUB-based prescaler (PSS). 403 WDT0 TCSR Bit 3--Reserved Bit: This bit is always read as 1 and cannot be modified. WDT1 TCSR Bit 3--Reset or NMI (RST/NMI): This bit is used to choose between an internal reset request and an NMI request when the TCNT overflows during the watchdog timer mode. This bit cannot be used in the H8S/2623 Series. Bit 3 RTS/NMI 0 1 Description NMI request. Internal reset request. (Initial value) Bits 2 to 0--Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock sources, obtained by dividing the system clock (o) or subclock (o SUB), for input to TCNT. WDT0 Input Clock Select Bit 2 CKS2 0 Bit 1 CKS1 0 Bit 0 CKS0 0 1 1 0 1 1 0 0 1 1 0 1 Clock o/2 (Initial value) o/64 o/128 o/512 o/2048 o/8192 o/32768 o/131072 Description Overflow Period* (where o = 20 MHz) 25.6 s 819.2 s 1.6 ms 6.6 ms 26.2 ms 104.9 ms 419.4 ms 1.68 s Note: * An overflow period is the time interval between the start of counting up from H'00 on the TCNT and the occurrence of a TCNT overflow. 404 WDT1 Input Clock Select*2 Description Bit 4 PSS 0 Bit 2 CKS2 0 Bit 1 CKS1 0 Bit 0 CKS0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Clock o/2 (Initial value) o/64 o/128 o/512 o/2048 o/8192 o/32768 o/131072 oSUB/2 oSUB/4 oSUB/8 oSUB/16 oSUB/32 oSUB/64 oSUB/128 oSUB/256 Overflow Period* 1 (where o = 20 MHz) (where o SUB = 32.768 kHz) 25.6 s 819.2 s 1.6 ms 6.6 ms 26.2 ms 104.9 ms 419.4 ms 1.68 s 15.6 ms 31.3 ms 62.5 ms 125 ms 250 ms 500 ms 1s 2s Notes: *1 An overflow period is the time interval between the start of counting up from H'00 on the TCNT and the occurrence of a TCNT overflow. *2 Cannot be used in the H8S/2623 Series. 405 12.2.3 Bit Reset Control/Status Register (RSTCSR) : 7 WOVF 6 RSTE 0 R/W 5 RSTS 0 R/W 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Initial value : R/W : 0 R/(W)* Note: * Only 0 can be written, for flag clearing. RSTCSR is an 8-bit readable/writable* register that controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal reset signal caused by overflows. Note: * RSTCSR is write-protected by a password to prevent accidental overwriting. For details see section 12.2.5, Notes on Register Access. Bit 7--Watchdog Overflow Flag (WOVF): Indicates that TCNT has overflowed (changed from H'FF to H'00) during watchdog timer operation. This bit is not set in interval timer mode. Bit 7 WOVF 0 Description [Clearing condition] Cleared by reading TCSR when WOVF = 1, then writing 0 to WOVF 1 [Setting condition] Set when TCNT overflows (changed from H'FF to H'00) during watchdog timer operation (Initial value) Bit 6--Reset Enable (RSTE): Specifies whether or not a reset signal is generated in the chip if TCNT overflows during watchdog timer operation. Bit 6 RSTE 0 1 Description Reset signal is not generated if TCNT overflows* Reset signal is generated if TCNT overflows (Initial value) Note: * The modules within the chip are not reset, but TCNT and TCSR within the WDT are reset. 406 Bit 5--Reset Select (RSTS): Selects the type of internal reset generated if TCNT overflows during watchdog timer operation. For details of the types of reset, see section 4, Exception Handling. Bit 5 RSTS 0 1 Description Power-on reset Setting prohibited (Initial value) Bits 4 to 0--Reserved: These bits are always read as 1 and cannot be modified. 12.2.4 Bit Pin Function Control Register (PFCR) : 7 -- 6 -- 0 R/W 5 BUZZE 0 R/W 4 -- 0 R/W 3 AE3 1/0 R/W 2 AE2 1/0 R/W 1 AE1 0 R/W 0 AE0 1/0 R/W Initial value : R/W : 0 R/W PFCR is an 8-bit readable/writable register that performs address output control in external expanded mode. Only bit 5 is described here. For details of the other bits, see section 7.2.6, Pin Function Control Register (PFCR). Bit 5--BUZZ Output Enable (BUZZE)*: Enables or disables BUZZ output from the PF1 pin. The WDT1 input clock selected with bits PSS and CKS2 to CKS0 is output as the BUZZ signal. Note: * In the H8S/2623 Series this bit is reserved, and must be written with 0. Bit 5 BUZZE 0 1 Description Functions as PF1 I/O pin Functions as BUZZ output pin (Initial value) 407 12.2.5 Notes on Register Access The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. Writing to TCNT and TCSR: These registers must be written to by a word transfer instruction. They cannot be written to with byte instructions. Figure 12-2 shows the format of data written to TCNT and TCSR. TCNT and TCSR both have the same write address. For a write to TCNT, the upper byte of the written word must contain H'5A and the lower byte must contain the write data. For a write to TCSR, the upper byte of the written word must contain H'A5 and the lower byte must contain the write data. This transfers the write data from the lower byte to TCNT or TCSR. TCNT write 15 Address: H'FF74 H'5A 87 Write data 0 TCSR write 15 Address: H'FF74 H'A5 87 Write data 0 Figure 12-2 Format of Data Written to TCNT and TCSR 408 Writing to RSTCSR: RSTCSR must be written to by word transfer instruction to address H'FF76. It cannot be written to with byte instructions. Figure 12-3 shows the format of data written to RSTCSR. The method of writing 0 to the WOVF bit differs from that for writing to the RSTE and RSTS bits. To write 0 to the WOVF bit, the write data must have H'A5 in the upper byte and H'00 in the lower byte. This clears the WOVF bit to 0, but has no effect on the RSTE and RSTS bits. To write to the RSTE and RSTS bits, the upper byte must contain H'5A and the lower byte must contain the write data. This writes the values in bits 6 and 5 of the lower byte into the RSTE and RSTS bits, but has no effect on the WOVF bit. Writing 0 to WOVF bit 15 Address: H'FF76 H'A5 87 H'00 0 Writing to RSTE and RSTS bits 15 Address: H'FF76 H'5A 87 Write data 0 Figure 12-3 Format of Data Written to RSTCSR Reading TCNT, TCSR, and RSTCSR (WDT0): These registers are read in the same way as other registers. The read addresses are H'FF74 for TCSR, H'FF75 for TCNT, and H'FF77 for RSTCSR. 409 12.3 12.3.1 Operation Watchdog Timer Operation To use the WDT as a watchdog timer, set the WT/IT bit in TCSR and TME bit to 1. Software must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflows occurs. This ensures that TCNT does not overflow while the system is operating normally. If TCNT overflows without being rewritten because of a system crash or other error, in the WDT0 the WDTOVF signal is output. This is shown in figure 12-4(a). This WDTOVF signal can be used to reset the system. The WDTOVF signal is output for 132 states when RSTE = 1, and for 130 states when RSTE = 0. If TCNT overflows when 1 is set in the RSTE bit in RSTCSR, a signal that resets the chip internally is generated at the same time as the WDTOVF signal. This reset can be selected as a power-on reset or a manual reset, depending on the setting of the RSTS bit in RSTCSR. The internal reset signal is output for 518 states. If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a WDT overflow, the RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0. In the case of WDT1, the chip is reset, or an NMI interrupt request is generated, for 516 system clock periods (516o) (515 or 516 states when the clock source is oSUB (PSS = 1)). This is illustrated in figure 12-4 (b). An NMI request from the watchdog timer and an interrupt request from the NMI pin are both treated as having the same vector. So, avoid handling an NMI request from the watchdog timer and an interrupt request from the NMI pin at the same time. 410 TCNT count Overflow H'FF H'00 WT/IT=1 TME=1 H'00 written to TCNT WOVF=1 WDTOVF and internal reset are generated WT/IT=1 TME=1 H'00 written to TCNT Time WDTOVF signal 132 states*2 Internal reset signal*1 518 states Legend WT/IT : Timer mode select bit TME : Timer enable bit Notes: *1 The internal reset signal is generated only if the RSTE bit is set to 1. *2 130 states when the RSTE bit is cleared to 0. Figure 12-4 (a) WDT0 Watchdog Timer Operation TCNT value Overflow H'FF H'00 WT/IT= 1 TME= 1 Write H'00' to TCNT WOVF= 1* Occurrence of internal reset WT/IT= 1 Write H'00' TME= 1 to TCNT Time Internal reset signal 515/516 states WT/IT : Timer Mode Select bit TME : Timer Enable bit Note: * The WOVF bit is set to 1 and then cleared to 0 by an internal reset. Figure 12-4 (b) WDT1 Operation in Watchdog Timer Mode 411 12.3.2 Interval Timer Operation To use the WDT as an interval timer, clear the WT/IT bit in TCSR to 0 and set the TME bit to 1. An interval timer interrupt (WOVI) is generated each time TCNT overflows, provided that the WDT is operating as an interval timer, as shown in figure 12-5. This function can be used to generate interrupt requests at regular intervals. TCNT count H'FF Overflow Overflow Overflow Overflow H'00 WT/IT=0 TME=1 WOVI WOVI WOVI WOVI Time Legend WOVI: Interval timer interrupt request generation Figure 12-5 Interval Timer Operation 12.3.3 Timing of Setting Overflow Flag (OVF) The OVF flag is set to 1 if TCNT overflows during interval timer operation. At the same time, an interval timer interrupt (WOVI) is requested. This timing is shown in figure 12-6. With WDT1, the OVF bit of the TCSR is set to 1 and a simultaneous NMI interrupt is requested when the TCNT overflows if the NMI request has been chosen in the watchdog timer mode. 412 o TCNT H'FF H'00 Overflow signal (internal signal) OVF Figure 12-6 Timing of Setting of OVF 12.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF) In the WDT0, the WOVF flag is set to 1 if TCNT overflows during watchdog timer operation. At the same time, the WDTOVF signal goes low. If TCNT overflows while the RSTE bit in RSTCSR is set to 1, an internal reset signal is generated for the entire chip. Figure 12-7 shows the timing in this case. o TCNT Overflow signal (internal signal) WOVF H'FF H'00 WDTOVF signal Internal reset signal 132 states 518 states (WDT0) 515/516 states (WDT1) Figure 12-7 Timing of Setting of WOVF 413 12.4 Interrupts During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine. If an NMI request has been chosen in the watchdog timer mode, an NMI request is generated when a TCNT overflow occurs. 12.5 12.5.1 Usage Notes Contention between Timer Counter (TCNT) Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 12-8 shows this operation. TCNT write cycle T1 T2 o Address Internal write signal TCNT input clock TCNT N M Counter write data Figure 12-8 Contention between TCNT Write and Increment 414 12.5.2 Changing Value of PSS and CKS2 to CKS0 If bits PSS and CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before changing the value of bits PSS and CKS2 to CKS0. 12.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode If the mode is switched from watchdog timer to interval timer, or vice versa, while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before switching the mode. 12.5.4 System Reset by WDTOVF Signal If the WDTOVF output signal is input to the RES pin of the H8S/2626 Series or H8S/2623 Series, the chip will not be initialized correctly. Make sure that the WDTOVF signal is not input logically to the RES pin. To reset the entire system by means of the WDTOVF signal, use the circuit shown in figure 12-9. H8S/2626 Series or H8S/2623 Series Reset input RES Reset signal to entire system WDTOVF Figure 12-9 Circuit for System Reset by WDTOVF Signal (Example) 12.5.5 Internal Reset in Watchdog Timer Mode The H8S/2626 Series or H8S/2623 Series is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during watchdog timer operation, but TCNT and TCSR of the WDT are reset. TCNT, TCSR, and RSTCSR cannot be written to while the WDTOVF signal is low. Also note that a read of the WOVF flag is not recognized during this period. To clear the WOVF falg, therefore, read TCSR after the WDTOVF signal goes high, then write 0 to the WOVF flag. 415 12.5.6 OVF Flag Clearing in Interval Timer Mode When the OVF flag setting conflicts with the OVF flag reading in interval timer mode, writing 0 to the OVF bit may not clear the flag even though the OVF bit has been read while it is 1. If there is a possibility that the OVF flag setting and reading will conflict, such as when the OVF flag is polled with the interval timer interrupt disabled, read the OVF bit while it is 1 at least twice before writing 0 to the OVF bit to clear the flag. 416 Section 13 Serial Communication Interface (SCI) 13.1 Overview The H8S/2626 Series and H8S/2623 Series have three independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication. A function is also provided for serial communication between processors (multiprocessor communication function). 13.1.1 Features SCI features are listed below. * Choice of asynchronous or clocked synchronous serial communication mode Asynchronous mode Serial data communication executed using asynchronous system in which synchronization is achieved character by character Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA) A multiprocessor communication function is provided that enables serial data communication with a number of processors Choice of 12 serial data transfer formats Data length : 7 or 8 bits Stop bit length : 1 or 2 bits Parity : Even, odd, or none Multiprocessor bit : 1 or 0 Receive error detection : Parity, overrun, and framing errors Break detection : Break can be detected by reading the RxD pin level directly in case of a framing error Clocked Synchronous mode Serial data communication synchronized with a clock Serial data communication can be carried out with other chips that have a synchronous communication function One serial data transfer format Data length : 8 bits Receive error detection : Overrun errors detected 417 * Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data * Choice of LSB-first or MSB-first transfer Can be selected regardless of the communication mode* (except in the case of asynchronous mode 7-bit data) Note: * Descriptions in this section refer to LSB-first transfer. * On-chip baud rate generator allows any bit rate to be selected * Choice of serial clock source: internal clock from baud rate generator or external clock from SCK pin * Four interrupt sources Four interrupt sources -- transmit-data-empty, transmit-end, receive-data-full, and receive error -- that can issue requests independently The transmit-data-empty interrupt and receive data full interrupts can activate the data transfer controller (DTC) to execute data transfer * Module stop mode can be set As the initial setting, SCI operation is halted. Register access is enabled by exiting module stop mode. 418 13.1.2 Block Diagram Figure 13-1 shows a block diagram of the SCI. Bus interface Module data bus Internal data bus RDR TDR RxD RSR TSR SCMR SSR SCR SMR Transmission/ reception control BRR o Baud rate generator o/4 o/16 o/64 Clock TxD Parity generation Parity check SCK External clock TEI TXI RXI ERI Legend RSR : Receive shift register RDR : Receive data register TSR : Transmit shift register TDR : Transmit data register SMR : Serial mode register SCR : Serial control register SSR : Serial status register SCMR : Smart card mode register BRR : Bit rate register Figure 13-1 Block Diagram of SCI 419 13.1.3 Pin Configuration Table 13-1 shows the serial pins for each SCI channel. Table 13-1 SCI Pins Channel 0 Pin Name Serial clock pin 0 Receive data pin 0 Transmit data pin 0 1 Serial clock pin 1 Receive data pin 1 Transmit data pin 1 2 Serial clock pin 2 Receive data pin 2 Transmit data pin 2 Symbol* SCK0 RxD0 TxD0 SCK1 RxD1 TxD1 SCK2 RxD2 TxD2 I/O I/O Input Output I/O Input Output I/O Input Output Function SCI0 clock input/output SCI0 receive data input SCI0 transmit data output SCI1 clock input/output SCI1 receive data input SCI1 transmit data output SCI2 clock input/output SCI2 receive data input SCI2 transmit data output Note: * Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the channel designation. 420 13.1.4 Register Configuration The SCI has the internal registers shown in table 13-2. These registers are used to specify asynchronous mode or clocked synchronous mode, the data format , and the bit rate, and to control transmitter/receiver. Table 13-2 SCI Registers Channel 0 Name Serial mode register 0 Bit rate register 0 Serial control register 0 Transmit data register 0 Serial status register 0 Receive data register 0 Smart card mode register 0 1 Serial mode register 1 Bit rate register 1 Serial control register 1 Transmit data register 1 Serial status register 1 Receive data register 1 Smart card mode register 1 2 Serial mode register 2 Bit rate register 2 Serial control register 2 Transmit data register 2 Serial status register 2 Receive data register 2 Smart card mode register 2 All Module stop control register B Abbreviation SMR0 BRR0 SCR0 TDR0 SSR0 RDR0 SCMR0 SMR1 BRR1 SCR1 TDR1 SSR1 RDR1 SCMR1 SMR2 BRR2 SCR2 TDR2 SSR2 RDR2 SCMR2 MSTPCRB R/W R/W R/W R/W R/W R/(W)* R R/W R/W R/W R/W R/W R/(W)* R R/W R/W R/W R/W R/W R/(W)* R R/W R/W 2 2 2 Initial Value H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'FF Address* 1 H'FF78 H'FF79 H'FF7A H'FF7B H'FF7C H'FF7D H'FF7E H'FF80 H'FF81 H'FF82 H'FF83 H'FF84 H'FF85 H'FF86 H'FF88 H'FF89 H'FF8A H'FF8B H'FF8C H'FF8D H'FF8E H'FDE9 Notes: *1 Lower 16 bits of the address. *2 Only 0 can be written, for flag clearing. 421 13.2 13.2.1 Bit R/W Register Descriptions Receive Shift Register (RSR) : : 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 -- RSR is a register used to receive serial data. The SCI sets serial data input from the RxD pin in RSR in the order received, starting with the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly read or written to by the CPU. 13.2.2 Bit Receive Data Register (RDR) : 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R Initial value : R/W : RDR is a register that stores received serial data. When the SCI has received one byte of serial data, it transfers the received serial data from RSR to RDR where it is stored, and completes the receive operation. After this, RSR is receive-enabled. Since RSR and RDR function as a double buffer in this way, enables continuous receive operations to be performed. RDR is a read-only register, and cannot be written to by the CPU. RDR is initialized to H'00 by a reset, in standby mode, watch mode, subactive mode, subsleep mode, or module stop mode. 422 13.2.3 Bit R/W Transmit Shift Register (TSR) : : 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 -- TSR is a register used to transmit serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin starting with the LSB (bit 0). When transmission of one byte is completed, the next transmit data is transferred from TDR to TSR, and transmission started, automatically. However, data transfer from TDR to TSR is not performed if the TDRE bit in SSR is set to 1. TSR cannot be directly read or written to by the CPU. 13.2.4 Bit Transmit Data Register (TDR) : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W Initial value : R/W : TDR is an 8-bit register that stores data for serial transmission. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts serial transmission. Continuous serial transmission can be carried out by writing the next transmit data to TDR during serial transmission of the data in TSR. TDR can be read or written to by the CPU at all times. TDR is initialized to H'FF by a reset, in standby mode, watch mode, subactive mode, subsleep mode, or module stop mode. 423 13.2.5 Bit Serial Mode Register (SMR) : 7 C/A 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Initial value : R/W : SMR is an 8-bit register used to set the SCI's serial transfer format and select the baud rate generator clock source. SMR can be read or written to by the CPU at all times. SMR is initialized to H'00 by a reset and in hardware standby mode. It retains its previous state in module stop mode, software standby mode, watch mode, subactive mode, and subsleep mode. Bit 7--Communication Mode (C/A): Selects asynchronous mode or clocked synchronous mode as the SCI operating mode. Bit 7 C/A 0 1 Description Asynchronous mode Clocked synchronous mode (Initial value) Bit 6--Character Length (CHR): Selects 7 or 8 bits as the data length in asynchronous mode. In clocked synchronous mode, a fixed data length of 8 bits is used regardless of the CHR setting. Bit 6 CHR 0 1 Description 8-bit data 7-bit data* (Initial value) Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted, and it is not possible to choose between LSB-first or MSB-first transfer. 424 Bit 5--Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. In clocked synchronous mode with a multiprocessor format, parity bit addition and checking is not performed, regardless of the PE bit setting. Bit 5 PE 0 1 Description Parity bit addition and checking disabled Parity bit addition and checking enabled* (Initial value) Note:* When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/E bit. Bit 4--Parity Mode (O/E): Selects either even or odd parity for use in parity addition and checking. The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and checking, in asynchronous mode. The O/E bit setting is invalid in clocked synchronous mode, when parity addition and checking is disabled in asynchronous mode, and when a multiprocessor format is used. Bit 4 O/E 0 1 Description Even parity* 1 Odd parity* 2 (Initial value) Notes: *1 When even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. *2 When odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd. 425 Bit 3--Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode. The STOP bits setting is only valid in asynchronous mode. If clocked synchronous mode is set the STOP bit setting is invalid since stop bits are not added. Bit 3 STOP 0 1 Description 1 stop bit: In transmission, a single 1 bit (stop bit) is added to the end of a transmit character before it is sent. (Initial value) 2 stop bits: In transmission, two 1 bits (stop bits) are added to the end of a transmit character before it is sent. In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. Bit 2--Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format is selected, the PE bit and O/E bit parity settings are invalid. The MP bit setting is only valid in asynchronous mode; it is invalid in clocked synchronous mode. For details of the multiprocessor communication function, see section 13.3.3, Multiprocessor Communication Function. Bit 2 MP 0 1 Description Multiprocessor function disabled Multiprocessor format selected (Initial value) 426 Bits 1 and 0--Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the baud rate generator. The clock source can be selected from o, o/4, o/16, and o/64, according to the setting of bits CKS1 and CKS0. For the relation between the clock source, the bit rate register setting, and the baud rate, see section 13.2.8, Bit Rate Register (BRR). Bit 1 CKS1 0 Bit 0 CKS0 0 1 1 0 1 Description o clock o/4 clock o/16 clock o/64 clock (Initial value) 13.2.6 Bit Serial Control Register (SCR) : 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W Initial value : R/W : SCR is a register that performs enabling or disabling of SCI transfer operations, serial clock output in asynchronous mode, and interrupt requests, and selection of the serial clock source. SCR can be read or written to by the CPU at all times. SCR is initialized to H'00 by a reset and in hardware standby mode. It retains its previous state in module stop mode, software standby mode, watch mode, subactive mode, and subsleep mode. Bit 7--Transmit Interrupt Enable (TIE): Enables or disables transmit data empty interrupt (TXI) request generation when serial transmit data is transferred from TDR to TSR and the TDRE flag in SSR is set to 1. Bit 7 TIE 0 1 Description Transmit data empty interrupt (TXI) requests disabled Transmit data empty interrupt (TXI) requests enabled (Initial value) Note: TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then clearing it to 0, or clearing the TIE bit to 0. 427 Bit 6--Receive Interrupt Enable (RIE): Enables or disables receive data full interrupt (RXI) request and receive error interrupt (ERI) request generation when serial receive data is transferred from RSR to RDR and the RDRF flag in SSR is set to 1. Bit 6 RIE 0 1 Description Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled* (Initial value) Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled Note:* RXI and ERI interrupt request cancellation can be performed by reading 1 from the RDRF flag, or the FER, PER, or ORER flag, then clearing the flag to 0, or clearing the RIE bit to 0. Bit 5--Transmit Enable (TE): Enables or disables the start of serial transmission by the SCI. Bit 5 TE 0 1 Description Transmission disabled* 1 Transmission enabled* 2 (Initial value) Notes: *1 The TDRE flag in SSR is fixed at 1. *2 In this state, serial transmission is started when transmit data is written to TDR and the TDRE flag in SSR is cleared to 0. SMR setting must be performed to decide the transfer format before setting the TE bit to 1. Bit 4--Receive Enable (RE): Enables or disables the start of serial reception by the SCI. Bit 4 RE 0 1 Description Reception disabled* 1 Reception enabled* 2 (Initial value) Notes: *1 Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states. *2 Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in clocked synchronous mode. SMR setting must be performed to decide the transfer format before setting the RE bit to 1. 428 Bit 3--Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE bit setting is only valid in asynchronous mode when the MP bit in SMR is set to 1. The MPIE bit setting is invalid in clocked synchronous mode or when the MP bit is cleared to 0. Bit 3 MPIE 0 Description Multiprocessor interrupts disabled (normal reception performed) [Clearing conditions] * * 1 When the MPIE bit is cleared to 0 When MPB= 1 data is received (Initial value) Multiprocessor interrupts enabled* Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received. Note: * When receive data including MPB = 0 is received, receive data transfer from RSR to RDR, receive error detection, and setting of the RDRF, FER, and ORER flags in SSR , is not performed. When receive data including MPB = 1 is received, the MPB bit in SSR is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag setting is enabled. Bit 2--Transmit End Interrupt Enable (TEIE): Enables or disables transmit end interrupt (TEI) request generation when there is no valid transmit data in TDR in MSB data transmission. Bit 2 TEIE 0 1 Description Transmit end interrupt (TEI) request disabled* Transmit end interrupt (TEI) request enabled* (Initial value) Note: * TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then clearing it to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0. 429 Bits 1 and 0--Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin. The combination of the CKE1 and CKE0 bits determines whether the SCK pin functions as an I/O port, the serial clock output pin, or the serial clock input pin. The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in asynchronous mode. The CKE0 bit setting is invalid in clocked synchronous mode, and in the case of external clock operation (CKE1 = 1). Note that the SCI's operating mode must be decided using SMR before setting the CKE1 and CKE0 bits. For details of clock source selection, see table 13.9 in section 13.3, Operation. Bit 1 CKE1 0 Bit 0 CKE0 0 Description Asynchronous mode Clocked synchronous mode 1 Asynchronous mode Clocked synchronous mode 1 0 Asynchronous mode Clocked synchronous mode 1 Asynchronous mode Clocked synchronous mode Internal clock/SCK pin functions as I/O port* 1 Internal clock/SCK pin functions as serial clock output* 1 Internal clock/SCK pin functions as clock output* 2 Internal clock/SCK pin functions as serial clock output External clock/SCK pin functions as clock input* 3 External clock/SCK pin functions as serial clock input External clock/SCK pin functions as clock input* 3 External clock/SCK pin functions as serial clock input Notes: *1 Initial value *2 Outputs a clock of the same frequency as the bit rate. *3 Inputs a clock with a frequency 16 times the bit rate. 430 13.2.7 Bit Serial Status Register (SSR) : 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W Initial value : R/W : Note: * Only 0 can be written, for flag clearing. SSR is an 8-bit register containing status flags that indicate the operating status of the SCI, and multiprocessor bits. SSR can be read or written to by the CPU at all times. However, 1 cannot be written to flags TDRE, RDRF, ORER, PER, and FER. Also note that in order to clear these flags they must be read as 1 beforehand. The TEND flag and MPB flag are read-only flags and cannot be modified. SSR is initialized to H'84 by a reset, in standby mode, watch mode, subactive mode, subsleep mode, or module stop mode. Bit 7--Transmit Data Register Empty (TDRE): Indicates that data has been transferred from TDR to TSR and the next serial data can be written to TDR. Bit 7 TDRE 0 Description [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] (Initial value) * When the TE bit in SCR is 0 * When data is transferred from TDR to TSR and data can be written to TDR 1 431 Bit 6--Receive Data Register Full (RDRF): Indicates that the received data is stored in RDR. Bit 6 RDRF 0 Description [Clearing conditions] (Initial value) * When 0 is written to RDRF after reading RDRF = 1 * When the DTC is activated by an RXI interrupt and reads data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR Note: RDR and the RDRF flag are not affected and retain their previous values when an error is detected during reception or when the RE bit in SCR is cleared to 0. If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the receive data will be lost. 1 Bit 5--Overrun Error (ORER): Indicates that an overrun error occurred during reception, causing abnormal termination. Bit 5 ORER 0 Description [Clearing condition] When 0 is written to ORER after reading ORER = 1 1 [Setting condition] When the next serial reception is completed while RDRF = 1*2 Notes: *1 The ORER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. *2 The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost. Also, subsequent serial reception cannot be continued while the ORER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. (Initial value)*1 432 Bit 4--Framing Error (FER): Indicates that a framing error occurred during reception in asynchronous mode, causing abnormal termination. Bit 4 FER 0 Description [Clearing condition] When 0 is written to FER after reading FER = 1 1 [Setting condition] When the SCI checks whether the stop bit at the end of the receive data when reception ends, and the stop bit is 0 * 2 Notes: *1 The FER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. *2 In 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit is not checked. If a framing error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the FER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. (Initial value)*1 Bit 3--Parity Error (PER): Indicates that a parity error occurred during reception using parity addition in asynchronous mode, causing abnormal termination. Bit 3 PER 0 1 Description [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR* 2 (Initial value)*1 Notes: *1 The PER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. *2 If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the PER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. 433 Bit 2--Transmit End (TEND): Indicates that there is no valid data in TDR when the last bit of the transmit character is sent, and transmission has been ended. The TEND flag is read-only and cannot be modified. Bit 2 TEND 0 Description [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] (Initial value) * When the TE bit in SCR is 0 * When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character 1 Bit 1--Multiprocessor Bit (MPB): When reception is performed using multiprocessor format in asynchronous mode, MPB stores the multiprocessor bit in the receive data. MPB is a read-only bit, and cannot be modified. Bit 1 MPB 0 1 Description [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received (Initial value)* Note: * Retains its previous state when the RE bit in SCR is cleared to 0 with multiprocessor format. Bit 0--Multiprocessor Bit Transfer (MPBT): When transmission is performed using multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to the transmit data. The MPBT bit setting is invalid when multiprocessor format is not used, when not transmitting, and in clocked synchronous mode. Bit 0 MPBT 0 1 Description Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted (Initial value) 434 13.2.8 Bit Bit Rate Register (BRR) : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W Initial value : R/W : BRR is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SMR. BRR can be read or written to by the CPU at all times. BRR is initialized to H'FF by a reset and in hardware standby mode. It retains its previous state in module stop mode, software standby mode, watch mode, subactive mode, and subsleep mode. As baud rate generator control is performed independently for each channel, different values can be set for each channel. Table 13-3 shows sample BRR settings in asynchronous mode, and table 13-4 shows sample BRR settings in clocked synchronous mode. 435 Table 13-3 BRR Settings for Various Bit Rates (Asynchronous Mode) o = 4 MHz Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -- 0.00 -- o = 4.9152 MHz Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 o = 5 MHz Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 1.73 0.00 1.73 n 2 1 1 0 0 0 0 0 -- 0 -- N 70 207 103 207 103 51 25 12 -- 3 -- n 2 1 1 0 0 0 0 0 0 0 0 N 86 255 127 255 127 63 31 15 7 4 3 n 2 2 1 1 0 0 0 0 0 N 88 64 129 64 129 64 32 15 7 4 3 -1.70 0 0.00 0 o = 6 MHz Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%) o = 6.144 MHz Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 o = 7.3728 MHz Error (%) o = 8 MHz Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -- n 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 9 5 4 n N 108 79 159 79 159 79 39 19 9 5 4 n 2 2 1 1 0 0 0 0 0 -- 0 N 130 95 191 95 191 95 47 23 11 -- 5 n N 141 103 207 103 207 103 51 25 12 7 -- -0.44 2 0.16 0.16 0.16 0.16 0.16 0.16 2 1 1 0 0 0 -0.07 2 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 2 1 1 0 0 0 0 0 0 -- -2.34 0 -2.34 0 0.00 0 -2.34 0 436 o = 9.8304 MHz Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%) o = 10 MHz Error (%) o = 12 MHz Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 o = 12.288 MHz Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 2 2 1 1 0 0 0 0 0 0 0 N 174 127 255 127 255 127 63 31 15 9 7 n N 177 129 64 129 64 129 64 32 15 9 7 n N 212 155 77 155 77 155 77 38 19 11 9 n 2 2 2 1 1 0 0 0 N 217 159 79 159 79 159 79 39 19 11 9 -0.26 2 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2 2 1 1 0 0 0 0 -0.25 2 0.16 0.16 0.16 0.16 0.16 0.16 2 2 1 1 0 0 -1.36 0 1.73 0.00 1.73 0 0 0 -2.34 0 0.00 0 -1.70 0 0.00 0 -2.34 0 o = 14 MHz Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%) o = 14.7456 MHz Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 o = 16 MHz Error (%) 0.03 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.00 0.13 o = 17.2032 MHz Error (%) 0.48 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 1.20 0.00 n 2 2 2 1 1 0 0 0 0 0 -- N 248 181 90 181 90 181 90 45 22 13 -- n N 64 191 95 191 95 191 95 47 23 14 11 n 3 2 2 1 1 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 n 3 2 2 1 1 0 0 0 0 0 0 N 75 223 111 223 111 223 111 55 27 13 13 -0.17 3 0.13 0.13 0.13 0.13 0.13 0.13 2 2 1 1 0 0 -0.93 0 -0.93 0 0.00 -- 0 0 -1.70 0 0.00 0 437 o = 18 MHz Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%) o = 19.6608 MHz Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 o = 20 MHz Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 0.00 1.73 n 3 2 2 1 1 0 0 0 0 0 0 N 79 233 116 233 116 233 116 58 28 17 14 n N 86 255 127 255 127 255 127 63 31 19 15 n 3 3 2 2 1 1 0 0 0 N 88 64 129 64 129 64 129 64 32 19 15 -0.12 3 0.16 0.16 0.16 0.16 0.16 0.16 2 2 1 1 0 0 -0.69 0 1.02 0.00 0 0 -1.70 0 0.00 0 -2.34 0 438 Table 13-4 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Bit Rate (bit/s) 110 250 500 1k 2.5 k 5k 10 k 25 k 50 k 100 k 250 k 500 k 1M 2.5 M 5M n -- 2 2 1 1 0 0 0 0 0 0 0 0 o = 4 MHz N -- 249 124 249 99 199 99 39 19 9 3 1 0* 3 2 2 1 1 0 0 0 0 0 0 0 124 249 124 199 99 199 79 39 19 7 3 1 0 0* -- -- -- 1 1 0 0 0 0 0 0 -- -- -- 249 124 249 99 49 24 9 4 3 3 2 2 1 1 0 0 0 0 0 0 249 124 249 99 199 99 159 79 39 15 7 3 -- -- 2 1 1 0 0 0 0 0 0 0 0 -- -- 124 249 124 199 99 49 19 9 4 1 0* n o = 8 MHz N n o = 10 MHz N n o = 16 MHz N n o = 20 MHz N Note: As far as possible, the setting should be made so that the error is no more than 1%. Legend Blank : Cannot be set. -- : Can be set, but there will be a degree of error. * : Continuous transfer is not possible. 439 The BRR setting is found from the following formulas. Asynchronous mode: N= o 64 x 22n-1 x B x 10 6 - 1 Clocked synchronous mode: N= Where B: N: o: n: o 8x2 2n-1 xB x 10 6 - 1 Bit rate (bit/s) BRR setting for baud rate generator (0 N 255) Operating frequency (MHz) Baud rate generator input clock (n = 0 to 3) (See the table below for the relation between n and the clock.) SMR Setting n 0 1 2 3 Clock o o/4 o/16 o/64 CKS1 0 0 1 1 CKS0 0 1 0 1 The bit rate error in asynchronous mode is found from the following formula: Error (%) = { o x 106 (N + 1) x B x 64 x 22n-1 - 1} x 100 440 Table 13-5 shows the maximum bit rate for each frequency in asynchronous mode. Tables 13-6 and 13-7 show the maximum bit rates with external clock input. Table 13-5 Maximum Bit Rate for Each Frequency (Asynchronous Mode) o (MHz) 4 4.9152 5 6 6.144 7.3728 8 9.8304 10 12 12.288 14 14.7456 16 17.2032 18 19.6608 20 Maximum Bit Rate (bit/s) 125000 153600 156250 187500 192000 230400 250000 307200 312500 375000 384000 437500 460800 500000 537600 562500 614400 625000 n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 441 Table 13-6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) o (MHz) 4 4.9152 5 6 6.144 7.3728 8 9.8304 10 12 12.288 14 14.7456 16 17.2032 18 19.6608 20 External Input Clock (MHz) 1.0000 1.2288 1.2500 1.5000 1.5360 1.8432 2.0000 2.4576 2.5000 3.0000 3.0720 3.5000 3.6864 4.0000 4.3008 4.5000 4.9152 5.0000 Maximum Bit Rate (bit/s) 62500 76800 78125 93750 96000 115200 125000 153600 156250 187500 192000 218750 230400 250000 268800 281250 307200 312500 Table 13-7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) o (MHz) 4 6 8 10 12 14 16 18 20 External Input Clock (MHz) 0.6667 1.0000 1.3333 1.6667 2.0000 2.3333 2.6667 3.0000 3.3333 Maximum Bit Rate (bit/s) 666666.7 1000000.0 1333333.3 1666666.7 2000000.0 2333333.3 2666666.7 3000000.0 3333333.3 442 13.2.9 Bit Smart Card Mode Register (SCMR) : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 SDIR 0 R/W 2 SINV 0 R/W 1 -- 1 -- 0 SMIF 0 R/W Initial value : R/W : SCMR selects LSB-first or MSB-first by means of bit SDIR. Except in the case of asynchronous mode 7-bit data, LSB-first or MSB-first can be selected regardless of the serial communication mode. The descriptions in this chapter refer to LSB-first transfer. For details of the other bits in SCMR, see 14.2.1, Smart Card Mode Register (SCMR). SCMR is initialized to H'F2 by a reset and in hardware standby mode. It retains its previous state in module stop mode, software standby mode, watch mode, subactive mode, and subsleep mode. Bits 7 to 4--Reserved: These bits are always read as 1 and cannot be modified. Bit 3--Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion format. This bit is valid when 8-bit data is used as the transmit/receive format. Bit 3 SDIR 0 Description TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first 1 TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first (Initial value) 443 Bit 2--Smart Card Data Invert (SINV): Specifies inversion of the data logic level. The SINV bit does not affect the logic level of the parity bit(s): parity bit inversion requires inversion of the O/E bit in SMR. Bit 2 SINV 0 1 Description TDR contents are transmitted without modification Receive data is stored in RDR without modification TDR contents are inverted before being transmitted Receive data is stored in RDR in inverted form (Initial value) Bit 1--Reserved: This bit is always read as 1 and cannot be modified. Bit 0--Smart Card Interface Mode Select (SMIF): When the smart card interface operates as a normal SCI, 0 should be written in this bit. Bit 0 SMIF 0 1 Description Operates as normal SCI (smart card interface function disabled) Smart card interface function enabled (Initial value) 13.2.10 Module Stop Control Register B (MSTPCRB) MSTPCRB Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0 Initial value : R/W : MSTPCRB is 8-bit readable/writable registers that perform module stop mode control. When one of bits MSTPB7 to MSTPB5 is set to 1, SCI0, SCI1, or SCI2, respectively, stops operation at the end of the bus cycle, and enters module stop mode. For details, see sections 21A.5, 21B.5, Module Stop Mode. MSTPCRB is initialized to H'FF by a reset and in hardware standby mode. They are not initialized in software standby mode. 444 Bit 7--Module Stop (MSTPB7): Specifies the SCI0 module stop mode. Bit 7 MSTPB7 0 1 Description SCI0 module stop mode is cleared SCI0 module stop mode is set (Initial value) Bit 6--Module Stop (MSTPB6): Specifies the SCI1 module stop mode. Bit 6 MSTPB6 0 1 Description SCI1 module stop mode is cleared SCI1 module stop mode is set (Initial value) Bit 5--Module Stop (MSTPB5): Specifies the SCI2 module stop mode. Bit 5 MSTPB5 0 1 Description SCI2 module stop mode is cleared SCI2 module stop mode is set (Initial value) 445 13.3 13.3.1 Operation Overview The SCI can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and clocked synchronous mode in which synchronization is achieved with clock pulses. Selection of asynchronous or clocked synchronous mode and the transmission format is made using SMR as shown in table 13-8. The SCI clock is determined by a combination of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR, as shown in table 13-9. Asynchronous Mode * Data length: Choice of 7 or 8 bits * Choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer format and character length) * Detection of framing, parity, and overrun errors, and breaks, during reception * Choice of internal or external clock as SCI clock source When internal clock is selected: The SCI operates on the baud rate generator clock and a clock with the same frequency as the bit rate can be output When external clock is selected: A clock with a frequency of 16 times the bit rate must be input (the on-chip baud rate generator is not used) Clocked Synchronous Mode * Transfer format: Fixed 8-bit data * Detection of overrun errors during reception * Choice of internal or external clock as SCI clock source When internal clock is selected: The SCI operates on the baud rate generator clock and a serial clock is output off-chip When external clock is selected: The on-chip baud rate generator is not used, and the SCI operates on the input serial clock 446 Table 13-8 SMR Settings and Serial Transfer Format Selection SMR Settings Bit 7 C/A 0 Bit 6 CHR 0 Bit 2 MP 0 Bit 5 PE 0 Bit 3 STOP 0 1 1 0 1 1 0 0 1 1 0 1 0 1 -- -- 1 -- -- 1 -- -- -- 0 1 0 1 -- Clocked 8-bit data synchronous mode No Asynchronous mode (multiprocessor format) 8-bit data Yes No Yes 7-bit data No Mode Asynchronous mode Yes SCI Transfer Format Multi Processor Bit No Data Length 8-bit data Parity Bit No Stop Bit Length 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 7-bit data 1 bit 2 bits None Table 13-9 SMR and SCR Settings and SCI Clock Source Selection SMR Bit 7 C/A 0 SCR Setting Bit 1 CKE1 0 Bit 0 CKE0 0 1 1 0 1 1 0 0 1 1 0 1 Clocked synchronous mode Internal Mode Asynchronous mode Clock Source Internal SCI Transmit/Receive Clock SCK Pin Function SCI does not use SCK pin Outputs clock with same frequency as bit rate External Inputs clock with frequency of 16 times the bit rate Outputs serial clock External Inputs serial clock 447 13.3.2 Operation in Asynchronous Mode In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and stop bits indicating the end of communication. Serial communication is thus carried out with synchronization established on a character-by-character basis. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 13-2 shows the general format for asynchronous serial communication. In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCI monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. One serial communication character consists of a start bit (low level), followed by data (in LSBfirst order), a parity bit (high or low level), and finally stop bits (high level). In asynchronous mode, the SCI performs synchronization at the falling edge of the start bit in reception. The SCI samples the data on the 8th pulse of a clock with a frequency of 16 times the length of one bit, so that the transfer data is latched at the center of each bit. Idle state (mark state) 1 Serial data 0 Start bit 1 bit LSB D0 D1 D2 D3 D4 D5 D6 MSB D7 0/1 Parity bit 1 bit, or none 1 1 1 Stop bit Transmit/receive data 7 or 8 bits 1 or 2 bits One unit of transfer data (character or frame) Figure 13-2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) 448 Data Transfer Format: Table 13-10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. Table 13-10 Serial Transfer Formats (Asynchronous Mode) SMR Settings CHR 0 0 0 0 1 1 1 1 0 0 1 1 PE 0 0 1 1 0 0 1 1 -- -- -- -- MP 0 0 0 0 0 0 0 0 1 1 1 1 STOP 0 1 0 1 0 1 0 1 0 1 0 1 1 S Serial Transfer Format and Frame Length 2 3 4 5 6 7 8 9 10 STOP 11 12 8-bit data 8-bit data 8-bit data 8-bit data 7-bit data 7-bit data 7-bit data 7-bit data 8-bit data 8-bit data 7-bit data 7-bit data STOP S STOP STOP S P STOP S P STOP STOP S S STOP STOP S P STOP S P STOP STOP S MPB STOP S MPB STOP STOP S MPB STOP S MPB STOP STOP Legend S : Start bit STOP : Stop bit P : Parity bit MPB : Multiprocessor bit 449 Clock: Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI's serial clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table 13-9. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 13-3. 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 frame Figure 13-3 Relation between Output Clock and Transfer Data Phase (Asynchronous Mode) Data Transfer Operations: * SCI initialization (asynchronous mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. When an external clock is used the clock should not be stopped during operation, including initialization, since operation is uncertain. 450 Figure 13-4 shows a sample SCI initialization flowchart. Start initialization Clear TE and RE bits in SCR to 0 [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. When the clock is selected in asynchronous mode, it is output immediately after SCR settings are made. [2] Set the data transfer format in SMR and SCMR. [3] Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. [4] Set CKE1 and CKE0 bits in SCR (TE, RE bits 0) [1] Set data transfer format in SMR and SCMR Set value in BRR Wait [2] [3] No 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits Figure 13-4 Sample SCI Initialization Flowchart 451 * Serial data transmission (asynchronous mode) Figure 13-5 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. Initialization Start transmission [1] Read TDRE flag in SSR [2] [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request, and date is written to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set DDR for the port corresponding to the TxD pin to 1, clear DR to 0, then clear the TE bit in SCR to 0. No TDRE=1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? Yes [3] Read TEND flag in SSR No TEND= 1 Yes No Break output? Yes Clear DR to 0 and set DDR to 1 [4] Clear TE bit in SCR to 0 Figure 13-5 Sample Serial Transmission Flowchart 452 In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. The serial transmit data is sent from the TxD pin in the following order. [a] Start bit: One 0-bit is output. [b] Transmit data: 8-bit or 7-bit data is output in LSB-first order. [c] Parity bit or multiprocessor bit: One parity bit (even or odd parity), or one multiprocessor bit is output. A format in which neither a parity bit nor a multiprocessor bit is output can also be selected. [d] Stop bit(s): One or two 1-bits (stop bits) are output. [e] Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. [3] The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is cleared to 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the "mark state" is entered in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. 453 Figure 13-6 shows an example of the operation for transmission in asynchronous mode. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1 1 1 Idle state (mark state) TDRE TEND TXI interrupt Data written to TDR and request generated TDRE flag cleared to 0 in TXI interrupt service routine TXI interrupt request generated TEI interrupt request generated 1 frame Figure 13-6 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) 454 * Serial data reception (asynchronous mode) Figure 13-7 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. Initialization Start reception [1] [2] [3] Receive error processing and break detection: Read ORER, PER, and If a receive error occurs, read the [2] FER flags in SSR ORER, PER, and FER flags in SSR to identify the error. After performing the appropriate error Yes processing, ensure that the PERFERORER= 1 ORER, PER, and FER flags are [3] all cleared to 0. Reception cannot No Error processing be resumed if any of these flags (Continued on next page) are set to 1. In the case of a framing error, a break can be detected by reading the value of [4] Read RDRF flag in SSR the input port corresponding to the RxD pin. No RDRF= 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 [4] SCI status check and receive data read : Read SSR and check that RDRF = 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] No All data received? Yes Clear RE bit in SCR to 0 [5] Serial reception continuation procedure: To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag, read RDR, and clear the RDRF flag to 0. The RDRF flag is cleared automatically when DTC is activated by an RXI interrupt and the RDR value is read. Figure 13-7 Sample Serial Reception Data Flowchart 455 [3] Error processing No ORER= 1 Yes Overrun error processing No FER= 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0 No PER= 1 Yes Parity error processing Clear ORER, PER, and FER flags in SSR to 0 Figure 13-7 Sample Serial Reception Data Flowchart (cont) 456 In serial reception, the SCI operates as described below. [1] The SCI monitors the transmission line, and if a 0 stop bit is detected, performs internal synchronization and starts reception. [2] The received data is stored in RSR in LSB-to-MSB order. [3] The parity bit and stop bit are received. After receiving these bits, the SCI carries out the following checks. [a] Parity check: The SCI checks whether the number of 1 bits in the receive data agrees with the parity (even or odd) set in the O/E bit in SMR. [b] Stop bit check: The SCI checks whether the stop bit is 1. If there are two stop bits, only the first is checked. [c] Status check: The SCI checks whether the RDRF flag is 0, indicating that the receive data can be transferred from RSR to RDR. If all the above checks are passed, the RDRF flag is set to 1, and the receive data is stored in RDR. If a receive error* is detected in the error check, the operation is as shown in table 13-11. Note: * Subsequent receive operations cannot be performed when a receive error has occurred. Also note that the RDRF flag is not set to 1 in reception, and so the error flags must be cleared to 0. [4] If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive data full interrupt (RXI) request is generated. Also, if the RIE bit in SCR is set to 1 when the ORER, PER, or FER flag changes to 1, a receive error interrupt (ERI) request is generated. 457 Table 13-11 Receive Errors and Conditions for Occurrence Receive Error Overrun error Abbreviation ORER Occurrence Condition Data Transfer When the next data reception is Receive data is not completed while the RDRF flag transferred from RSR to RDR. in SSR is set to 1 When the stop bit is 0 Receive data is transferred from RSR to RDR. Framing error Parity error FER PER When the received data differs Receive data is transferred from the parity (even or odd) set from RSR to RDR. in SMR Figure 13-8 shows an example of the operation for reception in asynchronous mode. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 0 1 1 Idle state (mark state) RDRF FER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine ERI interrupt request generated by framing error 1 frame Figure 13-8 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit) 458 13.3.3 Multiprocessor Communication Function The multiprocessor communication function performs serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. Use of this function enables data transfer to be performed among a number of processors sharing transmission lines. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles: an ID transmission cycle which specifies the receiving station , and a data transmission cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. The transmitting station first sends the ID of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. The receiving station skips the data until data with a 1 multiprocessor bit is sent. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip the data until data with a 1 multiprocessor bit is again received. In this way, data communication is carried out among a number of processors. Figure 13-9 shows an example of inter-processor communication using the multiprocessor format. Data Transfer Format: There are four data transfer formats. When the multiprocessor format is specified, the parity bit specification is invalid. For details, see table 13-10. Clock: See the section on asynchronous mode. 459 Transmitting station Serial transmission line Receiving station A (ID= 01) Serial data Receiving station B (ID= 02) Receiving station C (ID= 03) Receiving station D (ID= 04) H'01 (MPB= 1) ID transmission cycle= receiving station specification H'AA (MPB= 0) Data transmission cycle= Data transmission to receiving station specified by ID Legend MPB: Multiprocessor bit Figure 13-9 Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) Data Transfer Operations: * Multiprocessor serial data transmission Figure 13-10 shows a sample flowchart for multiprocessor serial data transmission. The following procedure should be used for multiprocessor serial data transmission. 460 Initialization Start transmission [1] [1] SCI initialization: Read TDRE flag in SSR [2] The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. Set the MPBT bit in SSR to 0 or 1. Finally, clear the TDRE flag to 0. No TDRE= 1 Yes Write transmit data to TDR and set MPBT bit in SSR Clear TDRE flag to 0 No All data transmitted? Yes Read TEND flag in SSR No TEND= 1 Yes No Break output? Yes [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is [3] possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request, and data is written to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set the port DDR to [4] 1, clear DR to 0, then clear the TE bit in SCR to 0. Clear DR to 0 and set DDR to 1 Clear TE bit in SCR to 0 Figure 13-10 Sample Multiprocessor Serial Transmission Flowchart 461 In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. The serial transmit data is sent from the TxD pin in the following order. [a] Start bit: One 0-bit is output. [b] Transmit data: 8-bit or 7-bit data is output in LSB-first order. [c] Multiprocessor bit One multiprocessor bit (MPBT value) is output. [d] Stop bit(s): One or two 1-bits (stop bits) are output. [e] Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. [3] The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the mark state is entered in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at this time, a transmission end interrupt (TEI) request is generated. 462 Figure 13-11 shows an example of SCI operation for transmission using the multiprocessor format. Multiprocessor Stop bit bit D7 0/1 1 1 Start bit 0 D0 D1 Data Start bit 0 D0 D1 Data D7 Multiproces- Stop 1 sor bit bit 0/1 1 Idle state (mark state) TDRE TEND TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt service routine TXI interrupt request generated TEI interrupt request generated 1 frame Figure 13-11 Example of SCI Operation in Transmission (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) * Multiprocessor serial data reception Figure 13-12 shows a sample flowchart for multiprocessor serial reception. The following procedure should be used for multiprocessor serial data reception. 463 Initialization Start reception [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] ID reception cycle: Set the MPIE bit in SCR to 1. [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station's ID. If the data is not this station's ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station's ID, clear the RDRF flag to 0. [4] SCI status check and data reception: Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. [5] Receive error processing and break detection: If a receive error occurs, read the ORER and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the ORER and FER flags are all cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin value. Read MPIE bit in SCR Read ORER and FER flags in SSR [2] Yes FERORER= 1 No Read RDRF flag in SSR No RDRF= 1 Yes Read receive data in RDR No This station's ID? Yes Read ORER and FER flags in SSR Yes FERORER= 1 No Read RDRF flag in SSR [4] No RDRF= 1 Yes Read receive data in RDR No All data received? Yes Clear RE bit in SCR to 0 [5] Error processing (Continued on next page) Figure 13-12 Sample Multiprocessor Serial Reception Flowchart 464 [5] Error processing No ORER= 1 Yes Overrun error processing No FER= 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 Figure 13-12 Sample Multiprocessor Serial Reception Flowchart (cont) 465 Figure 13-13 shows an example of SCI operation for multiprocessor format reception. Start bit 0 D0 D1 Data (ID1) MPB D7 1 Stop bit 1 Start bit 0 D0 D1 Data (Data1) MPB D7 0 Stop bit 1 1 1 Idle state (mark state) MPIE RDRF RDR value MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine ID1 If not this station's ID, RXI interrupt request is MPIE bit is set to 1 not generated, and RDR again retains its state (a) Data does not match station's ID 1 Start bit Data (ID2) MPB D0 D1 D7 1 Stop bit 1 Start bit 0 D0 Data (Data2) MPB D1 D7 0 Stop bit 1 0 1 Idle state (mark state) MPIE RDRF RDR value ID1 MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine ID2 Matches this station's ID, so reception continues, and data is received in RXI interrupt service routine Data2 MPIE bit set to 1 again (b) Data matches station's ID Figure 13-13 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) 466 13.3.4 Operation in Clocked Synchronous Mode In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 13-14 shows the general format for clocked synchronous serial communication. One unit of transfer data (character or frame) * * Serial clock LSB MSB Serial data Don't care Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Don't care Note: * High except in continuous transfer Figure 13-14 Data Format in Synchronous Communication In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. Data confirmation is guaranteed at the rising edge of the serial clock. In clocked serial communication, one character consists of data output starting with the LSB and ending with the MSB. After the MSB is output, the transmission line holds the MSB state. In clocked synchronous mode, the SCI receives data in synchronization with the rising edge of the serial clock. Data Transfer Format: A fixed 8-bit data format is used. No parity or multiprocessor bits are added. Clock: Either an internal clock generated by the on-chip baud rate generator or an external serial clock input at the SCK pin can be selected, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table 13-9. When the SCI is operated on an internal clock, the serial clock is output from the SCK pin. 467 Eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. When only receive operations are performed, however, the serial clock is output until an overrun error occurs or the RE bit is cleared to 0. If you want to perform receive operations in units of one character, you should select an external clock as the clock source. Data Transfer Operations: * SCI initialization (clocked synchronous mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. Figure 13-15 shows a sample SCI initialization flowchart. Start initialization [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, TE and RE, to 0. [2] Set the data transfer format in SMR and SCMR. Clear TE and RE bits in SCR to 0 Set CKE1 and CKE0 bits in SCR (TE, RE bits 0) Set data transfer format in SMR and SCMR Set value in BRR Wait [1] [3] Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. [2] [3] No 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits [4] Note: In simultaneous transmit and receive operations, the TE and RE bits should both be cleared to 0 or set to 1 simultaneously. Figure 13-15 Sample SCI Initialization Flowchart 468 * Serial data transmission (clocked synchronous mode) Figure 13-16 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. Initialization Start transmission [1] [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request and data is written to TDR. Read TDRE flag in SSR [2] No TDRE= 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? Yes [3] Read TEND flag in SSR No TEND= 1 Yes Clear TE bit in SCR to 0 Figure 13-16 Sample Serial Transmission Flowchart 469 In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. When clock output mode has been set, the SCI outputs 8 serial clock pulses. When use of an external clock has been specified, data is output synchronized with the input clock. The serial transmit data is sent from the TxD pin starting with the LSB (bit 0) and ending with the MSB (bit 7). [3] The SCI checks the TDRE flag at the timing for sending the MSB (bit 7). If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the MSB (bit 7) is sent, and the TxD pin maintains its state. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. [4] After completion of serial transmission, the SCK pin is fixed high. Figure 13-17 shows an example of SCI operation in transmission. Transfer direction Serial clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt request generated Data written to TDR TXI interrupt and TDRE flag request generated cleared to 0 in TXI interrupt service routine 1 frame TEI interrupt request generated Figure 13-17 Example of SCI Operation in Transmission 470 * Serial data reception (clocked synchronous mode) Figure 13-18 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. When changing the operating mode from asynchronous to clocked synchronous, be sure to check that the ORER, PER, and FER flags are all cleared to 0. The RDRF flag will not be set if the FER or PER flag is set to 1, and neither transmit nor receive operations will be possible. 471 Initialization Start reception [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. Read ORER flag in SSR Yes ORER= 1 No [2] [3] Error processing (Continued below) [2] [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR , and after performing the appropriate error processing, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1. [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. The RDRF flag is cleared automatically when the DTC is activated by a receive data full interrupt (RXI) request and the RDR value is read. Read RDRF flag in SSR [4] No RDRF= 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 Error processing Overrun error processing Clear ORER flag in SSR to 0 Figure 13-18 Sample Serial Reception Flowchart 472 In serial reception, the SCI operates as described below. [1] The SCI performs internal initialization in synchronization with serial clock input or output. [2] The received data is stored in RSR in LSB-to-MSB order. After reception, the SCI checks whether the RDRF flag is 0 and the receive data can be transferred from RSR to RDR. If this check is passed, the RDRF flag is set to 1, and the receive data is stored in RDR. If a receive error is detected in the error check, the operation is as shown in table 13-11. Neither transmit nor receive operations can be performed subsequently when a receive error has been found in the error check. [3] If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive data full interrupt (RXI) request is generated. Also, if the RIE bit in SCR is set to 1 when the ORER flag changes to 1, a receive error interrupt (ERI) request is generated. Figure 13-19 shows an example of SCI operation in reception. Serial clock Serial data RDRF ORER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine 1 frame RXI interrupt request generated ERI interrupt request generated by overrun error Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 Figure 13-19 Example of SCI Operation in Reception * Simultaneous serial data transmission and reception (clocked synchronous mode) Figure 13-20 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations. 473 Initialization Start transmission/reception [1] [1] SCI initialization: The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. Read TDRE flag in SSR No TDRE= 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 [2] [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. [3] Receive error processing: Read ORER flag in SSR Yes [3] Error processing ORER= 1 No If a receive error occurs, read the ORER flag in SSR , and after performing the appropriate error processing, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to 1. [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. Read RDRF flag in SSR No RDRF= 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 [4] [5] Serial transmission/reception continuation procedure: To continue serial transmission/ reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible. Then write data to TDR and clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request and data is written to TDR. Also, the RDRF flag is cleared automatically when the DTC is activated by a receive data full interrupt (RXI) request and the RDR value is read. No All data received? Yes [5] Clear TE and RE bits in SCR to 0 Figure 13-20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations 474 13.4 SCI Interrupts The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt (ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI) request. Table 13-12 shows the interrupt sources and their relative priorities. Individual interrupt sources can be enabled or disabled with the TIE, RIE, and TEIE bits in the SCR. Each kind of interrupt request is sent to the interrupt controller independently. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DTC to perform data transfer. The TDRE flag is cleared to 0 automatically when data transfer is performed by the DTC. The DTC cannot be activated by a TEI interrupt request. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER, PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt can activate the DTC to perform data transfer. The RDRF flag is cleared to 0 automatically when data transfer is performed by the DTC. The DTC cannot be activated by an ERI interrupt request. 475 Table 13-12 SCI Interrupt Sources Channel 0 Interrupt Source ERI RXI TXI TEI 1 ERI RXI TXI TEI 2 ERI RXI TXI TEI Description Interrupt due to receive error (ORER, FER, or PER) Interrupt due to receive data full state (RDRF) Interrupt due to transmit data empty state (TDRE) Interrupt due to transmission end (TEND) Interrupt due to receive error (ORER, FER, or PER) Interrupt due to receive data full state (RDRF) Interrupt due to transmit data empty state (TDRE) Interrupt due to transmission end (TEND) Interrupt due to receive error (ORER, FER, or PER) Interrupt due to receive data full state (RDRF) Interrupt due to transmit data empty state (TDRE) Interrupt due to transmission end (TEND) DTC Activation Not possible Possible Possible Not possible Not possible Possible Possible Not possible Not possible Possible Possible Not possible Low Priority* High Note: * This table shows the initial state immediately after a reset. Relative priorities among channels can be changed by means of the interrupt controller. A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. The TEND flag is cleared at the same time as the TDRE flag. Consequently, if a TEI interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt may have priority for acceptance, with the result that the TDRE and TEND flags are cleared. Note that the TEI interrupt will not be accepted in this case. 476 13.5 Usage Notes The following points should be noted when using the SCI. Relation between Writes to TDR and the TDRE Flag The TDRE flag in SSR is a status flag that indicates that transmit data has been transferred from TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1. Data can be written to TDR regardless of the state of the TDRE flag. However, if new data is written to TDR when the TDRE flag is cleared to 0, the data stored in TDR will be lost since it has not yet been transferred to TSR. It is therefore essential to check that the TDRE flag is set to 1 before writing transmit data to TDR. Operation when Multiple Receive Errors Occur Simultaneously If a number of receive errors occur at the same time, the state of the status flags in SSR is as shown in table 13-13. If there is an overrun error, data is not transferred from RSR to RDR, and the receive data is lost. Table 13-13 State of SSR Status Flags and Transfer of Receive Data SSR Status Flags RDRF 1 0 0 1 1 0 1 Notes: ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 X X X Receive Data Transfer RSR to RDR X Receive Error Status Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error : Receive data is transferred from RSR to RDR. X: Receive data is not transferred from RSR to RDR. 477 Break Detection and Processing (Asynchronous Mode Only): When framing error (FER) detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the parity error flag (PER) may also be set. Note that, since the SCI continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. Sending a Break (Asynchronous Mode Only): The TxD pin has a dual function as an I/O port whose direction (input or output) is determined by DR and DDR. This can be used to send a break. Between serial transmission initialization and setting of the TE bit to 1, the mark state is replaced by the value of DR (the pin does not function as the TxD pin until the TE bit is set to 1). Consequently, DDR and DR for the port corresponding to the TxD pin are first set to 1. To send a break during serial transmission, first clear DR to 0, then clear the TE bit to 0. When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin. Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only): Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0. Receive Data Sampling Timing and Reception Margin in Asynchronous Mode: In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the transfer rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the basic clock. This is illustrated in figure 13-21. 478 16 clocks 8 clocks 0 Internal basic clock 7 15 0 7 15 0 Receive data (RxD) Synchronization sampling timing Start bit D0 D1 Data sampling timing Figure 13-21 Receive Data Sampling Timing in Asynchronous Mode Thus the reception margin in asynchronous mode is given by formula (1) below. M = | (0.5 - 1 2N ) - (L - 0.5) F - | D - 0.5 | N (1 + F) | x 100% ... Formula (1) Where M N D L F : Reception margin (%) : Ratio of bit rate to clock (N = 16) : Clock duty (D = 0 to 1.0) : Frame length (L = 9 to 12) : Absolute value of clock rate deviation Assuming values of F = 0 and D = 0.5 in formula (1), a reception margin of 46.875% is given by formula (2) below. When D = 0.5 and F = 0, M = (0.5 - = 46.875% 1 2 x 16 ) x 100% ... Formula (2) However, this is only the computed value, and a margin of 20% to 30% should be allowed in system design. 479 Restrictions on Use of DTC * When an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 o clock cycles after TDR is updated by the DTC. Misoperation may occur if the transmit clock is input within 4 o clocks after TDR is updated. (Figure 13-22) * When RDR is read by the DTC, be sure to set the activation source to the relevant SCI reception end interrupt (RXI). SCK t TDRE LSB Serial data D0 D1 D2 D3 D4 D5 D6 D7 Note: When operating on an external clock, set t >4 clocks. Figure 13-22 Example of Clocked Synchronous Transmission by DTC Operation in Case of Mode Transition * Transmission Operation should be stopped (by clearing TE, TIE, and TEIE to 0) before making a module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode transition. TSR, TDR, and SSR are reset. The output pin states in module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode depend on the port settings, and becomes high-level output after the relevant mode is cleared. If a transition is made during transmission, the data being transmitted will be undefined. When transmitting without changing the transmit mode after the relevant mode is cleared, transmission can be started by setting TE to 1 again, and performing the following sequence: SSR read -> TDR write -> TDRE clearance. To transmit with a different transmit mode after clearing the relevant mode, the procedure must be started again from initialization. Figure 13-23 shows a sample flowchart for mode transition during transmission. Port pin states are shown in figures 13-24 and 13-25. Operation should also be stopped (by clearing TE, TIE, and TEIE to 0) before making a transition from transmission by DTC transfer to module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode transition. To perform transmission with the DTC after the relevant mode is cleared, setting TE and TIE to 1 will set the TXI flag and start DTC transmission. 480 * Reception Receive operation should be stopped (by clearing RE to 0) before making a module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode transition. RSR, RDR, and SSR are reset. If a transition is made without stopping operation, the data being received will be invalid. To continue receiving without changing the reception mode after the relevant mode is cleared, set RE to 1 before starting reception. To receive with a different receive mode, the procedure must be started again from initialization. Figure 13-26 shows a sample flowchart for mode transition during reception. All data transmitted? Yes Read TEND flag in SSR No [1] TEND = 1 Yes TE = 0 [2] No [1] Data being transmitted is interrupted. After exiting software standby mode, etc., normal CPU transmission is possible by setting TE to 1, reading SSR, writing TDR, and clearing TDRE to 0, but note that if the DTC has been activated, the remaining data in DTCRAM will be transmitted when TE and TIE are set to 1. [2] If TIE and TEIE are set to 1, clear them to 0 in the same way. [3] Includes module stop mode, watch mode, subactive mode, and subsleep mode. Transition to software standby mode, etc. Exit from software standby mode, etc. Change operating mode? Yes Initialization [3] No TE = 1 Figure 13-23 Sample Flowchart for Mode Transition during Transmission 481 Start of transmission End of transmission Transition to software standby Exit from software standby TE bit SCK output pin Port input/output TxD output pin Port input/output Port High output Start SCI TxD output Stop Port input/output Port High output SCI TxD output Figure 13-24 Asynchronous Transmission Using Internal Clock Transition to software standby Exit from software standby Start of transmission End of transmission TE bit SCK output pin Port input/output TxD output pin Port input/output Port Marking output SCI TxD output Last TxD bit held Port input/output Port High output* SCI TxD output Note: * Initialized by software standby. Figure 13-25 Synchronous Transmission Using Internal Clock 482 RDRF = 1 Yes Read receive data in RDR RE = 0 Transition to software standby mode, etc. Exit from software standby mode, etc. Change operating mode? Yes Initialization [2] [2] Includes module stop mode, watch mode, subactive mode, and subsleep mode. No RE = 1 Figure 13-26 Sample Flowchart for Mode Transition during Reception 483 Switching from SCK Pin Function to Port Pin Function: * Problem in Operation: When switching the SCK pin function to the output port function (highlevel output) by making the following settings while DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1 (synchronous mode), low-level output occurs for one half-cycle. 1. End of serial data transmission 2. TE bit = 0 3. C/A bit = 0 ... switchover to port output 4. Occurrence of low-level output (see figure 13-27) Half-cycle low-level output SCK/port 1. End of transmission Data TE C/A CKE1 CKE0 Bit 6 Bit 7 2. TE = 0 4. Low-level output 3. C/A = 0 Figure 13-27 Operation when Switching from SCK Pin Function to Port Pin Function 484 * Sample Procedure for Avoiding Low-Level Output: As this sample procedure temporarily places the SCK pin in the input state, the SCK/port pin should be pulled up beforehand with an external circuit. With DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1, make the following settings in the order shown. 1. End of serial data transmission 2. TE bit = 0 3. CKE1 bit = 1 4. C/A bit = 0 ... switchover to port output 5. CKE1 bit = 0 High-level output SCK/port 1. End of transmission Data TE C/A 3. CKE1 = 1 CKE1 CKE0 5. CKE1 = 0 Bit 6 Bit 7 2. TE = 0 4. C/A = 0 Figure 13-28 Operation when Switching from SCK Pin Function to Port Pin Function (Example of Preventing Low-Level Output) 485 486 Section 14 Smart Card Interface 14.1 Overview The SCI supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extension function. Switching between the normal serial communication interface and the Smart Card interface is carried out by means of a register setting. 14.1.1 Features Features of the Smart Card interface supported by the H8S/2626 Series and H8S/2623 Series are as follows. * Asynchronous mode Data length: 8 bits Parity bit generation and checking Transmission of error signal (parity error) in receive mode Error signal detection and automatic data retransmission in transmit mode Direct convention and inverse convention both supported * On-chip baud rate generator allows any bit rate to be selected * Three interrupt sources Three interrupt sources (transmit data empty, receive data full, and transmit/receive error) that can issue requests independently The transmit data empty interrupt and receive data full interrupt can activate the data transfer controller (DTC) to execute data transfer 487 14.1.2 Block Diagram Figure 14-1 shows a block diagram of the Smart Card interface. Bus interface Module data bus Internal data bus RDR TDR RxD RSR TSR SCMR SSR SCR SMR Transmission/ reception control BRR o Baud rate generator o/4 o/16 o/64 Clock TxD Parity generation Parity check SCK TXI RXI ERI Legend SCMR : Smart Card mode register RSR : Receive shift register RDR : Receive data register TSR : Transmit shift register TDR : Transmit data register SMR : Serial mode register SCR : Serial control register SSR : Serial status register BRR : Bit rate register Figure 14-1 Block Diagram of Smart Card Interface 488 14.1.3 Pin Configuration Table 14-1 shows the Smart Card interface pin configuration. Table 14-1 Smart Card Interface Pins Channel 0 Pin Name Serial clock pin 0 Receive data pin 0 Transmit data pin 0 1 Serial clock pin 1 Receive data pin 1 Transmit data pin 1 2 Serial clock pin 2 Receive data pin 2 Transmit data pin 2 Symbol SCK0 RxD0 TxD0 SCK1 RxD1 TxD1 SCK2 RxD2 TxD2 I/O I/O Input Output I/O Input Output I/O Input Output Function SCI0 clock input/output SCI0 receive data input SCI0 transmit data output SCI1 clock input/output SCI1 receive data input SCI1 transmit data output SCI2 clock input/output SCI2 receive data input SCI2 transmit data output 489 14.1.4 Register Configuration Table 14-2 shows the registers used by the Smart Card interface. Details of SMR, BRR, SCR, TDR, RDR, and MSTPCR are the same as for the normal SCI function: see the register descriptions in section 13, Serial Communication Interface (SCI). Table 14-2 Smart Card Interface Registers Channel 0 Name Serial mode register 0 Bit rate register 0 Serial control register 0 Transmit data register 0 Serial status register 0 Receive data register 0 Smart card mode register 0 1 Serial mode register 1 Bit rate register 1 Serial control register 1 Transmit data register 1 Serial status register 1 Receive data register 1 Smart card mode register 1 2 Serial mode register 2 Bit rate register 2 Serial control register 2 Transmit data register 2 Serial status register 2 Receive data register 2 Smart card mode register 2 All Module stop control register B Abbreviation SMR0 BRR0 SCR0 TDR0 SSR0 RDR0 SCMR0 SMR1 BRR1 SCR1 TDR1 SSR1 RDR1 SCMR1 SMR2 BRR2 SCR2 TDR2 SSR2 RDR2 SCMR2 MSTPCRB R/W R/W R/W R/W R/W R/(W)* R R/W R/W R/W R/W R/W R/(W)* R R/W R/W R/W R/W R/W R/(W)* R R/W R/W 2 2 2 Initial Value H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'FF Address* 1 H'FF78 H'FF79 H'FF7A H'FF7B H'FF7C H'FF7D H'FF7E H'FF80 H'FF81 H'FF82 H'FF83 H'FF84 H'FF85 H'FF86 H'FF88 H'FF89 H'FF8A H'FF8B H'FF8C H'FF8D H'FF8E H'FDE9 Notes: *1 Lower 16 bits of the address. *2 Only 0 can be written, for flag clearing. 490 14.2 Register Descriptions Registers added with the Smart Card interface and bits for which the function changes are described here. 14.2.1 Bit Smart Card Mode Register (SCMR) : 7 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 SDIR 0 R/W 2 SINV 0 R/W 1 -- 1 -- 0 SMIF 0 R/W Initial value : R/W : 1 -- SCMR is an 8-bit readable/writable register that selects the Smart Card interface function. SCMR is initialized to H'F2 by a reset and in standby mode. Bits 7 to 4--Reserved: These bits are always read as 1 and cannot be modified. Bit 3--Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion format. Bit 3 SDIR 0 Description TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first 1 TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first (Initial value) 491 Bit 2--Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This function is used together with the SDIR bit for communication with an inverse convention card. The SINV bit does not affect the logic level of the parity bit. For parity-related setting procedures, see section 14.3.4, Register Settings. Bit 2 SINV 0 Description TDR contents are transmitted as they are Receive data is stored as it is in RDR 1 TDR contents are inverted before being transmitted Receive data is stored in inverted form in RDR (Initial value) Bit 1--Reserved: This bit is always read as 1 and cannot be modified. Bit 0--Smart Card Interface Mode Select (SMIF): Enables or disables the Smart Card interface function. Bit 0 SMIF 0 1 Description Smart Card interface function is disabled Smart Card interface function is enabled (Initial value) 492 14.2.2 Bit Serial Status Register (SSR) : 7 TDRE 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 ERS 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W Initial value : R/W : 1 R/(W)* Note: * Only 0 can be written, for flag clearing. Bit 4 of SSR has a different function in Smart Card interface mode. Coupled with this, the setting conditions for bit 2, TEND, are also different. Bits 7 to 5--Operate in the same way as for the normal SCI. For details, see section 13.2.7, Serial Status Register (SSR). Bit 4--Error Signal Status (ERS): In Smart Card interface mode, bit 4 indicates the status of the error signal sent back from the receiving end in transmission. Framing errors are not detected in Smart Card interface mode. Bit 4 ERS 0 Description Normal reception, with no error signal [Clearing conditions] * * 1 Upon reset, and in standby mode or module stop mode When 0 is written to ERS after reading ERS = 1 (Initial value) Error signal sent from receiver indicating detection of parity error [Setting condition] When the low level of the error signal is sampled Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its previous state. 493 Bits 3 to 0--Operate in the same way as for the normal SCI. For details, see section 13.2.7, Serial Status Register (SSR). However, the setting conditions for the TEND bit, are as shown below. Bit 2 TEND 0 Description Transmission is in progress [Clearing conditions] * * 1 When 0 is written to TDRE after reading TDRE = 1 When the DTC is activated by a TXI interrupt and write data to TDR (Initial value) Transmission has ended [Setting conditions] * * * * * * Upon reset, and in standby mode or module stop mode When the TE bit in SCR is 0 and the ERS bit is also 0 When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after transmission of a 1-byte serial character when GM = 0 and BLK = 0 When TDRE = 1 and ERS = 0 (normal transmission) 1.5 etu after transmission of a 1-byte serial character when GM = 0 and BLK = 1 When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when GM = 1 and BLK = 0 When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when GM = 1 and BLK = 1 Note: etu: Elementary Time Unit (time for transfer of 1 bit) 494 14.2.3 Bit Serial Mode Register (SMR) : 7 GM 6 BLK 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 BCP1 0 R/W 2 BCP0 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Initial value : R/W : 0 R/W Note: When the smart card interface is used, be sure to make the 1 setting shown for bit 5. The function of bits 7, 6, 3, and 2 of SMR changes in Smart Card interface mode. Bit 7--GSM Mode (GM): Sets the smart card interface function to GSM mode. This bit is cleared to 0 when the normal smart card interface is used. In GSM mode, this bit is set to 1, the timing of setting of the TEND flag that indicates transmission completion is advanced and clock output control mode addition is performed. The contents of the clock output control mode addition are specified by bits 1 and 0 of the serial control register (SCR). Bit 7 GM 0 Description Normal smart card interface mode operation * * 1 * * (Initial value) TEND flag generation 12.5 etu (11.5 etu in block transfer mode) after beginning of start bit Clock output ON/OFF control only GSM mode smart card interface mode operation TEND flag generation 11.0 etu after beginning of start bit High/low fixing control possible in addition to clock output ON/OFF control (set by SCR) Note: etu: Elementary time unit (time for transfer of 1 bit) 495 Bit 6--Block Transfer Mode (BLK): Selects block transfer mode. Bit 6 BLK 0 Description Normal Smart Card interface mode operation * * * 1 Error signal transmission/detection and automatic data retransmission performed TXI interrupt generated by TEND flag TEND flag set 12.5 etu after start of transmission (11.0 etu in GSM mode) Block transfer mode operation * * * Error signal transmission/detection and automatic data retransmission not performed TXI interrupt generated by TDRE flag TEND flag set 11.5 etu after start of transmission (11.0 etu in GSM mode) Note: etu: Elementary Time Unit (time for transfer of 1 bit) Bits 3 and 2--Basic Clock Pulse 1 and 2 (BCP1, BCP0): These bits specify the number of basic clock periods in a 1-bit transfer interval on the Smart Card interface. Bit 3 BCP1 0 Bit 2 BCP0 1 0 1 1 0 Description 32 clock periods 64 clock periods 372 clock periods 256 clock periods (Initial value) Bits 5, 4, 1, and 0: Operate in the same way as for the normal SCI. For details, see section 13.2.5, Serial Mode Register (SMR). 496 14.2.4 Bit Serial Control Register (SCR) : 7 TIE 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W Initial value : R/W : 0 R/W In smart card interface mode, the function of bits 1 and 0 of SCR changes when bit 7 of the serial mode register (SMR) is set to 1. Bits 7 to 2--Operate in the same way as for the normal SCI. For details, see section 13.2.6, Serial Control Register (SCR). Bits 1 and 0--Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin. In smart card interface mode, in addition to the normal switching between clock output enabling and disabling, the clock output can be specified as to be fixed high or low. SCMR SMIF 0 1 1 1 1 1 1 SMR C/A, GM See the SCI 0 0 1 1 1 1 0 0 0 0 1 1 0 1 0 1 0 1 Operates as port I/O pin Outputs clock as SCK output pin Operates as SCK output pin, with output fixed low Outputs clock as SCK output pin Operates as SCK output pin, with output fixed high Outputs clock as SCK output pin SCR Setting CKE1 CKE0 SCK Pin Function 497 14.3 14.3.1 Operation Overview The main functions of the Smart Card interface are as follows. * * * * * One frame consists of 8-bit data plus a parity bit. In transmission, a guard time of at least 2 etu (Elementary Time Unit: the time for transfer of 1 bit) is left between the end of the parity bit and the start of the next frame. If a parity error is detected during reception, a low error signal level is output for one etu period, 10.5 etu after the start bit. If the error signal is sampled during transmission, the same data is transmitted automatically after the elapse of 2 etu or longer. (except in block transfer mode) Only asynchronous communication is supported; there is no clocked synchronous communication function. Pin Connections 14.3.2 Figure 14-2 shows a schematic diagram of Smart Card interface related pin connections. In communication with an IC card, since both transmission and reception are carried out on a single data transmission line, the TxD pin and RxD pin should be connected with the LSI pin. The data transmission line should be pulled up to the VCC power supply with a resistor. When the clock generated on the Smart Card interface is used by an IC card, the SCK pin output is input to the CLK pin of the IC card. No connection is needed if the IC card uses an internal clock. LSI port output is used as the reset signal. Other pins must normally be connected to the power supply or ground. 498 VCC TxD I/O RxD SCK Rx (port) H8S/2626 Series or H8S/2623 Series Connected equipment Data line Clock line Reset line CLK RST IC card Figure 14-2 Schematic Diagram of Smart Card Interface Pin Connections Note: If an IC card is not connected, and the TE and RE bits are both set to 1, closed transmission/reception is possible, enabling self-diagnosis to be carried out. 499 14.3.3 Data Format (1) Normal Transfer Mode Figure 14-3 shows the normal Smart Card interface data format. In reception in this mode, a parity check is carried out on each frame, and if an error is detected an error signal is sent back to the transmitting end, and retransmission of the data is requested. If an error signal is sampled during transmission, the same data is retransmitted. When there is no parity error Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Transmitting station output When a parity error occurs Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Transmitting station output Legend Ds D0 to D7 Dp DE Receiving station output : Start bit : Data bits : Parity bit : Error signal Figure 14-3 Normal Smart Card Interface Data Format 500 The operation sequence is as follows. [1] When the data line is not in use it is in the high-impedance state, and is fixed high with a pullup resistor. [2] The transmitting station starts transfer of one frame of data. The data frame starts with a start bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp). [3] With the Smart Card interface, the data line then returns to the high-impedance state. The data line is pulled high with a pull-up resistor. [4] The receiving station carries out a parity check. If there is no parity error and the data is received normally, the receiving station waits for reception of the next data. If a parity error occurs, however, the receiving station outputs an error signal (DE, low-level) to request retransmission of the data. After outputting the error signal for the prescribed length of time, the receiving station places the signal line in the high-impedance state again. The signal line is pulled high again by a pull-up resistor. [5] If the transmitting station does not receive an error signal, it proceeds to transmit the next data frame. If it does receive an error signal, however, it returns to step [2] and retransmits the erroneous data. (2) Block Transfer Mode The operation sequence in block transfer mode is as follows. [1] When the data line in not in use it is in the high-impedance state, and is fixed high with a pullup resistor. [2] The transmitting station starts transfer of one frame of data. The data frame starts with a start bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp). [3] With the Smart Card interface, the data line then returns to the high-impedance state. The data line is pulled high with a pull-up resistor. [4] After reception, a parity error check is carried out, but an error signal is not output even if an error has occurred. When an error occurs reception cannot be continued, so the error flag should be cleared to 0 before the parity bit of the next frame is received. [5] The transmitting station proceeds to transmit the next data frame. 501 14.3.4 Register Settings Table 14-3 shows a bit map of the registers used by the smart card interface. Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described below. Table 14-3 Smart Card Interface Register Settings Bit Register SMR BRR SCR TDR SSR RDR SCMR Bit 7 GM BRR7 TIE TDR7 TDRE RDR7 -- Bit 6 BLK BRR6 RIE TDR6 RDRF RDR6 -- Bit 5 1 BRR5 TE TDR5 ORER RDR5 -- Bit 4 O/E BRR4 RE TDR4 ERS RDR4 -- Bit 3 BCP1 BRR3 0 TDR3 PER RDR3 SDIR Bit 2 BCP0 BRR2 0 TDR2 TEND RDR2 SINV Bit 1 CKS1 BRR1 CKE1* TDR1 0 RDR1 -- Bit 0 CKS0 BRR0 CKE0 TDR0 0 RDR0 SMIF Notes: -- : Unused bit. *: The CKE1 bit must be cleared to 0 when the GM bit in SMR is cleared to 0. SMR Setting: The GM bit is cleared to 0 in normal smart card interface mode, and set to 1 in GSM mode. The O/E bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. Bits CKS1 and CKS0 select the clock source of the on-chip baud rate generator. Bits BCP1 and BCP0 select the number of basic clock periods in a 1-bit transfer interval. For details, see section 14.3.5, Clock. The BLK bit is cleared to 0 in normal smart card interface mode, and set to 1 in block transfer mode. BRR Setting: BRR is used to set the bit rate. See section 14.3.5, Clock, for the method of calculating the value to be set. SCR Setting: The function of the TIE, RIE, TE, and RE bits is the same as for the normal SCI. For details, see section 13, Serial Communication Interface (SCI). Bits CKE1 and CKE0 specify the clock output. When the GM bit in SMR is cleared to 0, set these bits to B'00 if a clock is not to be output, or to B'01 if a clock is to be output. When the GM bit in SMR is set to 1, clock output is performed. The clock output can also be fixed high or low. 502 Smart Card Mode Register (SCMR) Setting: The SDIR bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. The SINV bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. The SMIF bit is set to 1 in the case of the Smart Card interface. Examples of register settings and the waveform of the start character are shown below for the two types of IC card (direct convention and inverse convention). * Direct convention (SDIR = SINV = O/E = 0) (Z) A Ds Z D0 Z D1 A D2 Z D3 Z D4 Z D5 A D6 A D7 Z Dp (Z) State With the direct convention type, the logic 1 level corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order. The start character data above is H'3B. The parity bit is 1 since even parity is stipulated for the Smart Card. * Inverse convention (SDIR = SINV = O/E = 1) (Z) A Ds Z D7 Z D6 A D5 A D4 A D3 A D2 A D1 A D0 Z Dp (Z) State With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to state Z, and transfer is performed in MSB-first order. The start character data above is H'3F. The parity bit is 0, corresponding to state Z, since even parity is stipulated for the Smart Card. With the H8S/2626 Series and H8S/2623 Series, inversion specified by the SINV bit applies only to the data bits, D7 to D0. For parity bit inversion, the O/E bit in SMR is set to odd parity mode (the same applies to both transmission and reception). 503 14.3.5 Clock Only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock for the smart card interface. The bit rate is set with BRR and the CKS1, CKS0, BCP1 and BCP0 bits in SMR. The formula for calculating the bit rate is as shown below. Table 14-5 shows some sample bit rates. If clock output is selected by setting CKE0 to 1, a clock is output from the SCK pin. The clock frequency is determined by the bit rate and the setting of bits BCP1 and BCP0. B= o Sx2 2n+1 x (N + 1) x 10 6 Where: N = Value set in BRR (0 N 255) B = Bit rate (bit/s) o = Operating frequency (MHz) n = See table 14-4 S = Number of internal clocks in 1-bit period, set by BCP1 and BCP0 Table 14-4 Correspondence between n and CKS1, CKS0 n 0 1 2 3 1 CKS1 0 CKS0 0 1 0 1 Table 14-5 Examples of Bit Rate B (bit/s) for Various BRR Settings (When n = 0 and S = 372) o (MHz) N 0 1 2 10.00 13441 6720 4480 10.714 14400 7200 4800 13.00 17473 8737 5824 14.285 19200 9600 6400 16.00 21505 10753 7168 18.00 24194 12097 8065 20.00 26882 13441 8961 Note: Bit rates are rounded to the nearest whole number. 504 The method of calculating the value to be set in the bit rate register (BRR) from the operating frequency and bit rate, on the other hand, is shown below. N is an integer, 0 N 255, and the smaller error is specified. N= o Sx2 2n+1 xB x 10 6 - 1 Table 14-6 Examples of BRR Settings for Bit Rate B (bit/s) (When n = 0 and S = 372) o (MHz) 7.1424 bit/s 9600 N 0 Error 0.00 N 1 10.00 Error 30 10.7136 N 1 Error 25 N 1 13.00 Error 8.99 14.2848 N 1 Error 0.00 N 1 16.00 Error 12.01 N 2 18.00 Error 15.99 N 2 20.00 Error 6.60 Table 14-7 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) (when S = 372) o (MHz) 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 20.00 Maximum Bit Rate (bit/s) 9600 13441 14400 17473 19200 21505 24194 26882 N 0 0 0 0 0 0 0 0 n 0 0 0 0 0 0 0 0 The bit rate error is given by the following formula: Error (%) = ( o Sx2 2n+1 x B x (N + 1) x 106 - 1) x 100 505 14.3.6 Data Transfer Operations Initialization: Before transmitting and receiving data, initialize the SCI as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. [1] Clear the TE and RE bits in SCR to 0. [2] Clear the error flags ERS, PER, and ORER in SSR to 0. [3] Set the GM, BLK, O/E, BCP1, BCP0, CKS1, CKS0 bits in SMR. Set the PE bit to 1. [4] Set the SMIF, SDIR, and SINV bits in SCMR. When the SMIF bit is set to 1, the TxD and RxD pins are both switched from ports to SCI pins, and are placed in the high-impedance state. [5] Set the value corresponding to the bit rate in BRR. [6] Set the CKE0 and CKE1 bits in SCR. Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0. If the CKE0 bit is set to 1, the clock is output from the SCK pin. [7] Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the TE bit and RE bit at the same time, except for self-diagnosis. 506 Serial Data Transmission: As data transmission in smart card mode involves error signal sampling and retransmission processing, the processing procedure is different from that for the normal SCI. Figure 14-4 shows a flowchart for transmitting, and figure 14-5 shows the relation between a transmit operation and the internal registers. [1] Perform Smart Card interface mode initialization as described above in Initialization. [2] Check that the ERS error flag in SSR is cleared to 0. [3] Repeat steps [2] and [3] until it can be confirmed that the TEND flag in SSR is set to 1. [4] Write the transmit data to TDR, clear the TDRE flag to 0, and perform the transmit operation. The TEND flag is cleared to 0. [5] When transmitting data continuously, go back to step [2]. [6] To end transmission, clear the TE bit to 0. With the above processing, interrupt servicing or data transfer by the DTC is possible. If transmission ends and the TEND flag is set to 1 while the TIE bit is set to 1 and interrupt requests are enabled, a transmit data empty interrupt (TXI) request will be generated. If an error occurs in transmission and the ERS flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a transfer error interrupt (ERI) request will be generated. The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND flag set timing is shown in figure 14-6. If the DTC is activated by a TXI request, the number of bytes set in the DTC can be transmitted automatically, including automatic retransmission. For details, see Interrupt Operation and Data Transfer Operation by DTC below. Note: For block transfer mode, see section 13.3.2, Operation in Asynchronous Mode. 507 Start Initialization Start transmission ERS=0? Yes No Error processing No TEND=1? Yes Write data to TDR, and clear TDRE flag in SSR to 0 No All data transmitted? Yes No ERS=0? Yes Error processing No TEND=1? Yes Clear TE bit to 0 End Figure 14-4 Example of Transmission Processing Flow 508 TDR (1) Data write (2) Transfer from TDR to TSR (3) Serial data output Data 1 Data 1 Data 1 TSR (shift register) Data 1 ; Data remains in TDR Data 1 I/O signal line output In case of normal transmission: TEND flag is set In case of transmit error: ERS flag is set Steps (2) and (3) above are repeated until the TEND flag is set Note: When the ERS flag is set, it should be cleared until transfer of the last bit (D7 in LSB-first transmission, D0 in MSB-first transmission) of the next transfer data to be transmitted has been completed. Figure 14-5 Relation between Transmit Operation and Internal Registers I/O data TXI (TEND interrupt) When GM = 0 Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Guard time 12.5etu When GM = 1 11.0etu Legend Ds : Start bit D0 to D7 : Data bits Dp : Parity bit DE : Error signal etu: Elementary Time Unit (time for transfer of 1 bit) Figure 14-6 TEND Flag Generation Timing in Transmission Operation 509 Serial Data Reception (Except Block Transfer Mode): Data reception in Smart Card mode uses the same processing procedure as for the normal SCI. Figure 14-7 shows an example of the transmission processing flow. [1] Perform Smart Card interface mode initialization as described above in Initialization. [2] Check that the ORER flag and PER flag in SSR are cleared to 0. If either is set, perform the appropriate receive error processing, then clear both the ORER and the PER flag to 0. [3] Repeat steps [2] and [3] until it can be confirmed that the RDRF flag is set to 1. [4] Read the receive data from RDR. [5] When receiving data continuously, clear the RDRF flag to 0 and go back to step [2]. [6] To end reception, clear the RE bit to 0. Start Initialization Start reception ORER = 0 and PER = 0 Yes No Error processing No RDRF=1? Yes Read RDR and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit to 0 Figure 14-7 Example of Reception Processing Flow 510 With the above processing, interrupt servicing or data transfer by the DTC is possible. If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a receive data full interrupt (RXI) request will be generated. If an error occurs in reception and either the ORER flag or the PER flag is set to 1, a transfer error interrupt (ERI) request will be generated. If the DTC is activated by an RXI request, the receive data in which the error occurred is skipped, and only the number of bytes of receive data set in the DTC are transferred. For details, see Interrupt Operation and Data Transfer Operation by DTC below. If a parity error occurs during reception and the PER is set to 1, the received data is still transferred to RDR, and therefore this data can be read. Note: For block transfer mode, see section 13.3.2, Operation in Asynchronous Mode. Mode Switching Operation: When switching from receive mode to transmit mode, first confirm that the receive operation has been completed, then start from initialization, clearing RE bit to 0 and setting TE bit to 1. The RDRF flag or the PER and ORER flags can be used to check that the receive operation has been completed. When switching from transmit mode to receive mode, first confirm that the transmit operation has been completed, then start from initialization, clearing TE bit to 0 and setting RE bit to 1. The TEND flag can be used to check that the transmit operation has been completed. Fixing Clock Output Level: When the GM bit in SMR is set to 1, the clock output level can be fixed with bits CKE1 and CKE0 in SCR. At this time, the minimum clock pulse width can be made the specified width. Figure 14-8 shows the timing for fixing the clock output level. In this example, GSM is set to 1, CKE1 is cleared to 0, and the CKE0 bit is controlled. Specified pulse width Specified pulse width SCK SCR write (CKE0 = 0) SCR write (CKE0 = 1) Figure 14-8 Timing for Fixing Clock Output Level Interrupt Operation (Except Block Transfer Mode): There are three interrupt sources in smart card interface mode: transmit data empty interrupt (TXI) requests, transfer error interrupt (ERI) 511 requests, and receive data full interrupt (RXI) requests. The transmit end interrupt (TEI) request is not used in this mode. When the TEND flag in SSR is set to 1, a TXI interrupt request is generated. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When any of flags ORER, PER, and ERS in SSR is set to 1, an ERI interrupt request is generated. The relationship between the operating states and interrupt sources is shown in table 14-8. Note: For block transfer mode, see section 13.4, SCI Interrupts. Table 14-8 Smart Card Mode Operating States and Interrupt Sources Operating State Transmit Mode Normal operation Error Receive Mode Normal operation Error Flag TEND ERS RDRF PER, ORER Enable Bit TIE RIE RIE RIE Interrupt Source DTC Activation TXI ERI RXI ERI Possible Not possible Possible Not possible Data Transfer Operation by DTC: In smart card mode, as with the normal SCI, transfer can be carried out using the DTC. In a transmit operation, the TDRE flag is also set to 1 at the same time as the TEND flag in SSR, and a TXI interrupt is generated. If the TXI request is designated beforehand as a DTC activation source, the DTC will be activated by the TXI request, and transfer of the transmit data will be carried out. The TDRE and TEND flags are automatically cleared to 0 when data transfer is performed by the DTC. In the event of an error, the SCI retransmits the same data automatically. During this period, TEND remains cleared to 0 and the DTC is not activated. Therefore, the SCI and DTC will automatically transmit the specified number of bytes, including retransmission in the event of an error. However, the ERS flag is not cleared automatically when an error occurs, and so the RIE bit should be set to 1 beforehand so that an ERI request will be generated in the event of an error, and the ERS flag will be cleared. When performing transfer using the DTC, it is essential to set and enable the DTC before carrying out SCI setting. For details of the DTC setting procedures, see section 8, Data Transfer Controller (DTC). In a receive operation, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. If the RXI request is designated beforehand as a DTC activation source, the DTC will be activated by the RXI request, and transfer of the receive data will be carried out. The RDRF flag is cleared to 0 automatically when data transfer is performed by the DTC. If an error occurs, an error flag is set but the RDRF flag is not. Consequently, the DTC is not activated, but instead, an ERI interrupt request is sent to the CPU. Therefore, the error flag should be cleared. 512 Note: For block transfer mode, see section 13.4, SCI Interrupts. 14.3.7 Operation in GSM Mode Switching the Mode: When switching between smart card interface mode and software standby mode, the following switching procedure should be followed in order to maintain the clock duty. * When changing from smart card interface mode to software standby mode [1] Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin to the value for the fixed output state in software standby mode. [2] Write 0 to the TE bit and RE bit in the serial control register (SCR) to halt transmit/receive operation. At the same time, set the CKE1 bit to the value for the fixed output state in software standby mode. [3] Write 0 to the CKE0 bit in SCR to halt the clock. [4] Wait for one serial clock period. During this interval, clock output is fixed at the specified level, with the duty preserved. [5] Make the transition to the software standby state. * When returning to smart card interface mode from software standby mode [6] Exit the software standby state. [7] Write 1 to the CKE0 bit in SCR and output the clock. Signal generation is started with the normal duty. Software standby Normal operation Normal operation [1] [2] [3] [4] [5] [6] [7] Figure 14-9 Clock Halt and Restart Procedure 513 Powering On: To secure the clock duty from power-on, the following switching procedure should be followed. [1] The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor to fix the potential. [2] Fix the SCK pin to the specified output level with the CKE1 bit in SCR. [3] Set SMR and SCMR, and switch to smart card mode operation. [4] Set the CKE0 bit in SCR to 1 to start clock output. 14.3.8 Operation in Block Transfer Mode Operation in block transfer mode is the same as in SCI asynchronous mode, except for the following points. For details, see section 13.3.2, Operation in Asynchronous Mode. (1) Data Format The data format is 8 bits with parity. There is no stop bit, but there is a 2-bit (1-bit or more in reception) error guard time. Also, except during transmission (with start bit, data bits, and parity bit), the transmission pins go to the high-impedance state, so the signal lines must be fixed high with a pull-up resistor. (2) Transmit/Receive Clock Only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock. The number of basic clock periods in a 1-bit transfer interval can be set to 32, 64, 372, or 256 with bits BCP1 and BCP0. For details, see section 14.3.5, Clock. (3) ERS (FER) Flag As with the normal Smart Card interface, the ERS flag indicates the error signal status, but since error signal transmission and reception is not performed, this flag is always cleared to 0. 514 14.4 Usage Notes The following points should be noted when using the SCI as a Smart Card interface. Receive Data Sampling Timing and Reception Margin in Smart Card Interface Mode: In Smart Card interface mode, the SCI operates on a basic clock with a frequency of 32, 64, 372, or 256 times the transfer rate (as determined by bits BCP1 and BCP0). In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 16th, 32nd, 186th, or 128th pulse of the basic clock. Figure 14-10 shows the receive data sampling timing when using a clock of 372 times the transfer rate. 372 clocks 186 clocks 0 185 371 0 185 371 0 Internal basic clock Receive data (RxD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 14-10 Receive Data Sampling Timing in Smart Card Mode (Using Clock of 372 Times the Transfer Rate) 515 Thus the reception margin in asynchronous mode is given by the following formula. Formula for reception margin in smart card interface mode M = (0.5 - 1 2N ) - (L - 0.5) F - D - 0.5 N (1 + F) x 100% Where M: Reception margin (%) N: Ratio of bit rate to clock (N = 32, 64, 372, and 256) D: Clock duty (D = 0 to 1.0) L: Frame length (L = 10) F: Absolute value of clock frequency deviation Assuming values of F = 0, D = 0.5 and N = 372 in the above formula, the reception margin formula is as follows. When D = 0.5 and F = 0, M = (0.5 - 1/2 x 372) x 100% = 49.866% Retransfer Operations (Except Block Transfer Mode): Retransfer operations are performed by the SCI in receive mode and transmit mode as described below. * Retransfer operation when SCI is in receive mode Figure 14-11 illustrates the retransfer operation when the SCI is in receive mode. [1] If an error is found when the received parity bit is checked, the PER bit in SSR is automatically set to 1. If the RIE bit in SCR is enabled at this time, an ERI interrupt request is generated. The PER bit in SSR should be kept cleared to 0 until the next parity bit is sampled. [2] The RDRF bit in SSR is not set for a frame in which an error has occurred. [3] If no error is found when the received parity bit is checked, the PER bit in SSR is not set to 1. [4] If no error is found when the received parity bit is checked, the receive operation is judged to have been completed normally, and the RDRF flag in SSR is automatically set to 1. If the RIE bit in SCR is enabled at this time, an RXI interrupt request is generated. If DTC data transfer by an RXI source is enabled, the contents of RDR can be read automatically. When the RDR data is read by the DTC, the RDRF flag is automatically cleared to 0. [5] When a normal frame is received, the pin retains the high-impedance state at the timing for error signal transmission. 516 nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE RDRF [2] PER [1] Retransferred frame Transfer frame n+1 (DE) Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Ds D0 D1 D2 D3 D4 [4] [3] Figure 14-11 Retransfer Operation in SCI Receive Mode * Retransfer operation when SCI is in transmit mode Figure 14-12 illustrates the retransfer operation when the SCI is in transmit mode. [6] If an error signal is sent back from the receiving end after transmission of one frame is completed, the ERS bit in SSR is set to 1. If the RIE bit in SCR is enabled at this time, an ERI interrupt request is generated. The ERS bit in SSR should be kept cleared to 0 until the next parity bit is sampled. [7] The TEND bit in SSR is not set for a frame for which an error signal indicating an abnormality is received. [8] If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set. [9] If an error signal is not sent back from the receiving end, transmission of one frame, including a retransfer, is judged to have been completed, and the TEND bit in SSR is set to 1. If the TIE bit in SCR is enabled at this time, a TXI interrupt request is generated. If data transfer by the DTC by means of the TXI source is enabled, the next data can be written to TDR automatically. When data is written to TDR by the DTC, the TDRE bit is automatically cleared to 0. Transfer frame n+1 (DE) Ds D0 D1 D2 D3 D4 nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE TDRE Transfer to TSR from TDR TEND [7] FER/ERS [6] Retransferred frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Transfer to TSR from TDR Transfer to TSR from TDR [9] [8] Figure 14-12 Retransfer Operation in SCI Transmit Mode 517 518 Section 15 Hitachi Controller Area Network (HCAN) 15.1 Overview The HCAN is a module for controlling a controller area network (CAN) for realtime communication in vehicular and industrial equipment systems, etc. The H8S/2626 Series and H8S/2623 Series have a single-channel on-chip HCAN module. Reference: BOSCH CAN Specification Version 2.0 1991, Robert Bosch GmbH 15.1.1 Features * CAN version: Bosch 2.0B active compatible Communication systems: NRZ (Non-Return to Zero) system (with bit-stuffing function) Broadcast communication system Transmission path: Bidirectional 2-wire serial communication Communication speed: Max. 1 Mbps Data length: 0 to 8 bytes * Number of channels: 1 * Data buffers: 16 (one receive-only buffer and 15 buffers settable for transmission/reception) * Data transmission: Choice of two methods: Mailbox (buffer) number order (low-to-high) Message priority (identifier) high-to-low order * Data reception: Two methods: Message identifier match (transmit/receive-setting buffers) Reception with message identifier masked (receive-only) * CPU interrupts: Five interrupt vectors: Error interrupt Reset processing interrupt Message reception interrupt (mailboxes 1 to 15) Message reception interrupt (mailbox 0) Message transmission interrupt * HCAN operating modes: Support for various modes: Hardware reset Software reset Normal status (error-active, error-passive) Bus off status 519 HCAN configuration mode HCAN sleep mode HCAN halt mode * Other features: DTC can be activated by message reception mailbox (HCAN mailbox 0 only) 15.1.2 Block Diagram Figure 15-1 shows a block diagram of the HCAN. HCAN Peripheral address bus MBI Message buffer Peripheral data bus Mailboxes Message control Message data MC0-MC15, MD0-MD15 LAFM (CDLC) CAN Data Link Controller Bosch CAN 2.0B active HTxD Tx buffer MPI Microprocessor interface CPU interface Control register Status register Rx buffer HRxD Figure 15-1 HCAN Block Diagram Message Buffer Interface (MBI): The MBI, consisting of mailboxes and a local acceptance filter mask (LAFM), stores CAN transmit/receive messages (identifiers, data, etc.) Transmit messages are written by the CPU. For receive messages, the data received by the CDLC is stored automatically. Microprocessor Interface (MPI): The MPI, consisting of a bus interface, control register, status register, etc., controls HCAN internal data, statuses, and so forth. CAN Data Link Controller (CDLC): The CDLC performs transmission and reception of messages conforming to the Bosch CAN Ver. 2.0B active standard (data frames, remote frames, error frames, overload frames, inter-frame spacing), as well as CRC checking, bus arbitration, and other functions. 520 15.1.3 Pin Configuration Table 15-1 shows the HCAN's pins. When using HCAN pins, settings must be made in the HCAN configuration mode (during initialization: MCR0 = 1 and GSR3 = 1). Table 15-1 HCAN Pins Name HCAN transmit data pin HCAN receive data pin Abbreviation HTxD HRxD Input/Output Output Input Function CAN bus transmission pin CAN bus reception pin A bus driver is necessary between the pins and the CAN bus. A Philips PCA82C250 compatible model is recommended. 521 15.1.4 Register Configuration Table 15-2 lists the HCAN's registers. Table 15-2 HCAN Registers Name Master control register General status register Bit configuration register Mailbox configuration register Transmit wait register Transmit wait cancel register Transmit acknowledge register Abort acknowledge register Receive complete register Remote request register Interrupt register Mailbox interrupt mask register Interrupt mask register Receive error counter Transmit error counter Unread message status register Local acceptance filter mask L Local acceptance filter mask H Abbreviation R/W MCR GSR BCR MBCR TXPR TXCR TXACK ABACK RXPR RFPR IRR MBIMR IMR REC TEC UMSR LAFML LAFMH R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W Initial Value Address* Access Size H'01 H'0C H'0000 H'0100 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0100 H'FFFF H'FEFF H'00 H'00 H'0000 H'0000 H'0000 H'F800 H'F801 H'F802 H'F804 H'F806 H'F808 H'F80A H'F80C H'F80E H'F810 H'F812 H'F814 H'F816 H'F818 H'F819 H'F81A H'F81C H'F81E 8 bits 16 bits 8 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8 bits 16 bits 8 bits 8/16 bits 8/16 bits 8/16 bits 522 Name Message control 0 [1:8] Message control 1 [1:8] Message control 2 [1:8] Message control 3 [1:8] Message control 4 [1:8] Message control 5 [1:8] Message control 6 [1:8] Message control 7 [1:8] Message control 8 [1:8] Message control 9 [1:8] Message control 10 [1:8] Message control 11 [1:8] Message control 12 [1:8] Message control 13 [1:8] Message control 14 [1:8] Message control 15 [1:8] Message data 0 [1:8] Message data 1 [1:8] Message data 2 [1:8] Message data 3 [1:8] Message data 4 [1:8] Message data 5 [1:8] Message data 6 [1:8] Message data 7 [1:8] Message data 8 [1:8] Message data 9 [1:8] Message data 10 [1:8] Message data 11 [1:8] Message data 12 [1:8] Message data 13 [1:8] Message data 14 [1:8] Message data 15 [1:8] Module stop control register C Abbreviation MC0 [1:8] MC1 [1:8] MC2 [1:8] MC3 [1:8] MC4 [1:8] MC5 [1:8] MC6 [1:8] MC7 [1:8] MC8 [1:8] MC9 [1:8] MC10 [1:8] MC11 [1:8] MC12 [1:8] MC13 [1:8] MC14 [1:8] MC15 [1:8] MD0 [1:8] MD1 [1:8] MD2 [1:8] MD3 [1:8] MD4 [1:8] MD5 [1:8] MD6 [1:8] MD7 [1:8] MD8 [1:8] MD9 [1:8] MD10 [1:8] MD11 [1:8] MD12 [1:8] MD13 [1:8] MD14 [1:8] MD15 [1:8] MSTPCRC R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined H'FF Address* Access Size H'F820 H'F828 H'F830 H'F838 H'F840 H'F848 H'F850 H'F858 H'F860 H'F868 H'F870 H'F878 H'F880 H'F888 H'F890 H'F898 H'F8B0 H'F8B8 H'F8C0 H'F8C8 H'F8D0 H'F8D8 H'F8E0 H'F8E8 H'F8F0 H'F8F8 H'F900 H'F908 H'F910 H'F918 H'F920 H'F928 H'FDEA 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits Note: * Lower 16 bits of the address. 523 15.2 15.2.1 Register Descriptions Master Control Register (MCR) The master control register (MCR) is an 8-bit readable/writable register that controls the CAN interface. MCR Bit: 7 MCR7 Initial value: R/W: 0 R/W 6 -- 0 R 5 MCR5 0 R/W 4 -- 0 R 3 -- 0 R 2 MCR2 0 R/W 1 MCR1 0 R/W 0 MCR0 1 R/W Bit 7--HCAN Sleep Mode Release (MCR7): Enables or disables HCAN sleep mode release by bus operation. Bit 7: MCR7 0 1 Description HCAN sleep mode release by CAN bus operation disabled HCAN sleep mode release by CAN bus operation enabled (Initial value) Bit 6--Reserved: This bit always reads 0. The write value should always be 0. Bit 5--HCAN Sleep Mode (MCR5): Enables or disables HCAN sleep mode transition. Bit 5: MCR5 0 1 Description HCAN sleep mode released Transition to HCAN sleep mode enabled (Initial value) Bits 4 and 3--Reserved: These bits always read 0. The write value should always be 0. Bit 2--Message Transmission Method (MCR2): Selects the transmission method for transmit messages. Bit 2: MCR2 0 1 Description Transmission order determined by message identifier priority (Initial value) Transmission order determined by mailbox (buffer) number priority (TXPR1 > TXPR15) 524 Bit 1--Halt Request (MCR1): Controls halting of the HCAN module. Bit 1: MCR1 0 1 Description HCAN normal operating mode HCAN halt mode transition request (Initial value) Bit 0--Reset Request (MCR0): Controls resetting of the HCAN module. Bit 0: MCR0 0 Description Normal operating mode (MCR0 = 0 and GSR3 = 0) [Setting condition] When 0 is written after an HCAN reset 1 HCAN reset mode transition request (Initial value) In order for GSR3 to change from 1 to 0 after 0 is written to MCR0, time is required before the HCAN is internally reset. There is consequently a delay before GSR3 is cleared to 0 after MCR0 is cleared to 0. 15.2.2 General Status Register (GSR) The general status register (GSR) is an 8-bit readable register that indicates the status of the CAN bus. GSR Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 GSR3 1 R 2 GSR2 1 R 1 GSR1 0 R 0 GSR0 0 R Bits 7 to 4--Reserved: These bits always read 0. 525 Bit 3--Reset Status Bit (GSR3): Indicates whether the HCAN module is in the normal operating state or the reset state. Writes are invalid. Bit 3: GSR3 0 Description Normal operating state [Setting condition] After an HCAN internal reset 1 Configuration mode [Reset condition] MCR0 reset mode and sleep mode (Initial value) Bit 2--Message Transmission Status Flag (GSR2): Flag that indicates whether the module is currently in the message transmission period. The "message transmission period" is the period from the start of message transmission (SOF) until the end of a 3-bit intermission interval after EOF (End of Frame). Writes are invalid. Bit 2: GSR2 0 1 Description Message transmission period [Reset Condition] Idle period (Initial value) Bit 1--Transmit/Receive Warning Flag (GSR1): Flag that indicates an error warning. Writes are invalid. Bit 1: GSR1 0 1 Description [Reset condition] When TEC < 96 and REC < 96 or TEC 256 When TEC 96 or REC 96 (Initial value) Bit 0--Bus Off Flag (GSR0): Flag that indicates the bus off state. Writes are invalid. Bit 0: GSR0 0 1 Description [Reset condition] Recovery from bus off state When TEC 256 (bus off state) (Initial value) 526 15.2.3 Bit Configuration Register (BCR) The bit configuration register (BCR) is a 16-bit readable/writable register that is used to set CAN bit timing parameters and the baud rate prescaler. BCR Bit: 15 BCR7 Initial value: R/W: Bit: 0 R/W 7 BCR15 Initial value: R/W: 0 R/W 14 BCR6 0 R/W 6 BCR14 0 R/W 13 BCR5 0 R/W 5 BCR13 0 R/W 12 BCR4 0 R/W 4 BCR12 0 R/W 11 BCR3 0 R/W 3 BCR11 0 R/W 10 BCR2 0 R/W 2 BCR10 0 R/W 9 BCR1 0 R/W 1 BCR9 0 R/W 8 BCR0 0 R/W 0 BCR8 0 R/W Bits 15 and 14--Resynchronization Jump Width (SJW): These bits set the bit synchronization range. Bit 15: BCR7 0 Bit 14: BCR6 0 1 1 0 1 Description Bit synchronization width = 1 time quantum Bit synchronization width = 2 time quanta Bit synchronization width = 3 time quanta Bit synchronization width = 4 time quanta (Initial value) Bits 13 to 8--Baud Rate Prescaler (BRP): These bits are used to set the CAN bus baud rate. Bit 13: BCR5 0 0 0 1 Bit 12: BCR4 0 0 0 1 Bit 11: BCR3 0 0 0 1 Bit 10: BCR2 0 0 0 1 Bit 9: BCR1 0 0 1 1 Bit 8: BCR0 0 1 0 1 Description 2 x system clock 4 x system clock 6 x system clock 128 x system clock (Initial value) 527 Bit 7--Bit Sample Point (BSP): Sets the point at which data is sampled. Bit 7: BCR15 0 1 Description Bit sampling at one point (end of time segment 1 (TSEG1)) (Initial value) Bit sampling at three points (end of TSEG1 and preceding and following time quantum) Bits 6 to 4--Time Segment 2 (TSEG2): These bits are used to set the segment for correcting 1bit time error. A value from 2 to 8 can be set. Bit 6: BCR14 0 Bit 5: BCR13 0 Bit 4: BCR12 0 1 1 0 1 1 0 0 1 1 0 1 Description Setting prohibited TSEG2 = 2 time quanta TSEG2 = 3 time quanta TSEG2 = 4 time quanta TSEG2 = 5 time quanta TSEG2 = 6 time quanta TSEG2 = 7 time quanta TSEG2 = 8 time quanta (Initial value) Bits 3 to 0--Time Segment 1 (TSEG1): These bits are used to set the segment for absorbing output buffer, CAN bus, and input buffer delay. A value from 1 to 16 can be set. Bit 3: BCR11 0 0 0 0 0 1 Bit 2: BCR10 0 0 0 0 1 1 Bit 1: BCR9 0 0 1 1 0 1 Bit 0: BCR8 0 1 0 1 0 1 Description Setting prohibited Setting prohibited Setting prohibited TSEG1 = 4 time quanta TSEG1 = 5 time quanta TSEG1 = 16 time quanta (Initial value) 528 15.2.4 Mailbox Configuration Register (MBCR) The mailbox configuration register (MBCR) is a 16-bit readable/writable register that is used to set mailbox (buffer) transmission/reception. MBCR Bit: 15 MBCR7 14 MBCR6 13 MBCR5 12 MBCR4 11 MBCR3 10 MBCR2 9 MBCR1 8 -- 1 R 0 MBCR8 Initial value: R/W: Bit: 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 MBCR9 MBCR15 MBCR14 MBCR13 MBCR12 MBCR11 MBCR10 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bits 15 to 9 and 7 to 0--Mailbox Setting Register (MBCR7 to MBCR1, MBCR15 to MBCR8): These bits set the polarity of the corresponding mailboxes. Bit x: MBCRx 0 1 Description Corresponding mailbox is set for transmission Corresponding mailbox is set for reception (Initial value) Bit 8--Reserved: This bit always reads 1. The write value should always be 1. 529 15.2.5 Transmit Wait Register (TXPR) The transmit wait register (TXPR) is a 16-bit readable/writable register that is used to set a transmit wait after a transmit message is stored in a mailbox (buffer) (CAN bus arbitration wait). TXPR Bit: 15 TXPR7 Initial value: R/W: Bit: 0 R/W 7 14 TXPR6 0 R/W 6 13 TXPR5 0 R/W 5 12 TXPR4 0 R/W 4 11 TXPR3 0 R/W 3 10 TXPR2 0 R/W 2 9 TXPR1 0 R/W 1 8 -- 0 R 0 TXPR8 0 R/W TXPR15 TXPR14 TXPR13 TXPR12 TXPR11 TXPR10 TXPR9 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bits 15 to 9 and 7 to 0--Transmit Wait Register (TXPR7 to TXPR1, TXPR15 to TXPR8): These bits set a transmit wait for the corresponding mailboxes. Bit x: TXPRx 0 Description Transmit message idle state in corresponding mailbox [Clearing condition] Message transmission completion and cancellation completion 1 Transmit message transmit wait in corresponding mailbox (CAN bus arbitration) (Initial value) Bit 8--Reserved: This bit always reads 0. The write value should always be 0. 530 15.2.6 Transmit Wait Cancel Register (TXCR) The transmit wait cancel register (TXCR) is a 16-bit readable/writable register that controls cancellation of transmit wait messages in mailboxes (buffers). TXCR Bit: 15 TXCR7 Initial value: R/W: Bit: 0 R/W 7 14 TXCR6 0 R/W 6 13 TXCR5 0 R/W 5 12 TXCR4 0 R/W 4 11 TXCR3 0 R/W 3 10 TXCR2 0 R/W 2 9 TXCR1 0 R/W 1 8 -- 0 R 0 TXCR8 0 R/W TXCR15 TXCR14 TXCR13 TXCR12 TXCR11 TXCR10 TXCR9 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bits 15 to 9 and 7 to 0--Transmit Wait Cancel Register (TXCR7 to TXCR1, TXCR15 to TXCR8): These bits control cancellation of transmit wait messages in the corresponding HCAN mailboxes. Bit x: TXCRx 0 Description Transmit message cancellation idle state in corresponding mailbox (Initial value) [Clearing condition] Completion of TXPR clearing (when transmit message is canceled normally) 1 TXPR cleared for corresponding mailbox (transmit message cancellation) Bit 8--Reserved: This bit always reads 0. The write value should always be 0. 531 15.2.7 Transmit Acknowledge Register (TXACK) The transmit acknowledge register (TXACK) is a 16-bit readable/writable register containing status flags that indicate normal transmission of mailbox (buffer) transmit messages. TXACK Bit: 15 TXACK7 14 13 12 11 10 TXACK2 9 TXACK1 8 -- 0 R 0 TXACK6 TXACK5 TXACK4 TXACK3 Initial value: R/W: Bit: 0 R/(W)* 7 0 0 0 0 0 R/(W) * 2 0 R/(W) * 1 R/(W) * R/(W) * 6 5 R/(W) * R/(W) * 4 3 TXACK15 TXACK14 TXACK13 TXACK12 TXACK11 TXACK10 TXACK9 TXACK8 Initial value: R/W: 0 R/(W) * 0 0 0 0 0 R/(W) * 0 0 R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * Note: * Can only be written with 1 for flag clearing. Bits 15 to 9 and 7 to 0--Transmit Acknowledge Register (TXACK7 to TXACK1, TXACK15 to TXACK8): These bits indicate that a transmit message in the corresponding HCAN mailbox has been transmitted normally. Bit x: TXACKx 0 1 Description [Clearing condition] Writing 1 (Initial value) Completion of message transmission for corresponding mailbox Bit 8--Reserved: This bit always reads 0. The write value should always be 0. 532 15.2.8 Abort Acknowledge Register (ABACK) The abort acknowledge register (ABACK) is a 16-bit readable/writable register containing status flags that indicate normal cancellation (aborting) of a mailbox (buffer) transmit messages. ABACK Bit: 15 ABACK7 14 13 12 11 10 ABACK2 9 ABACK1 8 -- 0 R 0 ABACK6 ABACK5 ABACK4 ABACK3 Initial value: R/W: Bit: 0 R/(W)* 7 0 0 0 R/(W)* 4 0 R/(W) * 3 0 R/(W) * 2 0 R/(W) * 1 R/(W) * R/(W) * 6 5 ABACK15 ABACK14 ABACK13 ABACK12 ABACK11 ABACK10 ABACK9 ABACK8 Initial value: R/W: 0 R/(W)* 0 0 0 R/(W) * 0 R/(W)* 0 R/(W) * 0 0 R/(W) * R/(W) * R/(W) * R/(W) * Note: * Can only be written with 1 for flag clearing. Bits 15 to 9 and 7 to 0--Abort Acknowledge Register (ABACK7 to ABACK1, ABACK15 to ABACK8): These bits indicate that a transmit message in the corresponding mailbox has been canceled (aborted) normally. Bit x: ABACKx 0 1 Description [Clearing condition] Writing 1 (Initial value) Completion of transmit message cancellation for corresponding mailbox Bit 8--Reserved: This bit always reads 0. The write value should always be 0. 533 15.2.9 Receive Complete Register (RXPR) The receive complete register (RXPR) is a 16-bit readable/writable register containing status flags that indicate normal reception of messages (data frame or remote frame) in mailboxes (buffers). In the case of remote frame reception, the corresponding remote request register (RFPR) is also set simultaneously. RXPR Bit: 15 RXPR7 Initial value: R/W: Bit: 0 R/(W)* 7 14 13 12 11 10 RXPR2 0 R/(W) * 2 9 8 RXPR6 RXPR5 0 0 RXPR4 RXPR3 0 R/(W) * 4 0 R/(W)* 3 RXPR1 RXPR0 0 0 R/(W) * R/(W) * 6 5 R/(W) * R/(W) * 1 0 RXPR15 RXPR14 RXPR13 RXPR12 RXPR11 RXPR10 RXPR9 RXPR8 Initial value: R/W: 0 R/(W)* 0 0 0 R/(W) * 0 R/(W)* 0 R/(W) * 0 0 R/(W) * R/(W) * R/(W) * R/(W) * Note: * Can only be written with 1 for flag clearing. Bits 15 to 0--Receive Complete Register (RXPR7 to RXPR0, RXPR15 to RXPR8): These bits indicate that a receive message has been received normally in the corresponding mailbox. Bit x: RXPRx 0 1 Description [Clearing condition] Writing 1 (Initial value) Completion of message (data frame or remote frame) reception in corresponding mailbox 534 15.2.10 Remote Request Register (RFPR) The remote request register (RFPR) is a 16-bit readable/writable register containing status flags that indicate normal reception of remote frames in mailboxes (buffers). When a bit in this register is set, the corresponding reception complete bit is set simultaneously. RFPR Bit: 15 RFPR7 Initial value: R/W: Bit: 0 R/(W)* 7 14 RFPR6 0 13 RFPR5 0 12 RFPR4 0 R/(W) * 4 11 RFPR3 0 R/(W)* 3 10 RFPR2 0 R/(W) * 2 9 RFPR1 0 8 RFPR0 0 R/(W) * R/(W) * 6 5 R/(W) * R/(W) * 1 0 RFPR8 0 RFPR15 RFPR14 RFPR13 RFPR12 RFPR11 RFPR10 RFPR9 Initial value: R/W: 0 R/(W)* 0 0 0 R/(W) * 0 R/(W)* 0 R/(W) * 0 R/(W) * R/(W) * R/(W) * R/(W) * Note: * Can only be written with 1 for flag clearing. Bits 15 to 0--Remote Request Register (RFPR7 to PFPR0, RFPR15 to PFDR8): These bits indicate that a remote frame has been received normally in the corresponding mailbox. Bit x: RFPRx 0 1 Description [Clearing condition] Writing 1 (Initial value) Completion of remote frame reception in corresponding mailbox 535 15.2.11 Interrupt Register (IRR) The interrupt register (IRR) is a 16-bit readable/writable register containing status flags for the various interrupt sources. IRR Bit: 15 IRR7 Initial value: R/W: Bit: 0 R/(W)* 7 -- Initial value: R/W: 0 -- 14 IRR6 0 13 IRR5 0 12 IRR4 0 11 IRR3 0 10 IRR2 0 R 2 -- 0 -- 9 IRR1 0 R 1 IRR9 0 R 8 IRR0 1 R/(W) * 0 IRR8 0 R/(W) * R/(W) * R/(W) * 6 -- 0 -- 5 -- 0 -- R/(W) * R/(W) * 4 IRR12 0 R/(W) * 3 -- 0 -- Note: * Can only be written with 1 for flag clearing. Bit 15--Overload Frame/Bus Off Recovery Interrupt Flag (IRR7): Status flag indicating that the HCAN has transmitted an overload frame or recovered from the bus off state. Bit 15: IRR7 0 1 Description [Clearing condition] Writing 1 Overload frame transmission or recovery from bus off state [Setting conditions] Error active/passive state * When overload frame is transmitted Bus off state * When 11 recessive bits is received 128 times (REC 128) (Initial value) Bit 14--Bus Off Interrupt Flag (IRR6): Status flag indicating the bus off state caused by the transmit error counter. Bit 14: IRR6 0 1 Description [Clearing condition] Writing 1 Bus off state caused by transmit error [Setting condition] When TEC 256 536 (Initial value) Bit 13--Error Passive Interrupt Flag (IRR5): Status flag indicating the error passive state caused by the transmit/receive error counter. Bit 13: IRR5 0 1 Description [Clearing condition] Writing 1 Error passive state caused by transmit/receive error [Setting condition] When TEC 128 or REC 128 (Initial value) Bit 12--Receive Overload Warning Interrupt Flag (IRR4): Status flag indicating the error warning state caused by the receive error counter. Bit 12: IRR4 0 1 Description [Clearing condition] Writing 1 Error warning state caused by receive error [Setting condition] When REC 96 (Initial value) Bit 11--Transmit Overload Warning Interrupt Flag (IRR3): Status flag indicating the error warning state caused by the transmit error counter. Bit 11: IRR3 0 1 Description [Clearing condition] Writing 1 Error warning state caused by transmit error [Setting condition] When TEC 96 (Initial value) Bit 10--Remote Frame Request Interrupt Flag (IRR2): Status flag indicating that a remote frame has been received in a mailbox (buffer). Bit 10: IRR2 0 Description [Clearing condition] Clearing of all bits in RFPR (remote request register) of mailbox for which receive interrupt requests are enabled by MBIMR (Initial value) Remote frame received and stored in mailbox [Setting conditions] When remote frame reception is completed, when corresponding MBIMR = 0 1 537 Bit 9--Receive Message Interrupt Flag (IRR1): Status flag indicating that a mailbox (buffer) receive message has been received normally. Bit 9: IRR1 0 Description [Clearing condition] Clearing of all bits in RXPR (receive complete register) of mailbox for which receive interrupt requests are enabled by MBIMR (Initial value) Data frame or remote frame received and stored in mailbox [Setting conditions] When data frame or remote frame reception is completed, when corresponding MBIMR = 0 1 Bit 8--Reset Interrupt Flag (IRR0): Status flag indicating that the HCAN module has been reset. This bit cannot be masked in the interrupt mask register (IMR). If this bit is not cleared after reset input or recovery from software standby mode, interrupt handling will be performed as soon as interrupts are enabled by the interrupt controller. Bit 8: IRR0 0 1 Description [Clearing condition] Writing 1 Hardware reset (HCAN module stop*, software standby) (Initial value) [Setting condition] When reset processing is completed after a hardware reset (HCAN module stop*, software standby) Note: * After reset or hardware standby release, the module stop bit is initialized to 1, and so the HCAN enters the module stop state. Bits 7 to 5, 3, and 2--Reserved: These bits always read 0. The write value should always be 0. Bit 4--Bus Operation Interrupt Flag (IRR12): Status flag indicating detection of a dominant bit due to bus operation when the HCAN module is in HCAN sleep mode. Bit 4: IRR12 0 Description CAN bus idle state [Clearing condition] Writing 1 1 CAN bus operation in HCAN sleep mode [Setting condition] Bus operation (dominant bit detection) in HCAN sleep mode (Initial value) 538 Bit 1--Unread Interrupt Flag (IRR9): Status flag indicating that a receive message has been overwritten while still unread. Bit 1: IRR9 0 1 Description [Clearing condition] Clearing of all bits in UMSR (unread message status register) (Initial value) Unread message overwrite [Setting condition] When UMSR (unread message status register) is set Bit 0--Mailbox Empty Interrupt Flag (IRR8): Status flag indicating that the next transmit message can be stored in the mailbox. Bit 0: IRR8 0 1 Description [Clearing condition] Writing 1 (Initial value) Transmit message has been transmitted or aborted, and new message can be stored [Setting condition] When TXPR (transmit wait register) is cleared by completion of transmission or completion of transmission abort 539 15.2.12 Mailbox Interrupt Mask Register (MBIMR) The mailbox interrupt mask register (MBIMR) is a 16-bit readable/writable register containing flags that enable or disable individual mailbox (buffer) interrupt requests. MBIMR Bit: 15 MBIMR7 14 13 12 11 10 MBIMR2 9 8 MBIMR6 MBIMR5 MBIMR4 MBIMR3 MBIMR1 MBIMR0 Initial value: R/W: Bit: 1 R/W 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 MBIMR15 MBIMR14 MBIMR13 MBIMR12 MBIMR11 MBIMR10 MBIMR9 MBIMR8 Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Bits 15 to 0--Mailbox Interrupt Mask (MBIMRx) (MBIMR7 to MBIMR0, MBIMR15 to MBIMR8): Flags that enable or disable individual mailbox interrupt requests. Bit x: MBIMRx 0 Description [Transmitting] Interrupt request to CPU due to TXPR clearing [Receiving] Interrupt request to CPU due to RXPR setting 1 Interrupt requests to CPU disabled (Initial value) 540 15.2.13 Interrupt Mask Register (IMR) The interrupt mask register (IMR) is a 16-bit readable/writable register containing flags that enable or disable requests by individual interrupt sources. IMR Bit: 15 IMR7 Initial value: R/W: Bit: 1 R/W 7 -- Initial value: R/W: 1 R 14 IMR6 1 R/W 6 -- 1 R 13 IMR5 1 R/W 5 -- 1 R 12 IMR4 1 R/W 4 IMR12 1 R/W 11 IMR3 1 R/W 3 -- 1 R 10 IMR2 1 R/W 2 -- 1 R 9 IMR1 1 R/W 1 IMR9 1 R/W 8 -- 0 R 0 IMR8 1 R/W Bit 15--Overload Frame/Bus Off Recovery Interrupt Mask (IMR7): Enables or disables overload frame/bus off recovery interrupt requests. Bit 15: IMR7 0 1 Description Overload frame/bus off recovery interrupt request (OVR0) to CPU by IRR7 enabled Overload frame/bus off recovery interrupt request (OVR0) to CPU by IRR7 disabled (Initial value) Bit 14--Bus Off Interrupt Mask (IMR6): Enables or disables bus off interrupt requests caused by the transmit error counter. Bit 14: IMR6 0 1 Description Bus off interrupt request (ERS0) to CPU by IRR6 enabled Bus off interrupt request (ERS0) to CPU by IRR6 disabled (Initial value) Bit 13--Error Passive Interrupt Mask (IMR5): Enables or disables error passive interrupt requests caused by the transmit/receive error counter. Bit 13: IMR5 0 1 Description Error passive interrupt request (ERS0) to CPU by IRR5 enabled Error passive interrupt request (ERS0) to CPU by IRR5 disabled (Initial value) 541 Bit 12--Receive Overload Warning Interrupt Mask (IMR4): Enables or disables error warning interrupt requests caused by the receive error counter. Bit 12: IMR4 0 1 Description REC error warning interrupt request (OVR0) to CPU by IRR4 enabled REC error warning interrupt request (OVR0) to CPU by IRR4 disabled (Initial value) Bit 11--Transmit Overload Warning Interrupt Mask (IMR3): Enables or disables error warning interrupt requests caused by the transmit error counter. Bit 11: IMR3 0 1 Description TEC error warning interrupt request (OVR0) to by IRR3 CPU enabled TEC error warning interrupt request (OVR0) to by IRR3 CPU disabled (Initial value) Bit 10--Remote Frame Request Interrupt Mask (IMR2): Enables or disables remote frame reception interrupt requests. Bit 10: IMR2 0 1 Description Remote frame reception interrupt request (OVR0) to CPU by IRR2 enabled Remote frame reception interrupt request (OVR0) to CPU by IRR2 disabled (Initial value) Bit 9--Receive Message Interrupt Mask (IMR1): Enables or disables message reception interrupt requests. Bit 9: IMR1 0 1 Description Message reception interrupt request (RM1) to CPU by IRR1 enabled Message reception interrupt request (RM1) to CPU by IRR1 disabled (Initial value) Bit 8--Reserved: This bit always reads 0. The write value should always be 0. Bits 7 to 5, 3, and 2--Reserved: These bits always read 1. The write value should always be 1. 542 Bit 4--Bus Operation Interrupt Mask (IMR12): Enables or disables interrupt requests due to bus operation in sleep mode. Bit 4: IMR12 0 1 Description Bus operation interrupt request (OVR0) to CPU by IRR12 enabled Bus operation interrupt request (OVR0) to CPU by IRR12 disabled (Initial value) Bit 1--Unread Interrupt Mask (IMR9): Enables or disables unread receive message overwrite interrupt requests. Bit 1: IMR9 0 1 Description Unread message overwrite interrupt request (OVR0) to CPU by IRR9 enabled Unread message overwrite interrupt request (OVR0) to CPU by IRR9 disabled (Initial value) Bit 0--Mailbox Empty Interrupt Mask (IMR8): Enables or disables mailbox empty interrupt requests. Bit 0: IMR8 0 1 Description Mailbox empty interrupt request (SLE0) to CPU by IRR8 enabled Mailbox empty interrupt request (SLE0) to CPU by IRR8 disabled (Initial value) 15.2.14 Receive Error Counter (REC) The receive error counter (REC) is an 8-bit read-only register that functions as a counter indicating the number of receive message errors on the CAN bus. The count value is stipulated in the CAN protocol. REC Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 543 15.2.15 Transmit Error Counter (TEC) The transmit error counter (TEC) is an 8-bit read-only register that functions as a counter indicating the number of transmit message errors on the CAN bus. The count value is stipulated in the CAN protocol. TEC Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 15.2.16 Unread Message Status Register (UMSR) The unread message status register (UMSR) is a 16-bit readable/writable register containing status flags that indicate, for individual mailboxes (buffers), that a received message has been overwritten by a new receive message before being read. When a message is overwritten by a new receive message, the old data is lost. UMSR Bit: 15 UMSR7 14 UMSR6 13 UMSR5 12 UMSR4 11 UMSR3 10 UMSR2 9 UMSR1 8 UMSR0 Initial value: R/W: Bit: 0 R/(W)* 7 0 R/(W)* 6 0 R/(W)* 5 0 R/(W)* 4 0 R/(W)* 3 0 R/(W)* 2 0 R/(W)* 1 UMSR9 0 R/(W)* 0 UMSR8 UMSR15 UMSR14 UMSR13 UMSR12 UMSR11 UMSR10 Initial value: R/W: 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* Note: * Can only be written with 1 for flag clearing. Bits 15 to 0--Unread Message Status Flags (UMSR7 to UMSR0, UMSR15 to UMSR8): Status flags indicating that an unread receive message has been overwritten. 544 Bit x: UMSRx 0 1 Description [Clearing condition] Writing 1 Unread receive message is overwritten by a new message [Setting condition] When a new message is received before RXPR is cleared x = 0 to 15 (Initial value) 15.2.17 Local Acceptance Filter Masks (LAFML, LAFMH) The local acceptance filter masks (LAFML, LAFMH) are 16-bit readable/writable registers that filter receive messages to be stored in the receive-only mailbox (MC0, MD0) according to the identifier. In these registers, consist of LAFMH15 (MSB) to LAFMH5 (LSB) are 11 standard/extended identifier bits, and LAFMH1 (MSB) to LAFML0 (LSB) are 18 extended identifier bits. LAFML Bit: 15 LAFML7 14 LAFML6 13 LAFML5 12 LAFML4 11 LAFML3 10 LAFML2 9 LAFML1 8 LAFML0 Initial value: R/W: Bit: 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 LAFML9 0 R/W 0 LAFML8 LAFML15 LAFML14 LAFML13 LAFML12 LAFML11 LAFML10 Initial value: R/W: LAFMH Bit: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 15 LAFMH7 14 13 12 -- 0 R 4 11 -- 0 R 3 10 -- 0 R 2 9 8 LAFMH6 LAFMH5 LAFMH1 LAFMH0 Initial value: R/W: Bit: 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 1 0 R/W 0 LAFMH15 LAFMH14 LAFMH13 LAFMH12 LAFMH11 LAFMH10 LAFMH9 LAFMH8 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 545 LAFMH Bits 7 to 0 and 15 to 13--11-Bit Identifier Filter (LAFMH7 to LAFMH5, LAFMH15 to LAFMH8): Filter mask bits for the first 11 bits of the receive message identifier (for both standard and extended identifiers). Bit x: LAFMHx 0 1 Description Stored in MC0, MD0 (receive-only mailbox) depending on bit match between MC0 message identifier and receive message identifier (Initial value) Stored in MC0, MD0 (receive-only mailbox) regardless of bit match between MC0 message identifier and receive message identifier LAFMH Bits 12 to 10--Reserved: These bits always read 0. The write value should always be 0. LAFMH Bits 9 and 8, LAFML Bits 15 to 0--18-Bit Identifier Filter (LAFMH1, LAFMH0, LAFML7 to LAFML0, LAFML15 to LAFML8): Filter mask bits for the 18 bits of the receive message identifier (extended). Bit x: LAFMHx LAFMLx 0 1 Description Stored in MC0 (receive-only mailbox) depending on bit match between MC0 message identifier and receive message identifier (Initial value) Stored in MC0 (receive-only mailbox) regardless of bit match between MC0 message identifier and receive message identifier 546 15.2.18 Message Control (MC0 to MC15) The message control register sets (MC0 to MC15) consist of eight 8-bit readable/writable registers (MCx[1] to MCx[8]). The HCAN has 16 sets of these registers (MC0 to MC15). The initial value of these registers is undefined, so they must be initialized (by writing 0 or 1). MCx [1] Bit: 7 -- Initial value: R/W: MCx [2] Bit: 7 -- Initial value: R/W: MCx [3] Bit: 7 -- Initial value: R/W: MCx [4] Bit: 7 -- Initial value: R/W: MCx [5] Bit: 7 6 5 4 RTR 6 -- * R/W 5 -- * R/W 4 -- * R/W 3 DLC3 * R/W 2 DLC2 * R/W 1 DLC1 * R/W 0 DLC0 * R/W * R/W 6 -- * R/W 5 -- * R/W 4 -- * R/W 3 -- * R/W 2 -- * R/W 1 -- * R/W 0 -- * R/W * R/W 6 -- * R/W 5 -- * R/W 4 -- * R/W 3 -- * R/W 2 -- * R/W 1 -- * R/W 0 -- * R/W * R/W 6 -- * R/W 5 -- * R/W 4 -- * R/W 3 -- * R/W 2 -- * R/W 1 -- * R/W 0 -- * R/W * R/W 3 IDE 2 -- * R/W 1 0 STD_ID2 STD_ID1 STD_ID0 EXD_ID17 EXD_ID16 Initial value: R/W: * R/W * R/W * R/W * R/W * R/W * R/W * R/W 547 MCx [6] Bit: 7 6 5 4 3 2 1 0 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 Initial value: R/W: MCx [7] Bit: * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W 7 6 5 4 3 2 1 0 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 Initial value: R/W: MCx [8] Bit: * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W 7 6 5 4 3 2 1 0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Initial value: R/W: * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W *:Undefined x = 0 to 15 MCx[1] Bits 7 to 4--Reserved: The initial value of these bits is undefined; they must be initialized (by writing 0 or 1). MCx[1] Bits 3 to 0--Data Length Code (DLC): These bits indicate the required length of data frames and remote frames. Bit 3: DLC3 0 Bit 2: DLC2 0 Bit 1: DLC1 0 Bit 0: DLC0 0 1 1 0 1 1 0 0 1 1 0 1 1 0/1 0/1 0/1 Description Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes Data length = 8 bytes 548 MCx[2] Bits 7 to 0--Reserved: The initial value of these bits is undefined; they must be initialized (by writing 0 or 1). MCx[3] Bits 7 to 0--Reserved: The initial value of these bits is undefined; they must be initialized (by writing 0 or 1). MCx[4] Bits 7 to 0--Reserved: The initial value of these bits is undefined; they must be initialized (by writing 0 or 1). MCx[6] Bits 7 to 0--Standard Identifier (STD_ID10 to STD_ID3): MCx[5] Bits 7 to 5--Standard Identifier (STD_ID2 to STD_ID0): These bits set the identifier (standard identifier) of data frames and remote frames. Standard identifier SOF ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR IDE SRR STD_IDxx Figure 15-2 Standard Identifier MCx[5] Bit 4--Remote Transmission Request (RTR): Used to distinguish between data frames and remote frames. Bit 4: RTR 0 1 Description Data frame Remote frame MCx[5] Bit 3--Identifier Extension (IDE): Used to distinguish between the standard format and extended format of data frames and remote frames. Bit 3: IDE 0 1 Description Standard format Extended format MCx[5] Bit 2--Reserved: The initial value of this bit is undefined; it must be initialized (by writing 0 or 1). 549 MCx[5] Bits 1 and 0--Extended Identifier (EXD_ID17, EXD_ID16): MCx[8] Bits 7 to 0--Extended Identifier (EXD_ID15 to EXD_ID8): MCx[7] Bits 7 to 0--Extended Identifier (EXD_ID7 to EXD_ID0): These bits set the identifier (extended identifier) of data frames and remote frames. Extended Identifier IDE ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 EXD_IDxx ID4 ID3 ID2 ID1 ID0 RTR R1 EXD_IDxx Figure 15-3 Extended Identifier 550 15.2.19 Message Data (MD0 to MD15) The message data register sets (MD0 to MD15) consist of eight 8-bit readable/writable registers (MDx[1] to MDx[8]). The HCAN has 16 sets of these registers (MD0 to MD15). The initial value of these registers is undefined, so they must be initialized (by writing 0 or 1). MDx [1] Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: MDx [2] Bit: * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W 7 6 5 4 3 2 1 0 Initial value: R/W: MDx [3] Bit: * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W 7 6 5 4 3 2 1 0 Initial value: R/W: MDx [4] Bit: * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W 7 6 5 4 3 2 1 0 Initial value: R/W: MDx [5] Bit: * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W 7 6 5 4 3 2 1 0 Initial value: R/W: * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W 551 MDx [6] Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: MDx [7] Bit: * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W 7 6 5 4 3 2 1 0 Initial value: R/W: MDx [8] Bit: * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W 7 6 5 4 3 2 1 0 Initial value: R/W: * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W *:Undefined x = 0 to 15 552 15.2.20 Module Stop Control Register C (MSTPCRC) Bit: 7 6 5 4 3 2 1 0 MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 Initial value: R/W: 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W MSTPCRC is an 8-bit readable/writable register that performs module stop mode control. When the MSTPC3 bit is set to 1, HCAN operation is stopped at the end of the bus cycle, and module stop mode is entered. Register read/write accesses are not possible in module stop mode. For details, see sections 21A.5, 21B.5, Module Stop Mode. MSTPCRC is initialized to H'FF by a reset, and in hardware standby mode. It is not initialized in software standby mode. Bit 3--Module Stop (MSTPC3): Specifies the HCAN module stop mode. Bit 3: MSTPC3 0 1 Description HCAN module stop mode is cleared HCAN module stop mode is set (Initial value) 553 15.3 15.3.1 Operation Hardware and Software Resets The HCAN can be reset by a hardware reset or software reset. Hardware Reset (HCAN Module Stop, Reset*, Hardware*/Software Standby): Initialization is performed by automatic setting of the MCR reset request bit (MCR0) in MCR and the reset state bit (GSR3) in GSR within the HCAN (hardware reset). At the same time, all internal registers are initialized. However mailbox contents are retained. A flowchart of this reset is shown in figure 15-4. Note: * In a reset and in hardware standby mode, the module stop bit is initialized to 1 and the HCAN enters the module stop state. Software Reset (Write to MCR0): In normal operation initialization is performed by setting the MCR reset request bit (MCR0) in MCR (Software reset). With this kind of reset, if the CAN controller is performing a communication operation (transmission or reception), the initialization state is not entered until the message has been completed. During initialization, the reset state bit (GSR3) in GSR is set. In this kind of initialization, the error counters (TEC and REC) are initialized but other registers and RAM (mailboxes) are not. A flowchart of this reset is shown in figure 15-5. 554 Hardware reset MCR0 = 1 (automatic) IRR0 = 1 (automatic)*1 GSR3 = 1 (automatic) Initialization of HCAN module Bit configuration mode Period in which BCR, MBCR, etc., are initialized Clear IRR0 BCR setting MBCR setting Mailbox (RAM) initialization Message transmission method initialization MCR0 = 0 GSR3 = 0? Yes IMR setting (interrupt mask setting) MBIMR setting (interrupt mask setting) MC[x] setting (receive identifier setting) LAFM setting (receive identifier mask setting) No GSR3 = 0 & 11 recessive bits received? Yes CAN bus communication enabled No : Settings by user : Processing by hardware Notes: *1 When IRR0 is set to 1 (automatically) due to a hardware reset*2, a "hardware reset initiated reset processing" interrupt is generated. *2 In a reset and in hardware standby mode, the module stop bit is initialized to 1 and the HCAN enters the module stop state. Figure 15-4 Hardware Reset Flowchart 555 MCR0 = 1 Bus idle? Yes GSR3 = 1 (automatic) No Initialization of REC and TEC only BCR setting MBCR setting Mailbox (RAM) initialization Message transmission method initialization OK? Yes MCR0 = 0 Correction No GSR3 = 0? Yes No IMR setting MBIMR setting MC[x] setting LAFM setting OK? Yes Correction No GSR3 = 0 & 11 recessive bits received? Yes CAN bus communication enabled No : Settings by user : Processing by hardware Figure 15-5 Software Reset Flowchart 556 15.3.2 Initialization after Hardware Reset After a hardware reset, the following initialization processing should be carried out: * * * * * Clearing of IRR0 bit in interrupt register (IRR) Bit rate setting Mailbox transmit/receive settings Mailbox (RAM) initialization Message transmission method setting These initial settings must be made while the HCAN is in bit configuration mode. Configuration mode is a state in which the reset request bit (MCR0) in the master control register (MCR) is 1 and the reset status bit in the general status register (GSR) is also 1 (GSR3 = 1). Configuration mode is exited by clearing the reset request bit in MCR to 0; when MCR0 is cleared to 0, the HCAN automatically clears the reset state bit (GSR3) in the general status register (GSR). The power-up sequence then begins, and communication with the CAN bus is possible as soon as the sequence ends. The power-up sequence consists of the detection of 11 consecutive recessive bits. IRR0 Clearing: The reset interrupt flag (IRR0) is always set after a reset or recovery from software standby mode. As an HCAN interrupt is initiated immediately when interrupts are enabled, IRR0 should be cleared. Bit Rate and Bit Timing Settings: As bit rate settings, a baud rate setting and bit timing setting must be made each time a CAN node begins communication. The baud rate and bit timing settings are made in the bit configuration register (BCR). a. Note BCR can be written to at all times, but should only be modified in configuration mode. Settings should be made so that all CAN controllers connected to the CAN bus have the same baud rate and bit width. Refer to table 15-3 for the range of values that can be used as settings (TSEG1, TSEG2, BRP, sample point, and SJW) for BCR. 557 Table 15-3 BCR Register Value Setting Ranges Name Time segment 1 Time segment 2 Baud rate prescaler Sample point Re-synchronization jump width Abbreviation TSEG1 TSEG2 BRP SAM SJW Min. Value B'0000 B'000 B'000000 B'0 B'00 Max. Value B'1111 B'111 B'111111 B'1 B'11 b. Value Setting Ranges * The bit width consists of the total of the settable Time Quanta (TQ). TQ (number of system clocks) is determined by the baud rate prescaler (BRP). TQ = 2 x (BRP + 1) fCLK * The value of SJW is stipulated in the CAN specifications. 3 SJW 0 * The minimum value of TSEG1 is stipulated in the CAN specifications. TSEG1 > TSEG2 * The minimum value of TSEG2 is stipulated in the CAN specifications. TSEG2 SJW The following formula is used to calculate the baud rate. Bit rate [b/s] = fCLK 2 x (BRP + 1) x (3 + TSEG1 + TSEG2) Note: f CLK = (system clock) The BCR values are used for BRP, TSEG1, and TSEG2. Example: With a 1 Mb/s baud rate and a 20 MHz input clock: 1 Mb/s = 20 MHz 2 x (0 + 1) x (3 + 4 + 3) 558 Item f CLK BRP TSEG1 TSEG2 Set Values 20 MHz 0 (B'000000) 4 (B'0100) 3 (B'011) Actual Values -- System clock x 2 5TQ 4TQ 1-bit time 1-bit time (8-25 time quanta) SYNC_SEG PRSEG PHSEG1 PHSEG2 TSEG2 (time segment 2)* Quantum 2-8 1 Legend TSEG1 (time segment 1)* 2-16 SYNC_SEG: Segment for establishing synchronization of nodes on the CAN bus. (Normal bit edge transitions occur in this segment.) PRSEG: Segment for compensating for physical delay between networks. PHSEG1: Buffer segment for correcting phase drift (positive). (This segment is extended when synchronization (resynchronization) is established.) PHSEG2: Buffer segment for correcting phase drift (negative). (This segment is shortened when synchronization (resynchronization) is established.) Note: * The Time Quanta value for TSEG1 and TSEG2 is the TSEG value + 1. Figure 15-6 Detailed Description of One Bit HCAN bit rate calculation: Bit rate = fCLK 2 x (BRP + 1) x (3 + TSEG1 + TSEG2) Note: f CLK = o (system clock) The BCR values are used for BRP, TSEG1, and TSEG2. BCR Setting Constraints TSEG1 > TSEG2 SJW (SJW = 0 to 3) TSEG2 > B'001 (BRP = B'000000) TSEG2 > B'000 (BRP > B'000000) These constraints allow the setting range shown in table 15-3 for TSEG1 and TSEG2 in BCR. 559 Table 15-4 Setting Range for TSEG1 and TSEG2 in BCR TSEG2 (BCR [14:12]) 001 TSEG1 (BCR [11:8]) 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 No Yes* Yes* Yes* Yes* Yes* Yes* Yes* Yes* Yes* Yes* Yes* Yes* 010 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 011 No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 100 No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 101 No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 110 No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes 111 No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Notes: The time quanta value for TSEG1 and TSEG2 is the TSEG value + 1. * Setting is enabled except when BRP [13:8] = B'000000. Mailbox Transmit/Receive Settings: HCAN0, 1 each have 16 mailboxes. Mailbox 0 is receiveonly, while mailboxes 1 to 15 can be set for transmission or reception. Mailboxes that can be set for transmission or reception must be designated either for transmission use or for reception use before communication begins. The Initial status of mailboxes 1 to 15 is for transmission (while mailbox 0 is for reception only). Mailbox transmit/receive settings are not initialized by a software reset. * Setting for transmission Transmit mailbox setting (mailboxes 1 to 15) Clearing a bit to 0 in the mailbox configuration register (MBCR) designates the corresponding mailbox for transmission use. After a reset, mailboxes are initialized for transmission use, so this setting is not necessary. * Setting for reception Transmit/receive mailbox setting (mailboxes 1 to 15) Setting a bit to 1 in the mailbox configuration register (MBCR) designates the corresponding mailbox for reception use. When setting mailboxes for reception, to improve message transmission efficiency, high-priority messages should be set in low-to-high mailbox order (priority order: mailbox 1 (MCx[1]) > mailbox 15 (MCx[15]). 560 * Receive-only mailbox (mailbox 0) No setting is necessary, as this mailbox is always used for reception. Mailbox (Message Control/Data (MCx[x], MDx[x]) Initial Settings: After power is supplied, all registers and RAM (message control/data, control registers, status registers, etc.) are initialized. Message control/data (MCx[x], MDx[x]) only are in RAM, and so their values are undefined. Initial values must therefore be set in all the mailboxes (by writing 0s or 1s). Setting the Message Transmission Method: Either of the following message transmission methods can be selected with the message transmission method bit (MCR2) in the master control register (MCR): a. Transmission order determined by message identifier priority b. Transmission order determined by mailbox number priority When a is selected, if a number of messages are designated as waiting for transmission (TXPR = 1), the message with the highest priority set in the message identifier (MCx[5]-MCx[8]) is stored in the transmit buffer. CAN bus arbitration is then carried out for the message in the transmit buffer, and message transmission is performed when the transmission right is acquired. When the TXPR bit is set, internal arbitration is performed again, and the highest-priority message is found and stored in the transmit buffer. When b is selected, if a number of messages are designated as waiting for transmission (TXPR = 1), messages are stored in the transmit buffer in low-to-high mailbox order (priority order: mailbox 1 > mailbox 15). CAN bus arbitration is then carried out for the messages in the transmit buffer, and message transmission is performed when the bus is acquired. 15.3.3 Transmit Mode Message transmission is performed using mailboxes 1 to 15. The transmission procedure is described below, and a transmission flowchart is shown in figure 15-7. Initialization (after hardware reset only) a. b. c. d. e. Clearing of IRR0 bit in interrupt register (IRR) Bit rate settings Mailbox transmit/receive settings Mailbox initialization Message transmission method setting 561 Interrupt and transmit data settings a. b. c. d. CPU interrupt source setting Arbitration field setting Control field setting Data field setting Message transmission and interrupts a. b. c. d. Message transmission wait Message transmission completion and interrupt Message transmission abort Message retransmission 562 Initialization (After Hardware Reset Only): These settings should be made while the HCAN is in bit configuration mode. * IRR0 clearing The reset interrupt flag (IRR0) is always set after a reset or recovery from software standby mode. As an HCAN interrupt is initiated immediately when interrupts are enabled, IRR0 should be cleared. * Bit rate settings Set values relating to the CAN bus communication speed and resynchronization. Refer to Bit Rate and Bit Timing Settings in 15.3.2, Initialization after Hardware Reset, for details. * Mailbox transmit/receive settings Mailbox transmit/receive settings should be made in advance. A total of 15 mailboxes can be set for transmission or reception (mailboxes 1 to 15). To set a mailbox for transmission, clear the corresponding bit to 0 in the mailbox configuration register (MBCR). Refer to Mailbox transmit/receive settings in 15.3.2, Initialization after Hardware Reset, for details. * Mailbox initialization As message control/data registers (MCx[x], MDx[x]) are configured in RAM, their initial values after powering on are undefined, and so bit initialization is necessary. Write 0s or 1s to the mailboxes. See Mailbox (Message Control/Data (MCx[x], MDx[x]) Initial Setting in 15.3.2, Initialization after a Hardware Reset, for details. * Message transmission method setting Set the transmission method for mailboxes designated for transmission. The following two transmission methods can be used. Refer to Message transmission method settings in 15.3.2, Initialization after Hardware Reset, for details. a. Transmission order determined by message identifier priority b. Transmission order determined by mailbox number priority 563 Initialization (after hardware reset only) IRR0 clearing BCR setting MBCR setting Mailbox initialization Message transmission method setting Interrupt settings Transmit data setting Arbitration field setting Control field setting Data field setting Message transmission wait TXPR setting Bus idle? Yes Message transmission GSR2 = 0 (during transmission only) No Transmission completed? Yes TXACK = 1 IRR8 = 1 No IMR8 = 1? No Interrupt to CPU Yes Clear TXACK Clear IRR8 : Settings by user End of transmission : Processing by hardware Figure 15-7 Transmission Flowchart 564 Interrupt and Transmit Data Settings: When mailbox initialization is finished, CPU interrupt source settings and data settings must be made. Interrupt source settings are made in the mailbox interrupt register (MBIMR) and interrupt mask register (IMR), while transmit data settings are made by writing the necessary data from the arbitration field, control field, and data field, described below, in the corresponding message control (MCx[1]-MCx[8]) and message data (MDx[1]-MDx[8]). * CPU interrupt source settings Transmission acknowledge and transmission abort acknowledge interrupts can be masked for individual mailboxes in the mailbox interrupt mask register (MBIMR). Interrupt register (IRR) interrupts can be masked in the interrupt mask register (IMR). * Arbitration field setting In the arbitration field, the 11-bit identifier (STD_ID0-STD_ID10) and RTR bit (standard format) or 29-bit identifier (STD_ID0-STD_ID10, EXT_ID0-EXT_ID17) and IDE.RTR bit (extended format) are set. The registers to be set are MCx[5]-MCx[8]. * Control field setting In the control field, the byte length of the data to be transmitted is set in DLC0-DLC3. The register to be set is MCx[1]. * Data field setting In the data field, the data to be transmitted is set in byte units in the range of 0 to 8 bytes. The registers to be set are MDx[1]-MDx[8]. The number of bytes in the data actually transmitted depends on the data length code (DLC) in the control field. If a value exceeding the value set in DLC is set in the data field, only the number of bytes set in DLC will actually be transmitted. Message Transmission and Interrupts: * Message transmission wait If message transmission is to be performed after completion of the message control (MCx[1]- MCx[8]) and message data (MDx[1]-MDx[8]) settings, transmission is started by setting the corresponding mailbox transmit wait bit (TXPR1-TXPR15) to 1 in the transmit wait register (TXPR). The following two transmission methods can be used: a. Transmission order determined by message identifier priority b. Transmission order determined by mailbox number priority When a is selected, if a number of messages are designated as waiting for transmission (TXPR = 1), messages are stored in the transmit buffer in low-to-high mailbox order (priority order: mailbox 1 > mailbox 15). CAN bus arbitration is then carried out for the messages in the transmit buffer, and message transmission is performed when the bus is acquired. 565 When b is selected, if a number of messages are designated as waiting for transmission (TXPR = 1), the message with the highest priority set in the message identifier (MCx[5]-MCx[8]) is stored in the transmit buffer. CAN bus arbitration is then carried out for the message in the transmit buffer, and message transmission is performed when the transmission right is acquired. When the TXPR bit is set, internal arbitration is performed again, the highest-priority message is found and stored in the transmit buffer, CAN bus arbitration is carried out in the same way, and message transmission is performed when the transmission right is acquired. * Message transmission completion and interrupt When a message is transmitted error-free using the above procedure, the corresponding acknowledge bit (TXACK1-TXACK15) in the transmit acknowledge register (TXACK) and transmit wait bit (TXPR1-TXPR15) in the transmit wait register (TXPR) are automatically initialized. Also, if the corresponding bit (MBIMR1-MBIMR15) in the mailbox interrupt mask register (MBIMR) and the mailbox empty interrupt bit (IRR8) in the interrupt mask register (IMR) are set to the interrupt enable state at the same time, an interrupt can be sent to the CPU. * Message transmission cancellation Transmission cancellation can be specified for a message stored in a mailbox as a transmit wait message. A transmit wait message is canceled by setting the bit for the corresponding mailbox (TXCR1-TXCR15) to 1 in the transmit cancel register (TXCR). When cancellation is executed, the transmit wait register (TXPR) is automatically reset, and the corresponding bit is set to 1 in the abort acknowledge register (ABACK). An interrupt to the CPU can be requested. Also, if the mailbox empty interrupt (IRR8) is enabled for the bits (MBIMR1-MBIMR15) corresponding to the mailbox interrupt mask register (MBIMR) and interrupt mask register (IMR), interrupts may be sent to the CPU. However, a transmit wait message cannot be canceled at the following times: a. During internal arbitration or CAN bus arbitration b. During data frame or remote frame transmission Also, transmission cannot be canceled by clearing the transmit wait register (TXPR). Figure 15-8 shows a flowchart of transmit message cancellation. * Message retransmission If transmission of a transmit message is aborted in the following cases, the message is retransmitted automatically: a. CAN bus arbitration failure (failure to acquire the bus) b. Error during transmission (bit error, stuff error, CRC error, frame error, ACK error) 566 Message transmit wait TXPR setting Set TXCR bit corresponding to message to be canceled Cancellation possible? Yes Message not sent Clear TXCR, TXPR ABACK = 1 IRR8 = 1 No Completion of message transmission TXACK = 1 Clear TXCR, TXPR IRR8 = 1 IMR8 = 1? No Interrupt to CPU Yes Clear TXACK Clear ABACK Clear IRR8 : Settings by user End of transmission/transmission cancellation : Processing by hardware Figure 15-8 Transmit Message Cancellation Flowchart 567 15.3.4 Receive Mode Message reception is performed using mailboxes 0 and 1 to 15. The reception procedure is described below, and a reception flowchart is shown in figure 15-9. Initialization (after hardware reset only) a. b. c. d. Clearing of IRR0 bit in interrupt register (IRR) Bit rate settings Mailbox transmit/receive settings Mailbox (RAM) initialization Interrupt and receive message settings a. CPU interrupt source setting b. Arbitration field setting c. Local acceptance filter mask (LAFM) settings Message reception and interrupts a. Message reception CRC check b. Data frame reception c. Remote frame reception d. Unread message reception Initialization (After Hardware Reset Only): These settings should be made while the HCAN is in bit configuration mode. * IRR0 clearing The reset interrupt flag (IRR0) is always set after a reset or recovery from software standby mode. As an HCAN interrupt is initiated immediately when interrupts are enabled, IRR0 should be cleared. * Bit rate settings Set values relating to the CAN bus communication speed and resynchronization. Refer to Bit Rate and Bit Timing Setting in 15.3.2, Initialization after Hardware Reset, for details. * Mailbox transmit/receive settings Each channel has one receive-only mailbox (mailbox 0) plus 15 mailboxes that can be set for reception. Thus a total of 16 mailboxes can be used for reception. To set a mailbox for reception, set the corresponding bit to 1 in the mailbox configuration register (MBCR). The initial setting for mailboxes is 0, designating transmission use. Refer to Mailbox transmit/receive settings in 15.3.2, Initialization after Hardware Reset, for details. 568 * Mailbox (RAM) initialization As message control/data registers (MCx[x], MDx[x]) are configured in RAM, their initial values after powering on are undefined, and so bit initialization is necessary. Write 0s or 1s to the mailboxes. See Mailbox (Message Control/Data (MCx[x], MDx[x]) Initial Setting in 15.3.2, Initialization after a Hardware Reset, for details. 569 Initialization IRR0 clearing BCR setting MBCR setting Mailbox (RAM) initialization Interrupt settings : Settings by user : Processing by hardware Receive data setting Arbitration field setting Local acceptance filter settings Message reception (Match of identifier in mailbox?) Yes Same RXPR = 1? No Data frame? Yes RXPR IRR1 = 1 No Yes Unread message No RXPR, RFPR = 1 IRR2 = 1, IRR1 = 1 Yes Yes IMR1 = 1? No Interrupt to CPU IMR2 = 1? No Interrupt to CPU Message control read Message data read Message control read Message data read Clear all RXPRn bits of mailbox for which receive interrupt requests are enabled by MBIMR Clear all RXPRn bits of mailbox for which receive interrupt requests are enabled by MBIMR IRR1 = 0 IRR2 = 0, IRR1 = 0 Transmission of data frame corresponding to remote frame End of reception Figure 15-9 Reception Flowchart 570 Interrupt and Receive Message Settings: When mailbox initialization is finished, CPU interrupt source settings and receive message specifications must be made. Interrupt source settings are made in the mailbox interrupt register (MBIMR) and interrupt mask register (IMR). To receive a message, the identifier must be set in advance in the message control (MCx[1]-MCx[8]) for the receiving mailbox. When a message is received, all the bits in the receive message identifier are compared, and if a 100% match is found, the message is stored in the matching mailbox. Mailbox 0 (MC0[x], MD0[x]) has a local acceptance filter mask (LAFM) that allows Don't care settings to be made. * CPU interrupt source settings When transmitting, transmission acknowledge and transmission abort acknowledge interrupts can be masked for individual mailboxes in the mailbox interrupt mask register (MBIMR). When receiving, data frame and remote frame receive wait interrupts can be masked. Interrupt register (IRR) interrupts can be masked in the interrupt mask register (IMR). * Arbitration field setting In the arbitration field, the identifier (STD_ID0-STD_ID10, EXT_ID0-EXT_ID17) of the message to be received is set. If all the bits in the set identifier do not match, the message is not stored in a mailbox. Example: Mailbox 1 010_1010_1010 (standard identifier) Only one kind of message identifier can be received by MB1 Identifier 1: 010_1010_1010 * Local acceptance filter mask (LAFM) setting The local acceptance filter mask is provided for mailbox 0 (MC0[x], MD0[x]) only, enabling a Don't care specification to be made for all bits in the received identifier. This allows various kinds of messages to be received. Example: Mailbox 0 LAFM 010_1010_1010 (standard identifier) 000_0000_0011 (0: Care, 1: Don't care) A total of four kinds of message identifiers can be received by MB0 Identifier 1: 010_1010_1000 Identifier 2: 010_1010_1001 Identifier 3: 010_1010_1010 Identifier 4: 010_1010_1011 571 Message Reception and Interrupts: * Message reception CRC check When a message is received, a CRC check is performed automatically (by hardware). If the result of the CRC check is normal, ACK is transmitted in the ACK field irrespective of whether or not the message can be received. * Data frame reception If the received message is confirmed to be error-free by the CRC check, etc., the identifier in the mailbox (and also LAFM in the case of mailbox 0 only) and the identifier of the receive message are compared, and if a complete match is found, the message is stored in the mailbox. The message identifier comparison is carried out on each mailbox in turn, starting with mailbox 0 and ending with mailbox 15. If a complete match is found, the comparison ends at that point, the message is stored in the matching mailbox, and the corresponding receive complete bit (RXPR0-RXPR15) is set in the receive complete register (RXPR). However, when a mailbox 0 LAFM comparison is carried out, even if the identifier matches, the mailbox comparison sequence does not end at that point, but continues with mailbox 1 and then the remaining mailboxes. It is therefore possible for a message matching mailbox 0 to be received by another mailbox (however, the same message cannot be stored in more than one of mailboxes 1 to 15). If the corresponding bit (MBIMR0-MBIMR15) in the mailbox interrupt mask register (MBIMR) and the receive message interrupt mask (IMR1) in the interrupt mask register (IMR) are set to the interrupt enable value at this time, an interrupt can be sent to the CPU. * Remote frame reception Two kinds of messages--data frames and remote frames--can be stored in mailboxes. A remote frame differs from a data frame in that the remote reception request bit (RTR) in the message control register (MC[x]5) and the data field are 0 bytes. The data length to be returned in a data frame must be stored in the data length code (DLC) in the control field. When a remote frame (RTR = recessive) is received, the corresponding bit is set in the remote request wait register (RFPR). If the corresponding bit (MBIMR0-MBIMR15) in the mailbox interrupt mask register (MBIMR) and the remote frame request interrupt mask (IRR2) in the interrupt mask register (IMR) are set to the interrupt enable value at this time, an interrupt can be sent to the CPU. * Unread message reception When the identifier in a mailbox matches a receive message, the message is stored in the mailbox. If a message overwrite occurs before the CPU reads the message, the corresponding bit (UMSR0-UMSR15) is set in the unread message register (UMSR). In overwriting of an unread message, when a new message is received before the corresponding bit in the receive complete register (RXPR) has been cleared, the unread message register (UMSR) is set. If the unread interrupt flag (IRR9) in the interrupt mask register (IMR) is set to the interrupt enable 572 value at this time, an interrupt can be sent to the CPU. Figure 15-10 shows a flowchart of unread message overwriting. Unread message overwrite UMSR = 1 IRR9 = 1 IMR9 = 1? No Interrupt to CPU Yes Clear IRR9 Message control/message data read : Settings by user End : Processing by hardware Figure 15-10 Unread Message Overwrite Flowchart 573 15.3.5 HCAN Sleep Mode The HCAN is provided with an HCAN sleep mode that places the HCAN module in the sleep state to reduce current dissipation. Figure 15-11 shows a flowchart of the HCAN sleep mode. MCR5 = 1 Bus idle? Yes Initialize TEC and REC No Bus operation? No Yes IRR12 = 1 IMR12 = 1? Yes No CPU interrupt Sleep mode clearing method MCR7 = 0? Yes (manual) MCR5 = 0 No (automatic) Clear sleep mode? Yes MCR5=0 No 11 recessive bits? Yes CAN bus communication possible No : Settings by user : Processing by hardware Figure 15-11 HCAN Sleep Mode Flowchart 574 HCAN sleep mode is entered by setting the HCAN sleep mode bit (MCR5) to 1 in the master control register (MCR). If the CAN bus is operating, the transition to HCAN sleep mode is delayed until the bus becomes idle. Either of the following methods of clearing HCAN sleep mode can be selected by making a setting in the MCR7 bit. 1. Clearing by software 2. Clearing by CAN bus operation Eleven recessive bits must be received after HCAN sleep mode is cleared before CAN bus communication is enabled again. Clearing by software: HCAN sleep mode is cleared by writing a 0 to MCR5 from the CPU. Clearing by CAN bus operation: Clearing by CAN bus operation occurs automatically when the CAN bus performs an operation and this change is detected. In this case, the first message is not received in the mailbox, and normal reception starts from the next message. When a change is detected on the CAN bus in HCAN sleep mode, the bus operation interrupt flag (IRR12) is set in the interrupt register (IRR). If the bus interrupt mask (IMR12) in the interrupt mask register (IMR) is set to the interrupt enable value at this time, an interrupt can be sent to the CPU. 575 15.3.6 HCAN Halt Mode The HCAN halt mode is provided to enable mailbox settings to be changed without performing an HCAN hardware or software reset. Figure 15-12 shows a flowchart of the HCAN halt mode. MCR1 = 1 Bus idle? Yes MBCR setting No MCR1 = 0 : Settings by user CAN bus communication possible : Processing by hardware Figure 15-12 HCAN Halt Mode Flowchart HCAN halt mode is entered by setting the halt request bit (MCR1) to 1 in the master control register (MCR). If the CAN bus is operating, the transition to HCAN halt mode is delayed until the bus becomes idle. HCAN halt mode is cleared by clearing MCR1 to 0. 15.3.7 Interrupt Interface There are 12 HCAN interrupt sources, to which five independent interrupt vectors are assigned. Table 15-5 lists the HCAN interrupt sources. With the exception of the reset processing vector (IRR0), these sources can be masked. Masking is implemented using the mailbox interrupt mask register (MBIMR) and interrupt mask register (IMR). 576 Table 15-5 HCAN Interrupt Sources IPR Bits IPRM (6-4) Vector ERS0 Vector Number IRR Bit 104 IRR5 IRR6 OVR0 105 IRR0 IRR2 IRR3 IRR4 IRR7 Description Error passive interrupt (TEC 128 or REC 128) Bus off interrupt (TEC 256) Hardware reset processing interrupt Remote frame reception interrupt Error warning interrupt (TEC 96) Error warning interrupt (REC 96) Overload frame transmission interrupt/bus off recovery interrupt (11 recessive bits x 128 times) Unread message overwrite interrupt HCAN sleep mode CAN bus operation interrupt Mailbox 0 message reception interrupt Mailbox 1-15 message reception interrupt Message transmission/cancellation interrupt IRR9 IRR12 RM0 RM1 IPRM (2-0) SLE0 106 107 108 IRR1 IRR1 IRR8 15.3.8 DTC Interface The DTC can be activated by reception of a message in the HCAN's mailbox 0. When DTC transfer ends after DTC activation has been set, the RXPR0 and RFPR0 flags are acknowledge signal automatically. An interrupt request due to a receive interrupt from the HCAN cannot be sent to the CPU in this case. Figure 15-13 shows a DTC transfer flowchart. 577 DTC initialization DTC enable register setting DTC register information setting Message reception in HCAN's mailbox 0 DTC activation End of DTC transfer? Yes RXPR and RFPR clearing No Transfer counter = 0 or DISEL = 1? Yes Interrupt to CPU No : Settings by user End : Processing by hardware Figure 15-13 DTC Transfer Flowchart 15.4 CAN Bus Interface A bus transceiver IC is necessary to connect the H8S/2626 Series or H8S/2623 Series chip to a CAN bus. A Philips PCA82C250 transceiver IC, or compatible device, is recommended. Figure 15-14 shows a sample connection diagram. 578 H8S/2626 Series or H8S/2623 Series 124 Vcc PCA82C250 RS Vcc CAN bus HRxD HTxD RxD CANH TxD CANL Vref No connection GND 124 Figure 15-14 High-Speed Interface Using PCA82C250 15.5 Usage Notes 1. Reset The HCAN is reset by a reset, and in hardware standby mode and software standby mode. All the registers are initialized in a reset, but mailboxes (message control (MCx[x])/message data (MDx[x]) are not. However, after powering on, mailboxes (message control (MCx[x])/message data (MDx[x]) are initialized, and their values are undefined. Therefore, mailbox initialization must always be carried out after a reset or a transition to hardware standby mode or software standby mode. Also, the reset interrupt flag (IRR0) is always set after reset input or recovery from software standby mode. As this bit cannot be masked in the interrupt mask register (IMR), if HCAN interrupts are set as enabled by the interrupt controller without this flag having been cleared, an HCAN interrupt will be initiated immediately. IRR0 must therefore be cleared during initialization. 2. HCAN sleep mode The bus operation interrupt flag (IRR12) in the interrupt register (IRR) is set by bus operation in HCAN sleep mode. Therefore, this flag is not used by the HCAN to indicate sleep mode release. Also note that the reset status bit (GSR3) in the general status register (GSR) is set in sleep mode. 3. Interrupts When the mailbox interrupt mask register (MBIMR) is set, the interrupt register (IRR8.2.1) is not set by reception completion, transmission completion, or transmission cancellation for the set mailboxes. 579 4. Error counters In the case of error active and error passive, REC and TEC normally count up and down. In the bus off state, 11-bit recessive sequences are counted (REC + 1) using REC. If REC reaches 96 during the count, IRR4 and GSR1 are set, and if REC reaches 128, IRR7 is set. 5. Register access Byte or word access can be used on all HCAN registers. Longword access cannot be used. 6. HCAN medium-speed mode HCAN registers cannot be read or written to in medium-speed mode. 7. Register retention during standby All HCAN registers are initialized in hardware standby mode and software standby mode. 8. Using bit operation instructions Start flags in HCAN are cleared by writing 1 to them; there is no need to use bit operation instructions to clear them. To clear a flag, use the MOV instruction to write a 1 to the bit to be cleared. 9. HTxD pin output in error passive state If the HRxD pin becomes fixed at 1 during message transmission or reception when the HCAN is in the error active state, the HTxD pin will output 0 continuously while in the error passive state. To stop continuous 0 output to the CAN bus, disable the HCAN by means of an error warning interrupt or by setting the HCAN module stop mode through detection of a fixed 1 state by the HxRD pin monitor. 10. Transition to HCAN sleep mode The HCAN stops (transmission/reception stops) when MCR0 is cleared to 0 immediately after an HCAN sleep mode transition effected by setting TXPR of the HCAN to 1 and setting MCR5 to 1. When a transition is made to the HCAN sleep mode by means of the above steps, a 10-cycle wait should be inserted after the TxPR setting. After an HCAN sleep mode transition, release the HCAN sleep mode by clearing MCR5 to 0. 11. Message transmission cancellation (TxCR) If all the following conditions are met when cancellation of a transmission message is performed by means of TxCR of the HCAN, the TxCR or TxPR bit indicating cancellation is not cleared even though internal transmission is canceled. When canceling a message using TxCR, 1 should be written continuously until TxCR or TxPR becomes 0. 12. TxCR in the bus off state If TxPR is set before the HCAN goes to the bus off state, and a transition is made to the bus off state with transmission incomplete, cancellation will be performed even if TxCR is set during the bus off period, and the message will be transmitted after a transition to the error active state. 580 Section 16 A/D Converter 16.1 Overview The H8S/2626 Series and H8S/2623 Series include a successive approximation type 10-bit A/D converter that allows up to sixteen analog input channels to be selected. 16.1.1 Features A/D converter features are listed below. * 10-bit resolution * Sixteen input channels * Settable analog conversion voltage range Conversion of analog voltages with the reference voltage pin (Vref) as the analog reference voltage * High-speed conversion Minimum conversion time: 13.3 s per channel (at 20 MHz operation) * Choice of single mode or scan mode Single mode: Single-channel A/D conversion Scan mode: Continuous A/D conversion on 1 to 4 channels * Four data registers Conversion results are held in a 16-bit data register for each channel * Sample and hold function * Three kinds of conversion start Choice of software or timer conversion start trigger (TPU), or ADTRG pin * A/D conversion end interrupt generation A/D conversion end interrupt (ADI) request can be generated at the end of A/D conversion * Module stop mode can be set As the initial setting, A/D converter operation is halted. Register access is enabled by exiting module stop mode. 581 16.1.2 Block Diagram Figure 16-1 shows a block diagram of the A/D converter. Module data bus Bus interface A D D R A A D D R B A D D R C A D D R D A D C S R A D C R + Multiplexer - Comparator Sample-andhold circuit Control circuit Internal data bus AVCC Vref AVSS 10-bit D/A AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 Successive approximations register o/2 o/4 o/8 o/16 ADI interrupt Conversion start trigger from TPU ADTRG ADCR : A/D control register ADCSR : A/D control/status register ADDRA : A/D data register A ADDRB : A/D data register B ADDRC : A/D data register C ADDRD : A/D data register D Figure 16-1 Block Diagram of A/D Converter 582 16.1.3 Pin Configuration Table 16-1 summarizes the input pins used by the A/D converter. The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter. The Vref pin is the A/D conversion reference voltage pin. The 16 analog input pins are divided into two channel sets and two groups, with analog input pins 0 to 7 (AN0 to AN7) comprising channel set 0, analog input pins 8 to 15 (AN8 to AN15) comprising channel set 1, analog input pins 0 to 3 and 8 to 11 (AN0 to AN3, AN8 to AN11) comprising group 0, and analog input pins 4 to 7 and 12 to 15 (AN4 to AN7, AN12 to AN15) comprising group 1. Table 16-1 A/D Converter Pins Pin Name Analog power supply pin Analog ground pin Reference voltage pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 Analog input pin 8 Analog input pin 9 Analog input pin 10 Analog input pin 11 Analog input pin 12 Analog input pin 13 Analog input pin 14 Analog input pin 15 A/D external trigger input pin Symbol AVCC AVSS Vref AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 ADTRG I/O Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input External trigger input for starting A/D conversion Channel set 1 (CH3 = 1) group 1 analog inputs Channel set 1 (CH3 = 1) group 0 analog inputs Channel set 0 (CH3 = 0) group 1 analog inputs Function Analog block power supply Analog block ground and reference voltage A/D conversion reference voltage Channel set 0 (CH3 = 0) group 0 analog inputs 583 16.1.4 Register Configuration Table 16-2 summarizes the registers of the A/D converter. Table 16-2 A/D Converter Registers Name A/D data register AH A/D data register AL A/D data register BH A/D data register BL A/D data register CH A/D data register CL A/D data register DH A/D data register DL A/D control/status register A/D control register Module stop control register A Abbreviation ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR MSTPCRA R/W R R R R R R R R R/(W)* R/W R/W 2 Initial Value H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'33 H'3F Address* 1 H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF95 H'FF96 H'FF97 H'FF98 H'FF99 H'FDE8 Notes: *1 Lower 16 bits of the address. *2 Bit 7 can only be written with 0 for flag clearing. 584 16.2 16.2.1 Bit Register Descriptions A/D Data Registers A to D (ADDRA to ADDRD) : 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 -- 0 R AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 -- Initial value : R/W : There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of A/D conversion. The 10-bit data resulting from A/D conversion is transferred to the ADDR register for the selected channel and stored there. The upper 8 bits of the converted data are transferred to the upper byte (bits 15 to 8) of ADDR, and the lower 2 bits are transferred to the lower byte (bits 7 and 6) and stored. Bits 5 to 0 are always read as 0. The correspondence between the analog input channels and ADDR registers is shown in table 16-3. ADDR can always be read by the CPU. The upper byte can be read directly, but for the lower byte, data transfer is performed via a temporary register (TEMP). For details, see section 16.3, Interface to Bus Master. The ADDR registers are initialized to H'0000 by a reset, and in standby mode or module stop mode. Table 16-3 Analog Input Channels and Corresponding ADDR Registers Analog Input Channel Channel Set 0 (CH3 = 0) Group 0 AN0 AN1 AN2 AN3 Group 1 AN4 AN5 AN6 AN7 Channel Set 1 (CH3 = 1) Group 0 AN8 AN9 AN10 AN11 Group 1 AN12 AN13 AN14 AN15 A/D Data Register ADDRA ADDRB ADDRC ADDRD 585 16.2.2 Bit A/D Control/Status Register (ADCSR) : 7 ADF 0 R/(W)* 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W 3 CH3 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W Initial value : R/W : Note: * Only 0 can be written to bit 7, to clear this flag. ADCSR is an 8-bit readable/writable register that controls A/D conversion operations. ADCSR is initialized to H'00 by a reset, and in hardware standby mode or module stop mode. Bit 7--A/D End Flag (ADF): Status flag that indicates the end of A/D conversion. Bit 7 ADF 0 Description [Clearing conditions] * * 1 When 0 is written to the ADF flag after reading ADF = 1 When the DTC is activated by an ADI interrupt and ADDR is read (Initial value) [Setting conditions] * * Single mode: When A/D conversion ends Scan mode: When A/D conversion ends on all specified channels Bit 6--A/D Interrupt Enable (ADIE): Selects enabling or disabling of interrupt (ADI) requests at the end of A/D conversion. Bit 6 ADIE 0 1 Description A/D conversion end interrupt (ADI) request disabled A/D conversion end interrupt (ADI) request enabled (Initial value) 586 Bit 5--A/D Start (ADST): Selects starting or stopping on A/D conversion. Holds a value of 1 during A/D conversion. The ADST bit can be set to 1 by software, a timer conversion start trigger, or the A/D external trigger input pin (ADTRG). Bit 5 ADST 0 1 Description * * * A/D conversion stopped (Initial value) Single mode: A/D conversion is started. Cleared to 0 automatically when conversion on the specified channel ends Scan mode: A/D conversion is started. Conversion continues sequentially on the selected channels until ADST is cleared to 0 by software, a reset, or a transition to standby mode or module stop mode. Bit 4--Scan Mode (SCAN): Selects single mode or scan mode as the A/D conversion operating mode. See section 16.4, Operation, for single mode and scan mode operation. Only set the SCAN bit while conversion is stopped (ADST = 0). Bit 4 SCAN 0 1 Description Single mode Scan mode (Initial value) Bit 3--Channel Select 3 (CH3): Switches the analog input pins assigned to group 0 or group 1. Setting CH3 to 1 enables AN8 to AN15 to be used instead of AN0 to AN7. Bit 3 CH3 0 1 Description AN8 to AN11 are group 0 analog input pins, AN12 to AN15 are group 1 analog input pins AN0 to AN3 are group 0 analog input pins, AN4 to AN7 are group 1 analog input pins (Initial value) 587 Bits 2 to 0--Channel Select 2 to 0 (CH2 to CH0): Together with the SCAN bit, these bits select the analog input channels. Only set the input channel while conversion is stopped (ADST = 0). Channel Selection CH3 0 CH2 0 CH1 0 CH0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Single Mode (SCAN = 0) AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 (Initial value) Description Scan Mode (SCAN = 1) AN0 AN0, AN1 AN0 to AN2 AN0 to AN3 AN4 AN4, AN5 AN4 to AN6 AN4 to AN7 AN8 AN8, AN9 AN8 to AN10 AN8 to AN11 AN12 AN12, AN13 AN12 to AN14 AN12 to AN15 588 16.2.3 Bit A/D Control Register (ADCR) : 7 TRGS1 0 R/W 6 TRGS0 0 R/W 5 -- 1 -- 4 -- 1 -- 3 CKS1 0 R/W 2 CKS0 0 R/W 1 -- 1 -- 0 -- 1 -- Initial value : R/W : ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D conversion operations and sets the A/D conversion time. ADCR is initialized to H'33 by a reset, and in standby mode or module stop mode. Bits 7 and 6--Timer Trigger Select 1 and 0 (TRGS1, TRGS0): Select enabling or disabling of the start of A/D conversion by a trigger signal. Only set bits TRGS1 and TRGS0 while conversion is stopped (ADST = 0). Bit 7 TRGS1 0 Bit 6 TRGS0 0 1 1 0 1 Description A/D conversion start by software is enabled (Initial value) A/D conversion start by TPU conversion start trigger is enabled Setting prohibited A/D conversion start by external trigger pin (ADTRG) is enabled Bits 5, 4, 1, and 0--Reserved: These bits are always read as 1 and cannot be modified. Bits 3 and 2--Clock Select 1 and 0 (CKS1, CKS0): These bits select the A/D conversion time. The conversion time should be changed only when ADST = 0. Make a setting that gives a value not lower than that shown in table 22-8. Bit 3 CKS1 0 Bit 2 CKS0 0 1 1 0 1 Description Conversion time = 530 states (max.) Conversion time = 266 states (max.) Conversion time = 134 states (max.) Conversion time = 68 states (max.) (Initial value) 589 16.2.4 Bit Module Stop Control Register A (MSTPCRA) : 7 0 R/W 6 0 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value : R/W : MSTPCR is a 8-bit readable/writable register that performs module stop mode control. When the MSTPA1 bit in MSTPCR is set to 1, A/D converter operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see sections 21A.5, 21B.5, Module Stop Mode. MSTPCRA is initialized to H'3F by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 1--Module Stop (MSTPA1): Specifies the A/D converter module stop mode. Bit 1 MSTPA1 0 1 Description A/D converter module stop mode cleared A/D converter module stop mode set (Initial value) 590 16.3 Interface to Bus Master ADDRA to ADDRD are 16-bit registers, and the data bus to the bus master is 8 bits wide. Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is accessed via a temporary register (TEMP). A data read from ADDR is performed as follows. When the upper byte is read, the upper byte value is transferred to the CPU and the lower byte value is transferred to TEMP. Next, when the lower byte is read, the TEMP contents are transferred to the CPU. When reading ADDR. always read the upper byte before the lower byte. It is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. Figure 16-2 shows the data flow for ADDR access. Upper byte read Bus master (H'AA) Bus interface Module data bus TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) (n = A to D) Lower byte read Bus master (H'40) Module data bus Bus interface TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) (n = A to D) Figure 16-2 ADDR Access Operation (Reading H'AA40) 591 16.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode and scan mode. 16.4.1 Single Mode (SCAN = 0) Single mode is selected when A/D conversion is to be performed on a single channel only. A/D conversion is started when the ADST bit is set to 1, according to the software or external trigger input. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when conversion ends. On completion of conversion, the ADF flag is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. The ADF flag is cleared by writing 0 after reading ADCSR. When the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be set at the same time as the operating mode or input channel is changed. Typical operations when channel 1 (AN1) is selected in single mode are described next. Figure 16-3 shows a timing diagram for this example. [1] Single mode is selected (SCAN = 0), input channel AN1 is selected (CH3 = 0, CH2 = 0, CH1 = 0, CH0 = 1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1). [2] When A/D conversion is completed, the result is transferred to ADDRB. At the same time the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle. [3] Since ADF = 1 and ADIE = 1, an ADI interrupt is requested. [4] The A/D interrupt handling routine starts. [5] The routine reads ADCSR, then writes 0 to the ADF flag. [6] The routine reads and processes the connection result (ADDRB). [7] Execution of the A/D interrupt handling routine ends. After that, if the ADST bit is set to 1, A/D conversion starts again and steps [2] to [7] are repeated. 592 Set* ADIE ADST ADF State of channel 0 (AN0) State of channel 1 (AN1) State of channel 2 (AN2) State of channel 3 (AN3) Idle Idle Idle Idle A/D conversion 1 A/D conversion starts Set* Clear* Set* Clear* Idle A/D conversion 2 Idle ADDRA ADDRB ADDRC ADDRD Read conversion result A/D conversion result 1 Read conversion result A/D conversion result 2 Note: * Vertical arrows ( ) indicate instructions executed by software. Figure 16-3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) 593 16.4.2 Scan Mode (SCAN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by a software, timer or external trigger input, A/D conversion starts on the first channel in the group (AN0). When two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (AN1) starts immediately. A/D conversion continues cyclically on the selected channels until the ADST bit is cleared to 0. The conversion results are transferred for storage into the ADDR registers corresponding to the channels. When the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again from the first channel (AN0). The ADST bit can be set at the same time as the operating mode or input channel is changed. Typical operations when three channels (AN0 to AN2) are selected in scan mode are described next. Figure 16-4 shows a timing diagram for this example. [1] Scan mode is selected (SCAN = 1), channel set 0 is selected (CH3 = 0), scan group 0 is selected (CH2 = 0), analog input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1) [2] When A/D conversion of the first channel (AN0) is completed, the result is transferred to ADDRA. Next, conversion of the second channel (AN1) starts automatically. [3] Conversion proceeds in the same way through the third channel (AN2). [4] When conversion of all the selected channels (AN0 to AN2) is completed, the ADF flag is set to 1 and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends. [5] Steps [2] to [4] are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion starts again from the first channel (AN0). 594 Continuous A/D conversion execution Set*1 ADST ADF A/D conversion time State of channel 0 (AN0) State of channel 1 (AN1) State of channel 2 (AN2) State of channel 3 (AN3) Transfer ADDRA ADDRB ADDRC ADDRD Notes: *1 Vertical arrows ( ) indicate instructions executed by software. *2 Data currently being converted is ignored. A/D conversion result 1 A/D conversion result 4 A/D conversion result 2 A/D conversion result 3 Idle Idle Idle A/D conversion 1 Clear*1 Clear*1 Idle A/D conversion 2 A/D conversion 4 Idle A/D conversion 5 *2 Idle A/D conversion 3 Idle Idle Idle Figure 16-4 Example of A/D Converter Operation (Scan Mode, 3 Channels AN0 to AN2 Selected) 595 16.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 16-5 shows the A/D conversion timing. Table 16-4 indicates the A/D conversion time. As indicated in figure 16-5, the A/D conversion time includes tD and the input sampling time. The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 16-4. In scan mode, the values given in table 16-4 apply to the first conversion time. The values given in table 16-5 apply to the second and subsequent conversions. In both cases, set bits CKS1 and CKS0 in ADCR to give a value not lower than that shown in table 22-8. (1) o Address (2) Write signal Input sampling timing ADF tD t SPL t CONV Legend (1) : (2) : : tD : tSPL tCONV : ADCSR write cycle ADCSR address A/D conversion start delay Input sampling time A/D conversion time Figure 16-5 A/D Conversion Timing 596 Table 16-4 A/D Conversion Time (Single Mode) CKS1 = 0 CKS0 = 0 Item CKS0 = 1 CKS1 = 0 CKS0 = 0 CKS0 = 1 Symbol Min Typ Max Min Typ Max Min Typ Max Min Typ Max 18 -- -- 33 10 -- -- 63 17 -- 6 -- -- 31 9 -- 4 -- -- 15 -- 5 -- 68 A/D conversion start delay t D Input sampling time A/D conversion time t SPL t CONV 127 -- 515 -- 530 259 -- 266 131 -- 134 67 Note: Values in the table are the number of states. Table 16-5 A/D Conversion Time (Scan Mode) CKS1 0 CKS0 0 1 1 0 1 Conversion Time (State) 512 (Fixed) 256 (Fixed) 128 (Fixed) 64 (Fixed) 16.4.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to 11 in ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan modes, are the same as if the ADST bit has been set to 1 by software. Figure 16-6 shows the timing. o ADTRG Internal trigger signal ADST A/D conversion Figure 16-6 External Trigger Input Timing 597 16.5 Interrupts The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. ADI interrupt requests can be enabled or disabled by means of the ADIE bit in ADCSR. The DTC can be activated by an ADI interrupt. Having the converted data read by the DTC in response to an ADI interrupt enables continuous conversion to be achieved without imposing a load on software. The A/D converter interrupt source is shown in table 16-6. Table 16-6 A/D Converter Interrupt Source Interrupt Source ADI Description Interrupt due to end of conversion DTC Activation Possible 16.6 Usage Notes The following points should be noted when using the A/D converter. Setting Range of Analog Power Supply and Other Pins: (1) Analog input voltage range The voltage applied to analog input pin ANn during A/D conversion should be in the range AVSS ANn Vref. (2) Relation between AVCC, AVSS and VCC, VSS As the relationship between AVCC, AVSS and VCC, VSS, set AVSS = VSS. If the A/D converter is not used, the AVCC and AVSS pins must on no account be left open. (3) Vref input range The analog reference voltage input at the Vref pin set in the range Vref AVCC. If conditions (1), (2), and (3) above are not met, the reliability of the device may be adversely affected. Notes on Board Design: In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. 598 Also, digital circuitry must be isolated from the analog input signals (AN0 to AN15), analog reference power supply (Vref), and analog power supply (AVCC) by the analog ground (AVSS). Also, the analog ground (AVSS) should be connected at one point to a stable digital ground (VSS) on the board. Notes on Noise Countermeasures: A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN15) and analog reference power supply (Vref) should be connected between AVCC and AVSS as shown in figure 16-7. Also, the bypass capacitors connected to AVCC and Vref and the filter capacitor connected to AN0 to AN15 must be connected to AVSS. If a filter capacitor is connected as shown in figure 16-7, the input currents at the analog input pins (AN0 to AN15) are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin ), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding the circuit constants. AVCC Vref Rin* 2 *1 *1 0.1 F 100 AN0 to AN15 AVSS Notes: Values are reference values. *1 10 F 0.01 F *2 Rin: Input impedance Figure 16-7 Example of Analog Input Protection Circuit 599 Table 16-7 Analog Pin Specifications Item Analog input capacitance Permissible signal source impedance Min -- -- Max 20 5 Unit pF k 10 k AN0 to AN15 To A/D converter 20 pF Note: Values are reference values. Figure 16-8 Analog Input Pin Equivalent Circuit A/D Conversion Precision Definitions: H8S/2626 Series and H8S/2623 Series A/D conversion precision definitions are given below. * Resolution The number of A/D converter digital output codes * Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value B'0000000000 (H'00) to B'0000000001 (H'01) (see figure 16-10). * Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from B'1111111110 (H'3E) to B'1111111111 (H'3F) (see figure 16-10). * Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 16-9). * Nonlinearity error The error with respect to the ideal A/D conversion characteristic between the zero voltage and the full-scale voltage. Does not include the offset error, full-scale error, or quantization error. * Absolute precision The deviation between the digital value and the analog input value. Includes the offset error, full-scale error, quantization error, and nonlinearity error. 600 Digital output 111 110 101 100 011 010 001 000 Ideal A/D conversion characteristic Quantization error 1 2 1024 1024 1022 1023 1024 1024 FS Analog input voltage Figure 16-9 A/D Conversion Precision Definitions (1) Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Offset error Analog input voltage Figure 16-10 A/D Conversion Precision Definitions (2) 601 Permissible Signal Source Impedance: H8S/2626 Series and H8S/2623 Series analog input is designed so that conversion precision is guaranteed for an input signal for which the signal source impedance is 10 k or less. This specification is provided to enable the A/D converter's sampleand-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 10 k, charging may be insufficient and it may not be possible to guarantee the A/D conversion precision. However, if a large capacitance is provided externally, the input load will essentially comprise only the internal input resistance of 10 k, and the signal source impedance is ignored. However, since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/s or greater). When converting a high-speed analog signal, a low-impedance buffer should be inserted. Influences on Absolute Precision: Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute precision. Be sure to make the connection to an electrically stable GND such as AVSS. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, so acting as antennas. H8S/2626 Series or H8S/2623 Series Sensor output impedance to 5 k Sensor input Low-pass filter C to 0.1 F Cin = 15 pF A/D converter equivalent circuit 10 k 20 pF Figure 16-11 Example of Analog Input Circuit 602 Section 17 D/A Converter [Provided in the H8S/2626 Series only] 17.1 Overview The H8S/2626 Series has an on-chip two-channel D/A converter. 17.1.1 Features The D/A converter has the following features. * * * * * * 8-bit resolution Two output channels Conversion time: maximum 10 s (with 20 pF capacitive load) Output voltage: 0 V to Vref D/A output retention in software standby mode Module stop mode setting possible The initial setting is for D/A converter operation to be halted. Register access is enabled by clearing module stop mode. 603 17.1.2 Block Diagram Figure 17-1 shows a block diagram of the D/A converter. Module data bus Bus interface Vref 8-bit D/A DACR23 DADR2 DADR3 AVCC DA3 DA2 AVSS Control circuit Legend DACR23: D/A control register 23 DADR2, DADR3: D/A data registers 2 and 3 Internal data bus Figure 17-1 Block Diagram of D/A Converter 604 17.1.3 Pin Configuration Table 17-1 summarizes the input and output pins used by the D/A converter. Table 17-1 D/A Converter Pins Pin Name Analog power supply pin Analog ground pin Analog output pin 2 Analog output pin 3 Reference voltage pin Symbol AVCC AVSS DA2 DA3 Vref I/O Input Input Output Output Input Function Analog power supply Analog ground and reference voltage Channel 2 analog output Channel 3 analog output Analog reference voltage 17.1.4 Register Configuration Table 17-2 summarizes the registers of the D/A converter. Table 17-2 D/A Converter Registers Channel 2, 3 Name D/A data register 2 D/A data register 3 D/A control register 23 All Module stop control register C Abbreviation DADR2 DADR3 DACR23 MSTPCRC R/W R/W R/W R/W R/W Initial Value H'00 H'00 H'1F H'FF Address* H'FDAC H'FDAD H'FDAE H'FDEA Note: * Lower 16 bits of the address 605 17.2 17.2.1 Bit Register Descriptions D/A Data Registers 2 and 3 (DADR2, DADR3) : 7 6 5 4 3 2 1 0 Initial value : R/W : 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W DADR2 and DADR3 are 8-bit readable/writable registers that store the data to be converted. When analog output is enabled, the values in DADR2 and DADR3 are constantly converted and output at the analog output pins. The D/A data registers are initialized to H'00 by a reset and in hardware standby mode. 17.2.2 Bit D/A Control Register 23 (DACR23) : 7 DAOE1 6 DAOE0 0 R/W 5 DAE 0 R/W 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Initial value : R/W : 0 R/W DACR23 is an 8-bit readable/writable register that controls the operation of the D/A converter. DACR23 is initialized to H'1F by a reset and in hardware standby mode. Bit 7--D/A Output Enable 1 (DAOE1): Controls D/A conversion and analog output. Bit 7 DAOE1 0 1 Description DA3 analog output is disabled Channel 3 D/A conversion and DA3 analog output are enabled (Initial value) Bit 6--D/A Output Enable 0 (DAOE0): Controls D/A conversion and analog output. Bit 6 DAOE0 0 1 Description DA2 analog output is disabled Channel 2 D/A conversion and DA2 analog output are enabled (Initial value) 606 Bit 5--D/A Enable (DAE): Controls D/A conversion, together with bits DAOE0 and DAOE1. When the DAE bit is cleared to 0, D/A conversion is controlled independently in channels 2 and 3. When the DAE bit is set to 1, D/A conversion is controlled together in channels 2 and 3. Output of the conversion result is always controlled independently by bits DAOE0 and DAOE1. Bit 7 DAOE1 0 Bit 6 DAOE0 0 1 Bit 5 DAE * 0 Description D/A conversion is disabled in channels 2 and 3 (Initial value) D/A conversion is enabled in channel 2 D/A conversion is disabled in channel 3 1 0 0 0 D/A conversion is enabled in channels 2 and 3 D/A conversion is disabled in channel 2 D/A conversion is enabled in channel 3 1 1 * D/A conversion is enabled in channels 2 and 3 D/A conversion is enabled in channels 2 and 3 *: Don't care If the chip enters software standby mode while D/A conversion is enabled, the D/A output is retained and the analog power supply current is the same as the analog power supply current during D/A conversion. If it is necessary to reduce the analog power supply current in software standby mode, D/A output should be disabled by clearing both the DAOE0 bit and the DAOE1 bit to 0. Bits 4 to 0--Reserved: These bits are always read as 1, and cannot be modified. 607 17.2.3 Bit Module Stop Control Register C (MSTPCRC) : 7 6 5 4 3 2 1 0 MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 Initial value : R/W : 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W MSTPCRC is an 8-bit readable/writable register that performs module stop mode control. When the MSTPC5 bit is set to 1, D/A converter operation is stopped at the end of the bus cycle, and module stop mode is entered. Register read/write accesses are not possible in module stop mode. For details, see section 21B.5, Module Stop Mode. MSTPCRC is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 5--Module Stop (MSTPC5): Specifies module stop mode for the D/A converter (channels 2 and 3). Bit 5 MSTPC5 0 1 Description D/A converter (channels 2 and 3) module stop mode is cleared D/A converter (channels 2 and 3) module stop mode is set (Initial value) 608 17.3 Operation The D/A converter has two built-in D/A conversion circuits that can perform conversion independently. D/A conversion is performed constantly while enabled in DACR23. If the DADR2 or DADR3 value is modified, conversion of the new data begins immediately. The conversion results are output when bits DAOE0 and DAOE1 are set to 1. An example of D/A conversion on channel 2 is given below. The timing is shown in figure 17-2. 1. Data to be converted is written in DADR2. 2. Bit DAOE0 is set to 1 in DACR23. D/A conversion starts and DA2 becomes an output pin. The conversion result is output after the conversion time. The output value is (DADR2 contents/256) x Vref. Output of this conversion result continues until the value in DADR2 is modified or the DAOE0 bit is cleared to 0. 3. If the DADR2 value is modified, conversion starts immediately, and the result is output after the conversion time. 4. When the DAOE0 bit is cleared to 0, DA2 becomes an input pin. DADR2 write cycle DACR23 write cycle DADR2 write cycle DACR23 write cycle o Address DADR2 DAOE0 Conversion data 1 Conversion data 2 DA2 High-impedance state tDCONV Conversion result 1 tDCONV Conversion result 2 Legend tDCONV: D/A conversion time Figure 17-2 Example of D/A Converter Operation 609 610 Section 18 RAM 18.1 Overview The H8S/2626 and H8S/2623 have 12 kbytes of on-chip high-speed static RAM, the H8S/2625 and H8S/2622 have 8 kbytes, and the H8S/2624 and H8S/2621 have 4 kbytes. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. This makes it possible to perform fast word data transfer. The on-chip RAM can be enabled or disabled by means of the RAM enable bit (RAME) in the system control register (SYSCR). 18.1.1 Block Diagram Figure 18-1 shows a block diagram of the on-chip RAM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'FFC000 H'FFC002 H'FFC004 H'FFC001 H'FFC003 H'FFC005 H'FFEFBE H'FFFFC0 H'FFEFBF H'FFFFC1 H'FFFFFE H'FFFFFF Figure 18-1 Block Diagram of RAM (H8S/2623) 611 18.1.2 Register Configuration The on-chip RAM is controlled by SYSCR. Table 18-1 shows the address and initial value of SYSCR. Table 18-1 RAM Register Name System control register Abbreviation SYSCR R/W R/W Initial Value H'01 Address* H'FDE5 Note: * Lower 16 bits of the address. 18.2 18.2.1 Bit Register Descriptions System Control Register (SYSCR) : 7 MACS 0 R/W 6 -- 0 -- 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 2 -- 0 R/W 1 -- 0 -- 0 RAME 1 R/W Initial value : R/W : The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details of other bits in SYSCR, see section 3.2.2, System Control Register (SYSCR). Bit 0--RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset state is released. It is not initialized in software standby mode. Note: When the DTC is used, the RAME bit must be set to 1. Bit 0 RAME 0 1 Description On-chip RAM is disabled On-chip RAM is enabled (Initial value) 612 18.3 Operation When the RAME bit is set to 1, accesses to addresses H'FFC000 to H'FFEFBF and H'FFFFC0 to H'FFFFFF in the H8S/2626 and H8S/2623, to addresses H'FFD000 to H'FFEFBF and H'FFFFC0 to H'FFFFFF in the H8S/2625 and H8S/2622, and to addresses H'FFE000 to H'FFEFBF and H'FFFFC0 to H'FFFFFF in the H8S/2624 and H8S/2621, are directed to the on-chip RAM. When the RAME bit is cleared to 0, the off-chip address space is accessed. Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written to and read in byte or word units. Each type of access can be performed in one state. Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start at an even address. 18.4 Usage Notes When Using the DTC: DTC register information can be located in addresses H'FFEBC0 to H'FFEFBF. When the DTC is used, the RAME bit must not be cleared to 0. Reserved Areas: Addresses H'FFB000 to H'FFBFFF in the H8S/2626 and H8S/2623, H'FFB000 to H'FFCFFF in the H8S/2625 and H8S/2622, and H'FFB000 to H'FFDFFF in the H8S/2624 and H8S/2621, are reserved areas that cannot be read or written to. When the RAME bit is cleared to 0, external address space is accessed. 613 614 Section 19 ROM 19.1 Features The H8S/2626 Series and H8S/2623 Series have 256 kbytes of on-chip flash memory. The features of the flash memory are summarized below. * Four flash memory operating modes Program mode Erase mode Program-verify mode Erase-verify mode * Programming/erase methods The flash memory is programmed 128 bytes at a time. Block erase (in single-block units) can be performed. To erase the entire flash memory, each block must be erased in turn. Block erasing can be performed as required on 4-kbyte, 32-kbyte, and 64-kbyte blocks. * Programming/erase times The flash memory programming time is 10 ms (typ.) for simultaneous 128-byte programming, equivalent to 78 s (typ.) per byte, and the erase time is 100 ms (typ.). * Reprogramming capability The flash memory can be reprogrammed up to 100 times. * On-board programming modes There are two modes in which flash memory can be programmed/erased/verified on-board: Boot mode User program mode Automatic bit rate adjustment With data transfer in boot mode, the LSI's bit rate can be automatically adjusted to match the transfer bit rate of the host. Flash memory emulation in RAM Flash memory programming can be emulated in real time by overlapping a part of RAM onto flash memory. Protect modes There are three protect modes, hardware, software, and error protection which allow protected status to be designated for flash memory program/erase/verify operations. Programmer mode Flash memory can be programmed/erased in programmer mode, using a PROM programmer, as well as in on-board programming mode. * * * * 615 19.2 19.2.1 Overview Block Diagram Internal address bus Internal data bus (16 bits) Module bus FLMCR1 FLMCR2 EBR1 EBR2 RAMER FLPWCR Bus interface/controller Operating mode FWE pin Mode pin Flash memory (256 kbytes) Legend FLMCR1: FLMCR2: EBR1: EBR2: RAMER: FLPWCR: Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 RAM emulation register Flash memory power control register Figure 19-1 Block Diagram of Flash Memory 616 19.2.2 Mode Transitions When the mode pins and the FWE pin are set in the reset state and a reset-start is executed, the microcomputer enters an operating mode as shown in figure 19-2. In user mode, flash memory can be read but not programmed or erased. The boot, user program and programmer modes are provided as modes to write and erase the flash memory. MD1 = 1, MD2 = 1, FWE = 0 Reset state *1 User mode (on-chip ROM enabled) RES = 0 RES = 0 MD1 = 1, MD2 = 1, FWE = 1 RES = 0 MD1 = 1, MD2 = 0, FWE = 1 RES = 0 *2 FWE = 1 FWE = 0 Programmer mode User program mode *1 Boot mode On-board programming mode Notes: Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory. *1 RAM emulation possible *2 MD0 = 0, MD1 = 0, MD2 = 0, P14 = 0, P16 = 0, PF0 = 1 Figure 19-2 Flash Memory State Transitions 617 19.2.3 On-Board Programming Modes Boot Mode 1. Initial state The old program version or data remains written in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. 2. Programming control program transfer When boot mode is entered, the boot program in the H8S/2626 or H8S/2623 (originally incorporated in the chip) is started and the programming control program in the host is transferred to RAM via SCI communication. The boot program required for flash memory erasing is automatically transferred to the RAM boot program area. Host Host Programming control program New application program New application program LSI Boot program Flash memory RAM SCI LSI Boot program Flash memory RAM Boot program area SCI Application program (old version) Application program (old version) Programming control program 3. Flash memory initialization The erase program in the boot program area (in RAM) is executed, and the flash memory is initialized (to H'FF). In boot mode, total flash memory erasure is performed, without regard to blocks. Host 4. Writing new application program The programming control program transferred from the host to RAM is executed, and the new application program in the host is written into the flash memory. Host New application program LSI Boot program Flash memory RAM Boot program area Flash memory preprogramming erase Programming control program LSI SCI Boot program Flash memory RAM Boot program area New application program Programming control program SCI Program execution state 618 User Program Mode 1. Initial state The FWE assessment program that confirms that user program mode has been entered, and the program that will transfer the programming/erase control program from flash memory to on-chip RAM should be written into the flash memory by the user beforehand. The programming/erase control program should be prepared in the host or in the flash memory. Host Programming/ erase control program New application program New application program 2. Programming/erase control program transfer When user program mode is entered, user software confirms this fact, executes transfer program in the flash memory, and transfers the programming/erase control program to RAM. Host LSI Boot program Flash memory FWE assessment program LSI SCI RAM Boot program Flash memory FWE assessment program SCI RAM Transfer program Transfer program Programming/ erase control program Application program (old version) Application program (old version) 3. Flash memory initialization The programming/erase program in RAM is executed, and the flash memory is initialized (to H'FF). Erasing can be performed in block units, but not in byte units. Host 4. Writing new application program Next, the new application program in the host is written into the erased flash memory blocks. Do not write to unerased blocks. Host New application program LSI Boot program Flash memory FWE assessment program LSI SCI RAM Boot program Flash memory FWE assessment program Transfer program Programming/ erase control program Programming/ erase control program SCI RAM Transfer program Flash memory erase New application program Program execution state 619 19.2.4 Flash Memory Emulation in RAM Emulation should be performed in user mode or user program mode. When the emulation block set in RAMER is accessed while the emulation function is being executed, data written in the overlap RAM is read. SCI Flash memory Emulation block RAM Overlap RAM (emulation is performed on data written in RAM) Application program Execution state Figure 19-3 Reading Overlap RAM Data in User Mode or User Program Mode When overlap RAM data is confirmed, the RAMS bit is cleared, RAM overlap is released, and writes should actually be performed to the flash memory. When the programming control program is transferred to RAM, ensure that the transfer destination and the overlap RAM do not overlap, as this will cause data in the overlap RAM to be rewritten. 620 SCI Flash memory Programming data RAM Application program Overlap RAM (programming data) Programming control program execution state Figure 19-4 Writing Overlap RAM Data in User Program Mode 19.2.5 Differences between Boot Mode and User Program Mode Table 19-1 Differences between Boot Mode and User Program Mode Boot Mode Total erase Block erase Programming control program* Yes No Program/program-verify User Program Mode Yes Yes Erase/erase-verify Program/program-verify Emulation Note: * To be provided by the user, in accordance with the recommended algorithm. 621 19.2.6 Block Configuration The flash memory is divided into three 64-kbyte blocks, one 32-kbyte block, and eight 4-kbyte blocks. Address H'00000 4 kbytes x 8 32 kbytes 64 kbytes 256 kbytes 64 kbytes 64 kbytes Address H'3FFFF Figure 19-5 Flash Memory Block Configuration 19.3 Pin Configuration The flash memory is controlled by means of the pins shown in table 19-2. Table 19-2 Pin Configuration Pin Name Reset Abbreviation I/O RES Input Input Input Input Input Input Input Input Output Input Function Reset Flash memory program/erase protection by hardware Sets MCU operating mode Sets MCU operating mode Sets MCU operating mode Sets MCU operating mode in programmer mode Sets MCU operating mode in programmer mode Sets MCU operating mode in programmer mode Serial transmit data output Serial receive data input Flash write enable FWE Mode 2 Mode 1 Mode 0 Port F0 Port 16 Port 14 Transmit data Receive data MD2 MD1 MD0 PF0 P16 P14 TxD2 RxD2 622 19.4 Register Configuration The registers used to control the on-chip flash memory when enabled are shown in table 19-3. In order to access these registers, the FLSHE bit in SCRX must be set to 1 (except for RAMER, SCRX). Table 19-3 Register Configuration Register Name Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 RAM emulation register Flash memory power control register* Serial control register X 6 Abbreviation FLMCR1* 5 FLMCR2* EBR1 * EBR2 * 5 5 5 5 5 R/W R/W*2 R* 2 2 2 Initial Value H'00* 3 H'00 H'00* H'00* H'00 2 4 4 Address* 1 H'FFA8 H'FFA9 H'FFAA H'FFAB H'FEDB R/W* R/W* R/W R/W* R/W RAMER* FLPWCR* SCRX H'00* H'00 4 H'FFAC H'FDB4 Notes: *1 Lower 16 bits of the address. *2 To access these registers, set the FLSHE bit to 1 in serial control register X. Even if FLSHE is set to 1, if the chip is in a mode in which the on-chip flash memory is disabled, a read will return H'00 and writes are invalid. Writes are also invalid when the FWE bit in FLMCR1 is not set to 1. *3 When a high level is input to the FWE pin, the initial value is H'80. *4 When a low level is input to the FWE pin, or if a high level is input and the SWE1 bit in FLMCR1 is not set, these registers are initialized to H'00. *5 FLMCR1, FLMCR2, EBR1, EBR2, RAMER, and FLPWCR are 8-bit registers. Use byte access on these registers. *6 An invalid register in the H8S/2623. 19.5 19.5.1 Register Descriptions Flash Memory Control Register 1 (FLMCR1) FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode for addresses H'00000 to H'3FFFF is entered by setting SWE1 bit to 1 when FWE = 1, then setting the PV1 or EV1 bit. Program mode for addresses H'00000 to H'3FFFF is entered by setting SWE1 bit to 1 when FWE = 1, then setting the PSU1 bit, and finally setting the P1 bit. Erase mode for addresses H'00000 to H'3FFFF is entered by setting SWE1 bit to 1 when FWE = 1, then setting the ESU1 bit, and finally setting the E1 bit. FLMCR1 is initialized by a reset, and in hardware standby mode and software standby mode. Its initial value is H'80 when a high level is input to the FWE pin, and H'00 when a low level is input. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. 623 Writes are enabled only in the following cases: Writes to bit SWE1 of FLMCR1 enabled when FWE = 1, to bits ESU1, PSU1, EV1, and PV1 when FWE = 1 and SWE1 = 1, to bit E1 when FWE = 1, SWE1 = 1 and ESU1 = 1, and to bit P1 when FWE = 1, SWE1 = 1, and PSU1 = 1. Bit: 7 FWE Initial value: R/W: --* R 6 SWE1 0 R/W 5 ESU1 0 R/W 4 PSU1 0 R/W 3 EV1 0 R/W 2 PV1 0 R/W 1 E1 0 R/W 0 P1 0 R/W Note: * Determined by the state of the FWE pin. Bit 7--Flash Write Enable Bit (FWE): Sets hardware protection against flash memory programming/erasing. Bit 7: FWE 0 1 Description When a low level is input to the FWE pin (hardware-protected state) When a high level is input to the FWE pin Bit 6--Software Write Enable Bit 1 (SWE1): This bit selects write and erase valid/invalid of the flash memory. Set it when setting bits 5 to 0, bits 7 to 0 of EBR1, and bits 3 to 0 of EBR2. Bit 6: SWE1 0 1 Description Writes disabled Writes enabled [Setting condition] When FWE = 1 (Initial value) Bit 5--Erase Setup Bit 1 (ESU1): Prepares for a transition to erase mode. Set this bit to 1 before setting the E1 bit in FLMCR1 to 1. Do not set the SWE1, PSU1, EV1, PV1, E1, or P1 bit at the same time. Bit 5: ESU1 Description 0 1 Erase setup cleared Erase setup [Setting condition] When FWE = 1 and SWE1 = 1 (Initial value) Bit 4--Program Setup Bit 1 (PSU1): Prepares for a transition to program mode. Set this bit to 1 before setting the P1 bit in FLMCR1 to 1. Do not set the SWE1, ESU1, EV1, PV1, E1, or P1 bit at the same time. 624 Bit 4: PSU1 Description 0 1 Program setup cleared Program setup [Setting condition] When FWE = 1 and SWE1 = 1 (Initial value) Bit 3--Erase-Verify 1 (EV1): Selects erase-verify mode transition or clearing. Do not set the SWE1, ESU1, PSU1, PV1, E1, or P1 bit at the same time. Bit 3: EV1 0 1 Description Erase-verify mode cleared Transition to erase-verify mode [Setting condition] When FWE = 1 and SWE1 = 1 (Initial value) Bit 2--Program-Verify 1 (PV1): Selects program-verify mode transition or clearing. Do not set the SWE1, ESU1, PSU1, EV1, E1, or P1 bit at the same time. Bit 2: PV1 Description 0 1 Program-verify mode cleared Transition to program-verify mode [Setting condition] When FWE = 1 and SWE1 = 1 (Initial value) Bit 1--Erase 1 (E1): Selects erase mode transition or clearing. Do not set the SWE1, ESU1, PSU1, EV1, PV1, or P1 bit at the same time. Bit 1: E1 0 1 Description Erase mode cleared Transition to erase mode [Setting condition] When FWE = 1, SWE1 = 1, and ESU1 = 1 (Initial value) 625 Bit 0--Program 1 (P1): Selects program mode transition or clearing. Do not set the SWE1, PSU1, ESU1, EV1, PV1, or E1 bit at the same time. Bit 0: P1 0 1 Description Program mode cleared Transition to program mode [Setting condition] When FWE = 1, SWE1 = 1, and PSU1 = 1 (Initial value) 19.5.2 Flash Memory Control Register 2 (FLMCR2) FLMCR2 is an 8-bit register used for flash memory operating mode control. FLMCR2 is initialized to H'00 by a reset, and in hardware standby mode and software standby mode. When on-chip flash memory is disabled, a read will return H'00. Bit: 7 FLER Initial value: R/W: 0 R 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- 2 -- 0 -- 1 -- 0 -- 0 -- 0 -- Note: FLMCR2 is a read-only register, and should not be written to. Bit 7--Flash Memory Error (FLER): Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the errorprotection state. Bit 7: FLER 0 Description Flash memory is operating normally Flash memory program/erase protection (error protection) is disabled [Clearing condition] Reset or hardware standby mode 1 An error has occurred during flash memory programming/erasing Flash memory program/erase protection (error protection) is enabled [Setting condition] See section 19.8.3, Error Protection (Initial value) Bits 6 to 0--Reserved: These bits always read 0. 626 19.5.3 Erase Block Register 1 (EBR1) EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE1 bit in FLMCR1 is not set. When a bit in EBR1 is set to 1, the corresponding block can be erased. Other blocks are erase-protected. Only one of the bits of EBR1 and EBR2 combined can be set. Do not set more than one bit, as this will cause all the bits in both EBR1 and EBR2 to be automatically cleared to 0. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. The flash memory block configuration is shown in table 19-4. Bit: Initial value: R/W: 7 EB7 0 R/W 6 EB6 0 R/W 5 EB5 0 R/W 4 EB4 0 R/W 3 EB3 0 R/W 2 EB2 0 R/W 1 EB1 0 R/W 0 EB0 0 R/W 19.5.4 Erase Block Register 2 (EBR2) EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low level is input to the FWE pin. Bit 0 will be initialized to 0 if bit SWE1 of FLMCR1 is not set, even though a high level is input to pin FWE. When a bit in EBR2 is set to 1, the corresponding block can be erased. Other blocks are erase-protected. Only one of the bits of EBR1 and EBR2 combined can be set. Do not set more than one bit, as this will cause all the bits in both EBR1 and EBR2 to be automatically cleared to 0. Bits 7 to 4 are reserved and must only be written with 0. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. The flash memory block configuration is shown in table 19-4. Bit: 7 -- Initial value: R/W: 0 R/W 6 -- 0 R/W 5 -- 0 R/W 4 -- 0 R/W 3 EB11 0 R/W 2 EB10 0 R/W 1 EB9 0 R/W 0 EB8 0 R/W 627 Table 19-4 Flash Memory Erase Blocks Block (Size) EB0 (4 kbytes) EB1 (4 kbytes) EB2 (4 kbytes) EB3 (4 kbytes) EB4 (4 kbytes) EB5 (4 kbytes) EB6 (4 kbytes) EB7 (4 kbytes) EB8 (32 kbytes) EB9 (64 kbytes) EB10 (64 kbytes) EB11 (64 kbytes) Addresses H'000000-H'000FFF H'001000-H'001FFF H'002000-H'002FFF H'003000-H'003FFF H'004000-H'004FFF H'005000-H'005FFF H'006000-H'006FFF H'007000-H'007FFF H'008000-H'00FFFF H'010000-H'01FFFF H'020000-H'02FFFF H'030000-H'03FFFF 19.5.5 RAM Emulation Register (RAMER) RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating real-time flash memory programming. RAMER initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. RAMER settings should be made in user mode or user program mode. Flash memory area divisions are shown in table 19-5. To ensure correct operation of the emulation function, the ROM for which RAM emulation is performed should not be accessed immediately after this register has been modified. Normal execution of an access immediately after register modification is not guaranteed. Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R/W 4 -- 0 R/W 3 RAMS 0 R/W 2 RAM2 0 R/W 1 RAM1 0 R/W 0 RAM0 0 R/W Bits 7 and 6--Reserved: These bits always read 0. Bits 5 and 4--Reserved: Only 0 may be written to these bits. 628 Bit 3--RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in RAM. When RAMS = 1, all flash memory block are program/erase-protected. Bit 3: RAMS 0 Description Emulation not selected Program/erase-protection of all flash memory blocks is disabled 1 Emulation selected Program/erase-protection of all flash memory blocks is enabled (Initial value) Bits 2 to 0--Flash Memory Area Selection: These bits are used together with bit 3 to select the flash memory area to be overlapped with RAM. (See table 19-5.) Table 19-5 Flash Memory Area Divisions Addresses H'FFD000-H'FFDFFF H'000000-H'000FFF H'001000-H'001FFF H'002000-H'002FFF H'003000-H'003FFF H'004000-H'004FFF H'005000-H'005FFF H'006000-H'006FFF H'007000-H'007FFF Block Name RAM area 4 kbytes EB0 (4 kbytes) EB1 (4 kbytes) EB2 (4 kbytes) EB3 (4 kbytes) EB4 (4 kbytes) EB5 (4 kbytes) EB6 (4 kbytes) EB7 (4 kbytes) RAMS 0 1 1 1 1 1 1 1 1 RAM2 * 0 0 0 0 1 1 1 1 RAM1 * 0 0 1 1 0 0 1 1 RAM0 * 0 1 0 1 0 1 0 1 *: Don't care 19.5.6 Flash Memory Power Control Register (FLPWCR)* Bit: 7 PDWND Initial value: R/W: 0 R/W 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 -- 0 R FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI switches to subactive mode. Note: * An invalid register in the H8S/2623. 629 Bit 7--Power-Down Disable (PDWND): Enables or disables a transition to the flash memory power-down mode when the LSI switches to subactive mode. Bit 7: PDWND Description 0 1 Transition to flash memory power-down mode enabled Transition to flash memory power-down mode disabled (Initial value) Bits 6 to 0--Reserved: These bits always read 0. 19.5.7 Serial Control Register X (SCRX) Bit 7 -- Initial value R/W 0 R/W 6 -- 0 R/W 5 -- 0 R/W 4 -- 0 R/W 3 FLSHE 0 R/W 2 -- 0 R/W 1 -- 0 R/W 0 -- 0 R/W SCRX is an 8-bit readable/writable register that controls on-chip flash memory. SCRX is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 4--Reserved: Only 0 may be written to these bits. Bit 3--Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). Setting the FLSHE bit to 1 enables read/write access to the flash memory control registers. If FLSHE is cleared to 0, the flash memory control registers are deselected. In this case, the flash memory control register contents are retained. Bit 3: FLSHE 0 1 Description Flash control registers deselected in area H'FFFFA8 to H'FFFFAC (Initial value) Flash control registers selected in area H'FFFFA8 to H'FFFFAC Bits 2 to 0--Reserved: Only 0 may be written to these bits. 630 19.6 On-Board Programming Modes When pins are set to on-board programming mode and a reset-start is executed, a transition is made to the on-board programming state in which program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 19-6. For a diagram of the transitions to the various flash memory modes, see figure 19-2. Table 19-6 Setting On-Board Programming Modes Mode Boot mode Expanded mode Single-chip mode User program mode Expanded mode Single-chip mode 1 FWE 1 MD2 0 0 1 1 MD1 1 1 1 1 MD0 0 1 0 1 19.6.1 Boot Mode When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The SCI channel to be used is set to asynchronous mode. When a reset-start is executed after the H8S/2626 or H8S/2623 pins have been set to boot mode, the boot program built into the LSI is started and the programming control program prepared in the host is serially transmitted to the LSI via the SCI. In the H8S/2626 and H8S/2623, the programming control program received via the SCI is written into the programming control program area in on-chip RAM. After the transfer is completed, control branches to the start address of the programming control program area and the programming control program execution state is entered (flash memory programming is performed). The transferred programming control program must therefore include coding that follows the programming algorithm given later. The system configuration in boot mode is shown in figure 19-6, and the boot mode execution procedure in figure 19-7. 631 H8S/2626 or H8S/2623 Flash memory Host Write data reception Verify data transmission RxD2 SCI2 TxD2 On-chip RAM Figure 19-6 System Configuration in Boot Mode 632 Start Set pins to boot mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate LSI measures low period of H'00 data transmitted by host LSI calculates bit rate and sets value in bit rate register After bit rate adjustment, LSI transmits one H'00 data byte to host to indicate end of adjustment Host confirms normal reception of bit rate adjustment end indication (H'00), and transmits one H'55 data byte After receiving H'55, LSI transmits one H'AA data byte to host Host transmits number of programming control program bytes (N), upper byte followed by lower byte LSI transmits received number of bytes to host as verify data (echo-back) n=1 Host transmits programming control program sequentially in byte units LSI transmits received programming control program to host as verify data (echo-back) Transfer received programming control program to on-chip RAM No Yes End of transmission Check flash memory data, and if data has already been written, erase all blocks After confirming that all flash memory data has been erased, LSI transmits one H'AA data byte to host Execute programming control program transferred to on-chip RAM n+1n n = N? Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is transmitted as an erase error, and the erase operation and subsequent operations are halted. Figure 19-7 Boot Mode Execution Procedure 633 Automatic SCI Bit Rate Adjustment Start bit Stop bit D0 D1 D2 D3 D4 D5 D6 D7 Low period (9 bits) measured (H'00 data) High period (1 or more bits) When boot mode is initiated, the LSI measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. The LSI calculates the bit rate of the transmission from the host from the measured low period, and transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the LSI. If reception cannot be performed normally, initiate boot mode again (reset), and repeat the above operations. Depending on the host's transmission bit rate and the LSI's system clock frequency, there will be a discrepancy between the bit rates of the host and the LSI. Set the host transfer bit rate at 2,400, 4,800, 9,600 or 19,200 bps to operate the SCI properly. Table 19-7 shows host transfer bit rates and system clock frequencies for which automatic adjustment of the LSI bit rate is possible. The boot program should be executed within this system clock range. Table 19-7 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible Host Bit Rate 2,400 bps 4,800 bps 9,600 bps 19,200 bps System Clock Frequency for Which Automatic Adjustment of LSI Bit Rate is Possible 2 to 8 MHz 4 to 16 MHz 8 to 20 MHz 16 to 20 MHz 634 On-Chip RAM Area Divisions in Boot Mode: In boot mode, the RAM area is divided into an area used by the boot program and an area to which the programming control program is transferred via the SCI, as shown in figure 19-8. The boot program area cannot be used until the execution state in boot mode switches to the programming control program transferred from the host. H'FFC000 Programming control program area (8 kbytes) H'FFDFFF H'FFE000 Boot program area (4 kbytes) H'FFEFBF Note: The boot program area cannot be used until a transition is made to the execution state for the programming control program transferred to RAM. Note also that the boot program remains in this area of the on-chip RAM even after control branches to the programming control program. Figure 19-8 RAM Areas in Boot Mode Notes on Use of Boot Mode: * When the chip comes out of reset in boot mode, it measures the low-level period of the input at the SCI's RxD2 pin. The reset should end with RxD2 high. After the reset ends, it takes approximately 100 states before the chip is ready to measure the low-level period of the RxD2 pin. * In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all flash memory blocks are erased. Boot mode is for use when user program mode is unavailable, such as the first time on-board programming is performed, or if the program activated in user program mode is accidentally erased. * Interrupts cannot be used while the flash memory is being programmed or erased. * The RxD2 and TxD2 pins should be pulled up on the board. * Before branching to the programming control program (RAM area H'FFC000), the chip terminates transmit and receive operations by the on-chip SCI (channel 2) (by clearing the RE and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. The transmit data output pin, TxD2, goes to the high-level output state (PA1DDR = 1, PA1DR = 1). 635 The contents of the CPU's internal general registers are undefined at this time, so these registers must be initialized immediately after branching to the programming control program. In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area must be specified for use by the programming control program. The initial values of other on-chip registers are not changed. * Boot mode can be entered by making the pin settings shown in table 19-6 and executing a reset-start. Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting the FWE pin and mode pins, and executing reset release*1. Boot mode can also be cleared by a WDT overflow reset. Do not change the mode pin input levels in boot mode, and do not drive the FWE pin low while the boot program is being executed or while flash memory is being programmed or erased* 2. * If the mode pin input levels are changed (for example, from low to high) during a reset, the state of ports with multiplexed address functions and bus control output pins (AS, RD, HWR) will change according to the change in the microcomputer's operating mode*3. Therefore, care must be taken to make pin settings to prevent these pins from becoming output signal pins during a reset, or to prevent collision with signals outside the microcomputer. Notes: *1 Mode pin and FWE pin input must satisfy the mode programming setup time (tMDS = 4 states) with respect to the reset release timing. *2 For further information on FWE application and disconnection, see section 19.13, Flash Memory Programming and Erasing Precautions. *3 See Appendix D, Pin States. 19.6.2 User Program Mode When set to user program mode, the chip can program and erase its flash memory by executing a user program/erase control program. Therefore, on-board reprogramming of the on-chip flash memory can be carried out by providing on-board means of FWE control and supply of programming data, and storing a program/erase control program in part of the program area as necessary. To select user program mode, select a mode that enables the on-chip flash memory (mode 6 or 7), and apply a high level to the FWE pin. In this mode, on-chip supporting modules other than flash memory operate as they normally would in modes 6 and 7. The flash memory itself cannot be read while the SWE1 bit is set to 1 to perform programming or erasing, so the control program that performs programming and erasing should be run in on-chip RAM or external memory. If the program is to be located in external memory, the instruction for writing to flash memory, and the following instruction, should be placed in on-chip RAM. 636 Figure 19-9 shows the procedure for executing the program/erase control program when transferred to on-chip RAM. Write the FWE assessment program and transfer program (and the program/erase control program if necessary) beforehand MD2, MD1, MD0 = 110, 111 Reset-start Transfer program/erase control program to RAM Branch to program/erase control program in RAM area FWE = high* Execute program/erase control program (flash memory rewriting) Clear FWE* Branch to flash memory application program Notes: Do not apply a constant high level to the FWE pin. Apply a high level to the FWE pin only when the flash memory is programmed or erased. Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. * For further information on FWE application and disconnection, see section19.13, Flash Memory Programming and Erasing Precautions. Figure 19-9 User Program Mode Execution Procedure 637 19.7 Flash Memory Programming/Erasing A software method, using the CPU, is employed to program and erase flash memory in the onboard programming modes. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes for addresses H'000000 to H'03FFFF are made by setting the PSU1, ESU1, P1, E1, PV1, and EV1 bits in FLMCR1. The flash memory cannot be read while being programmed or erased. Therefore, the program (user program) that controls flash memory programming/erasing should be located and executed in on-chip RAM or external memory. If the program is to be located in external memory, the instruction for writing to flash memory, and the following instruction, should be placed in on-chip RAM. Also ensure that the DTC is not activated before or after execution of the flash memory write instruction. In the following operation descriptions, wait times after setting or clearing individual bits in FLMCR1 are given as parameters; for details of the wait times, see section 22.6, Flash Memory Characteristics. Notes: 1. Operation is not guaranteed if setting/resetting of the SWE1, ESU1, PSU1, EV1, PV1, E1, and P1 bits in FLMCR1 is executed by a program in flash memory. 2. When programming or erasing, set FWE to 1 (programming/erasing will not be executed if FWE = 0). 3. Programming must be executed in the erased state. Do not perform additional programming on addresses that have already been programmed. 638 *3 E1 = 1 Erase setup state E1 = 0 Normal mode ESU1 = 1 *1 ESU1 = 0 Erase-verify mode Erase mode FWE = 1 FWE = 0 *2 EV1 = 1 EV1 = 0 PSU1 = 1 PSU1 = 0 On-board SWE1 = 1 Software programming mode programming Software programming enable disable state SWE1 = 0 state *4 P1 = 1 Program setup state P1 = 0 Program mode PV1 = 1 PV1 = 0 Program-verify mode Notes: In order to perform a normal read of flash memory, SWE1 must be cleared to 0. Also note that verify-reads can be performed during the programming/erasing process. *1 : Normal mode : On-board programming mode *2 Do not make a state transition by setting or clearing multiple bits simultaneously. *3 After a transition from erase mode to the erase setup state, do not enter erase mode without passing through the software programming enable state. *4 After a transition from program mode to the program setup state, do not enter program mode without passing through the software programming enable state. Figure 19-10 FLMCR1 Bit Settings and State Transitions 639 19.7.1 Program Mode When writing data or programs to flash memory, the program/program-verify flowchart shown in figure 19-11 should be followed. Performing programming operations according to this flowchart will enable data or programs to be written to flash memory without subjecting the device to voltage stress or sacrificing program data reliability. Programming should be carried out 128 bytes at a time. The wait times after bits are set or cleared in the flash memory control register 1 (FLMCR1) and the maximum number of programming operations (N) are shown in table 22-9 in section 22.6, Flash Memory Characteristics. Following the elapse of (x0) s or more after the SWE1 bit is set to 1 in FLMCR1, 128-byte program data is stored in the program data area and reprogram data area, and the 128-byte data in the program data area in RAM is written consecutively to the program address (the lower 8 bits of the first address written to must be H'00 or H'80). 128 consecutive byte data transfers are performed. The program address and program data are latched in the flash memory. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc. Set 6.6 ms as the WDT overflow period. After this, preparation for program mode (program setup) is carried out by setting the PSU1 bit in FLMCR1, and after the elapse of (y) s or more, the operating mode is switched to program mode by setting the P1 bit in FLMCR1. The time during which the P1 bit is set is the flash memory programming time. Refer to the table in figure 19-11 for the programming time. 640 19.7.2 Program-Verify Mode In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. After the elapse of the given programming time, clear the P1 bit in FLMCR1, then wait for at least () s before clearing the PSU1 bit to exit program mode. After the elapse of at least () s, the watchdog timer is cleared and the operating mode is switched to program-verify mode by setting the PV1 bit in FLMCR1. Before reading in program-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of () s or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least () s after the dummy write before performing this read operation. Next, the originally written data is compared with the verify data, and reprogram data is computed (see figure 19-11) and transferred to RAM. After verification of 128 bytes of data has been completed, exit program-verify mode, wait for at least () s, then clear the SWE1 bit in FLMCR1. If reprogramming is necessary, set program mode again, and repeat the program/program-verify sequence as before. The maximum number of repetitions of the program/program-verify sequence is indicated by the maximum programming count (N). However, ensure that the program/program-verify sequence is not repeated more than (N) times on the same bits. Notes on Program/Program-Verify Procedure 1. In order to perform 128-byte-unit programming, the lower 8 bits of the write start address must be H'00 or H'80. 2. When performing continuous writing of 128-byte data to flash memory, byte-unit transfer should be used. 128-byte data transfer is necessary even when writing fewer than 128 bytes of data. Write H'FF data to the extra addresses. 3. Verify data is read in word units. 4. The write pulse is applied and a flash memory write executed while the P1 bit in FLMCR1 is set. In the H8S/2626 and H8S/2623, write pulses should be applied as follows in the program/program-verify procedure to prevent voltage stress on the device and loss of write data reliability. a. After write pulse application, perform a verify-read in program-verify mode and apply a write pulse again for any bits read as 1 (reprogramming processing). When all the 0-write bits in the 128-byte write data are read as 0 in the verify-read operation, the program/program-verify procedure is completed. In the H8S/2626 and H8S/2623, the number of loops in reprogramming processing is guaranteed not to exceed the maximum value of the maximum programming count (N). 641 b. After write pulse application, a verify-read is performed in program-verify mode, and programming is judged to have been completed for bits read as 0. c. If programming of other bits is incomplete in the 128 bytes, reprogramming processing should be executed. If a bit for which programming has been judged to be completed is read as 1 in a subsequent verify-read, a write pulse should again be applied to that bit. 5. The period for which the P1 bit in FLMCR1 is set (the write pulse width) should be changed according to the degree of progress through the program/program-verify procedure. For detailed wait time specifications, see section 22.6, Flash Memory Characteristics. 6. The program/program-verify flowchart for the H8S/2626 and H8S/2623 is shown in figure 1911. To cover the points noted above, bits on which reprogramming processing is to be executed, and bits on which additional programming is to be executed, must be determined as shown below. Since reprogram data and additional-programming data vary according to the progress of the programming procedure, it is recommended that the following data storage areas (128 bytes each) be provided in RAM. Reprogram Data Computation Table Result of Verify-Read after Write Pulse (X) Application (V) Result of Operation 0 1 1 0 1 1 0 1 (D) 0 Comments Programming completed: reprogramming processing not to be executed Programming incomplete: reprogramming processing to be executed Still in erased state: no action Legend (D): Source data of bits on which programming is executed (X): Source data of bits on which reprogramming is executed 642 Additional-Programming Data Computation Table Result of Verify-Read after Write Pulse (Y) (X') Application (V) Result of Operation 0 0 0 Comments Programming by write pulse application judged to be completed: additional programming processing to be executed Programming by write pulse application incomplete: additional programming processing not to be executed Programming already completed: additional programming processing not to be executed Still in erased state: no action 1 1 1 0 1 Legend (Y): Data of bits on which additional programming is executed (X'): Data of bits on which reprogramming is executed in a certain reprogramming loop 7. It is necessary to execute additional programming processing during the course of the H8S/2626 or H8S/2623 program/program-verify procedure. However, once 128-byte-unit programming is finished, additional programming should not be carried out on the same address area. When executing reprogramming, an erase must be executed first. Note that normal operation of reads, etc., is not guaranteed if additional programming is performed on addresses for which a program/program-verify operation has finished. 643 Start of programming START Set SWE1 bit in FLMCR1 Write pulse application subroutine*5 Sub-Routine Write Pulse Enable WDT Set PSU1 bit in FLMCR1 tspsu: tsswe: Programming must be executed in the erased state. Do not perform additional programming on addresses that have already been programmed. Wait (x 0) s Store 128 bytes of program data in program *4 data area and reprogram data area n=1 m=0 Successively write 128-byte reprogram data to flash memory Sub-Routine-Call Wait (y) s Set P1 bit in FLMCR1 *1 *5 tsp10 or tsp30 or tsp200: Wait (z0) s or (z1) s or (z2) s Clear P1 bit in FLMCR1 tcp: Write pulse application subroutine Set PV1 bit in FLMCR1 tspv: Wait () s Wait () s Clear PSU1 bit in FLMCR1 Wait () s Disable WDT End Sub Note *6: Programming Time P1 Bit Set Time (s) Additional Number of Writes Programming Programming z0 1 z1 2 z0 z1 * * * * * * * * * H'FF dummy write to verify address tspur: Wait () s Read verify data *2 NG m=1 NG nn+1 Increment address Program data = verify data? OK N1 n ? OK Additional-programming data computation Transfer additional-programming data to additional-programming data area Reprogram data computation *4 *3 *4 N1-1 N1 N1+1 N1+2 N1+3 * * * z0 z0 z2 z2 z2 * * * z1 z1 -- -- -- * * * Transfer reprogram data to reprogram data area 128-byte data verification completed? OK Clear PV1 bit in FLMCR1 tcpv: tcpv: NG N1+N2-2 N1+N2-1 N1+N2 z2 z2 z2 -- -- -- Wait () s N1 n ? NG RAM Program data storage area (128 bytes) Successively write 128-byte data from additional- 1 * programming data area in RAM to flash memory Sub-Routine-Call Additional programming subroutine Reprogram data storage area (128 bytes) m=0? NG n (N1 + N2) ? NG Additional-programming data storage area (128 bytes) OK Clear SWE1 bit in FLMCR1 tcswe: tcswe: OK Clear SWE1 bit in FLMCR1 tcswe: Wait (x1) s End of programming Wait (x1) s Programming failure Notes: *1 Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. *2 Verify data is read in 16-bit (word) units. *3 Even bits for which programming has been completed in the 128-byte programming loop will be subject to programming again if they fail the subsequent verify operation. *4 A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional-programming data must be provided in RAM. The reprogram and additional-programming data contents are modified as programming proceeds. *5 A write pulse of 30 s or 200 s is applied according to the progress of the programming operation. See Note *6 for details of the pulse widths. When writing of additional-programming data is executed, a 10 s write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied. Reprogram Data Computation Table Original Data (D) 0 0 1 1 Verify Data (V) 0 1 0 1 Reprogram Data (X) 1 0 1 1 Comments Programming complete Programming is incomplete: reprogramming should be performed Left in the erased state Additional-Programming Data Computation Table Reprogram Data (X') 0 0 1 1 Verify Data (V) 0 1 0 1 Additional-Programming Data (X) 0 1 1 1 Comments Additional programming should be performed Additional programming should not be performed Additional programming should not be performed Additional programming should not be performed Figure 19-11 Program/Program-Verify Flowchart 644 19.7.3 Erase Mode When erasing flash memory, the single-block erase/erase-verify flowchart shown in figure 19-12 should be followed. To erase flash memory contents, make a 1-bit setting for the flash memory area to be erased in erase block register 1 and 2 (EBR1, EBR2) at least (x) s after setting the SWE1 bit to 1 in FLMCR1. Next, the watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. Set 6.6 ms as the WDT overflow period. Preparation for entering erase mode (erase setup) is performed next by setting the ESU1 bit in FLMCR1. The operating mode is then switched to erase mode by setting the E1 bit in FLMCR1 after the elapse of at least (y) s. The time during which the E1 bit is set is the flash memory erase time. Ensure that the erase time does not exceed (z) ms. Note: With flash memory erasing, preprogramming (setting all memory data in the memory to be erased to all 0) is not necessary before starting the erase procedure. 19.7.4 Erase-Verify Mode In erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased. After the elapse of the fixed erase time, clear the E1 bit in FLMCR1, then wait for at least () s before clearing the ESU1 bit to exit erase mode. After exiting erase mode, the watchdog timer is cleared after the elapse of () s or more. The operating mode is then switched to erase-verify mode by setting the EV1 bit in FLMCR1. Before reading in erase-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of () s or more. When the flash memory is read in this state (verify data is read in 16bit units), the data at the latched address is read. Wait at least () s after the dummy write before performing this read operation. If the read data has been erased (all 1), a dummy write is performed to the next address, and erase-verify is performed. If the read data is unerased, set erase mode again and repeat the erase/erase-verify sequence in the same way. The maximum number of reoperations of the erase/erase-verify sequence is indicated by the maximum erase count (N). However, ensure that the erase/erase-verify sequence is not repeated more than (N) times. When verification is completed, exit erase-verify mode, and wait for at least () s. If erasure has been completed on all the erase blocks, clear the SWE1 bit in FLMCR1. If there are any unerased blocks, make a 1 bit setting for the flash memory area to be erased, and repeat the erase/eraseverify sequence as before. 645 Start *1 Set SWE1 bit in FLMCR1 tsswe: Wait (x) s n=1 Set EBR1 and 2 Enable WDT Set ESU1 bit in FLMCR1 tsesu: Wait (y) s Set E1 bit in FLMCR1 tse: Wait (z) ms Clear E1 bit in FLMCR1 tce: Wait () s Clear ESU1 bit in FLMCR1 tcesu: Wait () s Disable WDT Set EV1 bit in FLMCR1 tsev: Wait () s Set block start address to verify address nn+1 Halt erase Start erase *3 H'FF dummy write to verify address tsevr: Wait () s Increment address Read verify data Verify data = all "1"? OK NG Last address of block? OK Clear EV1 bit in FLMCR1 tcev: Wait () s NG *4 *2 NG Clear EV1 bit in FLMCR1 tcev: Wait () s NG End of erasing of all erase blocks? OK n (N)? OK Clear SWE1 bit in FLMCR1 tcswe: Wait (x 1) s Erase failure Clear SWE1 bit in FLMCR1 tcswe: Wait (x 1) s End of erasing Notes: *1 *2 *3 *4 Preprogramming (setting erase block data to all "0") is not necessary. Verify data is read in 16-bit (W) units. Set only one bit in EBR1 and 2. More than 2 bits cannot be set. Erasing is performed in block units. To erase a number of blocks, each block must be erased in turn. Figure 19-12 Erase/Erase-Verify Flowchart 646 19.8 Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 19.8.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Hardware protection is reset by settings in flash memory control register 1 (FLMCR1), flash memory control register 2 (FLMCR2), erase block register 1 (EBR1), and erase block register 2 (EBR2). The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained in the error-protected state. (See table 19-8.) Table 19-8 Hardware Protection Functions Item FWE pin protection Description * When a low level is input to the FWE pin, FLMCR1, FLMCR2, (except bit FLER) EBR1, and EBR2 are initialized, and the program/erase-protected state is entered. In a reset (including a WDT reset) and in standby mode, FLMCR1, FLMCR2, EBR1, and EBR2 are initialized, and the program/erase-protected state is entered. In a reset via the RES pin, the reset state is not entered unless the RES pin is held low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the RES pin low for the RES pulse width specified in the AC Characteristics section. Program Yes Erase Yes Reset/standby protection * Yes Yes * 647 19.8.2 Software Protection Software protection can be implemented by setting the SWE1 bit in FLMCR1, erase block register 1 (EBR1), erase block register 2 (EBR2), and the RAMS bit in the RAM emulation register (RAMER). When software protection is in effect, setting the P1 or E1 bit in flash memory control register 1 (FLMCR1), does not cause a transition to program mode or erase mode. (See table 19-9.) Table 19-9 Software Protection Functions Item SWE bit protection Description * Setting bit SWE1 in FLMCR1 to 0 will place area H'000000 to H'03FFFFF in the program/erase-protected state. (Execute the program in the on-chip RAM, external memory) Erase protection can be set for individual blocks by settings in erase block register 1 (EBR1) and erase block register 2 (EBR2). Setting EBR1 and EBR2 to H'00 places all blocks in the erase-protected state. Setting the RAMS bit to 1 in the RAM emulation register (RAMER) places all blocks in the program/erase-protected state. Program Yes Erase Yes Block specification protection * -- Yes * Emulation protection * Yes Yes 648 19.8.3 Error Protection In error protection, an error is detected when H8S/2626 or H8S/2623 runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. If the H8S/2626 or H8S/2623 malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, but program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered by re-setting the P1 or E1 bit. However, PV1 and EV1 bit setting is enabled, and a transition can be made to verify mode. FLER bit setting conditions are as follows: 1. When the flash memory of the relevant address area is read during programming/erasing (including vector read and instruction fetch) 2. When a SLEEP instruction (including software standby) is executed during programming/erasing Error protection is released only by a reset and in hardware standby mode. 649 Figure 19-13 shows the flash memory state transition diagram. Program mode Erase mode RD VF PR ER FLER = 0 RES = 0 or HSTBY = 0 Reset or standby (hardware protection) RD VF PR ER FLER = 0 Error occurrence (software standby) Error occurrence RES = 0 or HSTBY = 0 RES = 0 or HSTBY = 0 FLMCR1, FLMCR2, EBR1, EBR2 initialization state Error protection mode RD VF PR ER FLER = 1 Software standby mode Software standby mode release Error protection mode (software standby) RD VF PR ER FLER = 1 FLMCR1, FLMCR2, EBR1, EBR2 initialization state Legend RD: Memory read possible VF: Verify-read possible PR: Programming possible ER: Erasing possible RD: VF: PR: ER: Memory read not possible Verify-read not possible Programming not possible Erasing not possible Figure 19-13 Flash Memory State Transitions 650 19.9 Flash Memory Emulation in RAM Making a setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time. After the RAMER setting has been made, accesses cannot be made from the flash memory area or the RAM area overlapping flash memory. Emulation can be performed in user mode and user program mode. Figure 19-14 shows an example of emulation of real-time flash memory programming. Start of emulation program Set RAMER Write tuning data to overlap RAM Execute application program No Tuning OK? Yes Clear RAMER Write to flash memory emulation block End of emulation program Figure 19-14 Flowchart for Flash Memory Emulation in RAM 651 This area can be accessed from both the RAM area and flash memory area H'00000 EB0 H'01000 EB1 H'02000 EB2 H'03000 EB3 H'04000 EB4 H'05000 EB5 H'06000 EB6 H'07000 EB7 H'08000 H'FFD000 Flash memory EB8 to EB11 On-chip RAM H'FFEFBF H'3FFFF H'FFDFFF Figure 19-15 Example of RAM Overlap Operation Example in which Flash Memory Block Area EB0 is Overlapped 1. Set bits RAMS, RAM2 to RAM0 in RAMER to 1, 0, 0, 0, to overlap part of RAM onto the area (EB0) for which real-time programming is required. 2. Real-time programming is performed using the overlapping RAM. 3. After the program data has been confirmed, the RAMS bit is cleared, releasing RAM overlap. 4. The data written in the overlapping RAM is written into the flash memory space (EB0). Notes: 1. When the RAMS bit is set to 1, program/erase protection is enabled for all blocks regardless of the value of RAM2 to RAM0 (emulation protection). In this state, setting the P1 or E1 bit in flash memory control register 1 (FLMCR1), will not cause a transition to program mode or erase mode. When actually programming or erasing a flash memory area, the RAMS bit should be cleared to 0. 2. A RAM area cannot be erased by execution of software in accordance with the erase algorithm while flash memory emulation in RAM is being used. 3. Block area EB0 contains the vector table. When performing RAM emulation, the vector table is needed in the overlap RAM. 652 19.10 Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including NMI interrupt is disabled when flash memory is being programmed or erased (when the P1 or E1 bit is set in FLMCR1), and while the boot program is executing in boot mode*1, to give priority to the program or erase operation. There are three reasons for this: 1. Interrupt during programming or erasing might cause a violation of the programming or erasing algorithm, with the result that normal operation could not be assured. 2. In the interrupt exception handling sequence during programming or erasing, the vector would not be read correctly*2, possibly resulting in MCU runaway. 3. If interrupt occurred during boot program execution, it would not be possible to execute the normal boot mode sequence. For these reasons, in on-board programming mode alone there are conditions for disabling interrupt, as an exception to the general rule. However, this provision does not guarantee normal erasing and programming or MCU operation. All requests, including NMI interrupt, must therefore be restricted inside and outside the MCU when programming or erasing flash memory. NMI interrupt is also disabled in the error-protection state while the P1 or E1 bit remains set in FLMCR1. Notes: *1 Interrupt requests must be disabled inside and outside the MCU until the programming control program has completed programming. *2 The vector may not be read correctly in this case for the following two reasons: * If flash memory is read while being programmed or erased (while the P1 or E1 bit is set in FLMCR1), correct read data will not be obtained (undetermined values will be returned). * If the interrupt entry in the vector table has not been programmed yet, interrupt exception handling will not be executed correctly. 19.11 Flash Memory Programmer Mode Programs and data can be written and erased in programmer mode as well as in the on-board programming modes. In programmer mode, flash memory read mode, auto-program mode, autoerase mode, and status read mode are supported. In auto-program mode, auto-erase mode, and status read mode, a status polling procedure is used, and in status read mode, detailed internal signals are output after execution of an auto-program or auto-erase operation. In programmer mode, set the mode pins to programmer mode (see table 19-10) and input a 12 MHz input clock. Table 19-10 shows the pin settings for programmer mode. 653 Table 19-10 Programmer Mode Pin Settings Pin Names Mode pins: MD2, MD1, MD0 Mode setting pins: PF0, P16, P14 FWE pin RES pin XTAL, EXTAL, PLLVCC, PLLCAP, PLLVSS pins Settings Low level input to MD2, MD1, and MD0. High level input to PF0, low level input to P16 and P14 High level input (in auto-program and auto-erase modes) Reset circuit Oscillator circuit 19.11.1 Socket Adapter Pin Correspondence Diagram Connect the socket adapter to the chip as shown in figure 19-17. This will enable conversion to a 40-pin arrangement. The on-chip ROM memory map is shown in figure 19-16, and the socket adapter pin correspondence diagram in figure 19-17. Addresses in MCU mode H'000000 Addresses in programmer mode H'00000 On-chip ROM space 256 kbytes H'03FFFF H'3FFFF Figure 19-16 On-Chip ROM Memory Map 654 H8S/2626 or H8S/2623 Pin No. 28 29 30 31 32 33 34 35 36 38 40 41 42 43 44 45 46 47 20 21 22 23 24 25 26 27 19 16 18 67 6, 9, 13, 17, 39, 52, 61, 62, 63, 75, 76, 77, 97 2, 4, 8, 14, 15, 37, 48, 49, 53, 54, 55, 56, 65, 94, 95, 98 60 64 66 59 58 57 Other than the above Pin Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 D8 D9 D10 D11 D12 D13 D14 D15 CE OE WE FWE VCC VSS RES XTAL EXTAL PLL VCC PLLCAP PLL VSS NC (OPEN) Socket Adapter (Conversion to 40-Pin Arrangement) HN27C4096HG (40 Pins) Pin No. 21 22 23 24 25 26 27 28 29 31 32 33 34 35 36 37 38 39 19 18 17 16 15 14 13 12 2 20 3 4 1, 40 11, 30 5, 6, 7 8 Pin Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CE OE WE FWE VCC VSS NC A20 A19 A18 Flash write enable Data input/output Address input Chip enable Output enable Write enable Power-on reset circuit Oscillator circuit 9 10 Legend FWE: I/O7-I/O0: A18-A0: CE: OE: WE: PLL circuit Figure 19-17 Socket Adapter Pin Correspondence Diagram 655 19.11.2 Programmer Mode Operation Table 19-11 shows how the different operating modes are set when using programmer mode, and table 19-12 lists the commands used in programmer mode. Details of each mode are given below. * Memory Read Mode Memory read mode supports byte reads. * Auto-Program Mode Auto-program mode supports programming of 128 bytes at a time. Status polling is used to confirm the end of auto-programming. * Auto-Erase Mode Auto-erase mode supports automatic erasing of the entire flash memory. Status polling is used to confirm the end of auto-programming. * Status Read Mode Status polling is used for auto-programming and auto-erasing, and normal termination can be confirmed by reading the I/O6 signal. In status read mode, error information is output if an error occurs. Table 19-11 Settings for Various Operating Modes in Programmer Mode Pin Names Mode Read Output disable Command write Chip disable* 1 FWE H or L H or L H or L* H or L 3 CE L L L H OE L H H X WE H H L X I/O7- I/O0 Data output Hi-Z Data input Hi-Z A18-A0 Ain X Ain* 2 X Notes: *1 Chip disable is not a standby state; internally, it is an operation state. *2 Ain indicates that there is also address input in auto-program mode. *3 For command writes in auto-program and auto-erase modes, input a high level to the FWE pin. 656 Table 19-12 Programmer Mode Commands Number of Cycles 1+n 129 2 2 1st Cycle Mode Write Write Write Write Address Data X X X X H'00 H'40 H'20 H'71 Mode Read Write Write Write 2nd Cycle Address Data RA WA X X Dout Din H'20 H'71 Command Name Memory read mode Auto-program mode Auto-erase mode Status read mode Notes: 1. In auto-program mode, 129 cycles are required for command writing by a simultaneous 128-byte write. 2. In memory read mode, the number of cycles depends on the number of address write cycles (n). 19.11.3 Memory Read Mode 1. After completion of auto-program/auto-erase/status read operations, a transition is made to the command wait state. When reading memory contents, a transition to memory read mode must first be made with a command write, after which the memory contents are read. 2. In memory read mode, command writes can be performed in the same way as in the command wait state. 3. Once memory read mode has been entered, consecutive reads can be performed. 4. After powering on, memory read mode is entered. Table 19-13 AC Characteristics in Transition to Memory Read Mode (Conditions: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C) Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width WE rise time WE fall time Symbol t nxtc t ceh t ces t dh t ds t wep tr tf Min 20 0 0 50 50 70 -- -- Max -- -- -- -- -- -- 30 30 Unit s ns ns ns ns ns ns ns 657 Command write A18-A0 tces CE tceh tnxtc Memory read mode Address stable OE tf WE twep tr tds I/O7-I/O0 tdh Note: Data is latched on the rising edge of WE. Figure 19-18 Timing Waveforms for Memory Read after Memory Write Table 19-14 AC Characteristics in Transition from Memory Read Mode to Another Mode (Conditions: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C) Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width WE rise time WE fall time Symbol t nxtc t ceh t ces t dh t ds t wep tr tf Min 20 0 0 50 50 70 -- -- Max -- -- -- -- -- -- 30 30 Unit s ns ns ns ns ns ns ns 658 Memory read mode A18-A0 Address stable tnxtc CE Other mode command write tces tceh OE tf WE twep tr tds I/O7-I/O0 Note: Do not enable WE and OE at the same time. tdh Figure 19-19 Timing Waveforms in Transition from Memory Read Mode to Another Mode Table 19-15 AC Characteristics in Memory Read Mode (Conditions: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C) Item Access time CE output delay time OE output delay time Output disable delay time Data output hold time Symbol t acc t ce t oe t df t oh Min -- -- -- -- 5 Max 20 150 150 100 -- Unit s ns ns ns ns A18-A0 Address stable Address stable CE OE WE VIL VIL VIH tacc toh tacc toh I/O7-I/O0 Figure 19-20 CE and OE Enable State Read Timing Waveforms 659 A18-A0 CE Address stable tce toe Address stable tce toe OE WE tacc toh I/O7-I/O0 tdf tacc toh VIH tdf Figure 19-21 CE and OE Clock System Read Timing Waveforms 19.11.4 Auto-Program Mode 1. In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out by executing 128 consecutive byte transfers. 2. A 128-byte data transfer is necessary even when programming fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. 3. The lower 7 bits of the transfer address must be low. If a value other than an effective address is input, processing will switch to a memory write operation but a write error will be flagged. 4. Memory address transfer is performed in the second cycle (figure 19-22). Do not perform transfer after the third cycle. 5. Do not perform a command write during a programming operation. 6. Perform one auto-program operation for a 128-byte block for each address. Two or more additional programming operations cannot be performed on a previously programmed address block. 7. Confirm normal end of auto-programming by checking I/O6. Alternatively, status read mode can also be used for this purpose (I/O7 status polling uses the auto-program operation end decision pin). 8. Status polling I/O6 and I/O7 pin information is retained until the next command write. As long as the next command write has not been performed, reading is possible by enabling CE and OE. 660 Table 19-16 AC Characteristics in Auto-Program Mode (Conditions: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C) Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width Status polling start time Status polling access time Address setup time Address hold time Memory write time Write setup time Write end setup time WE rise time WE fall time Symbol t nxtc t ceh t ces t dh t ds t wep t wsts t spa t as t ah t write t pns t pnh tr tf Min 20 0 0 50 50 70 1 -- 0 60 1 100 100 -- -- Max -- -- -- -- -- -- -- 150 -- -- 3000 -- -- 30 30 Unit s ns ns ns ns ns ms ns ns ns ms ns ns ns ns FWE tpnh Address stable tpns tces tceh tnxtc tnxtc A18-A0 CE OE tf twep tr tas tah Data transfer 1 to 128 bytes twsts tspa WE tds tdh twrite Write operation end decision signal I/O7 I/O6 I/O5-I/O0 Write normal end decision signal H'40 H'00 Figure 19-22 Auto-Program Mode Timing Waveforms 661 19.11.5 Auto-Erase Mode 1. Auto-erase mode supports only entire memory erasing. 2. Do not perform a command write during auto-erasing. 3. Confirm normal end of auto-erasing by checking I/O6. Alternatively, status read mode can also be used for this purpose (I/O7 status polling uses the auto-erase operation end decision pin). 4. Status polling I/O6 and I/O7 pin information is retained until the next command write. As long as the next command write has not been performed, reading is possible by enabling CE and OE. Table 19-17 AC Characteristics in Auto-Erase Mode (Conditions: V CC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C) Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width Status polling start time Status polling access time Memory erase time Erase setup time Erase end setup time WE rise time WE fall time Symbol t nxtc t ceh t ces t dh t ds t wep t ests t spa t erase t ens t enh tr tf Min 20 0 0 50 50 70 1 -- 100 100 100 -- -- Max -- -- -- -- -- -- -- 150 40000 -- -- 30 30 Unit s ns ns ns ns ns ms ns ms ns ns ns ns 662 FWE A18-A0 CE OE WE I/O7 ;;;; tpnh tens tces tceh tnxtc tnxtc tf twep tr tests tspa tds tdh terase Erase end decision signal Erase normal end decision signal I/O6 I/O5-I/O0 H'20 H'20 H'00 Figure 19-23 Auto-Erase Mode Timing Waveforms 663 19.11.6 Status Read Mode 1. Status read mode is provided to identify the kind of abnormal end. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. 2. The return code is retained until a command write other than a status read mode command write is executed. Table 19-18 AC Characteristics in Status Read Mode (Conditions: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C) Item Read time after command write CE hold time CE setup time Data hold time Data setup time Symbol t nxtc t ceh t ces t dh t ds Min 20 0 0 50 50 70 -- -- -- -- -- Max -- -- -- -- -- -- Unit s ns ns ns ns ns Write pulse width OE output delay time Disable delay time WE rise time WE fall time CE output delay time A18-A0 I/O7-I/O0 ;;;; t wep t oe t df 150 100 150 30 30 ns ns ns ns ns t ce tr tf tces tceh tnxtc tces tceh tnxtc tnxtc CE tce OE tf twep tr tf twep tr toe WE tds tdh tds tdh tdf H'71 H'71 Note: I/O2 and I/O3 are undefined. Figure 19-24 Status Read Mode Timing Waveforms 664 Table 19-19 Status Read Mode Return Commands Pin Name I/O7 Attribute Normal end decision I/O6 Command error I/O5 Programming error I/O4 Erase error I/O3 -- I/O2 -- I/O1 I/O0 ProgramEffective ming or address error erase count exceeded 0 0 Initial value 0 Indications Normal end: 0 Abnormal end: 1 0 Command error: 1 0 0 0 0 -- ProgramErasing -- ming error: 1 Otherwise: 0 error: 1 Otherwise: 0 Otherwise: 0 Count Effective exceeded: 1 address Otherwise: 0 error: 1 Otherwise: 0 Note: I/O2 and I/O3 are undefined. 19.11.7 Status Polling 1. The I/O7 status polling flag indicates the operating status in auto-program/auto-erase mode. 2. The I/O6 status polling flag indicates a normal or abnormal end in auto-program/auto-erase mode. Table 19-20 Status Polling Output Truth Table Pin Name I/O7 I/O6 I/O0-I/O5 During Internal Operation 0 0 0 Abnormal End 1 0 0 -- 0 1 0 Normal End 1 1 0 19.11.8 Programmer Mode Transition Time Commands cannot be accepted during the oscillation stabilization period or the programmer mode setup period. After the programmer mode setup time, a transition is made to memory read mode. Table 19-21 Stipulated Transition Times to Command Wait State Item Standby release (oscillation stabilization time) Programmer mode setup time VCC hold time Symbol t osc1 t bmv t dwn Min 30 10 0 Max -- -- -- Unit ms ms ms 665 tosc1 VCC tbmv Memory read mode Command Auto-program mode wait state Auto-erase mode Command wait state Normal/abnormal end decision tdwn RES FWE Note: When using other than the automatic write mode and automatic erase mode, drive the FWE input pin low. Figure 19-25 Oscillation Stabilization Time, Boot Program Transfer Time, and Power-Down Sequence 19.11.9 Notes on Memory Programming 1. When programming addresses which have previously been programmed, carry out autoerasing before auto-programming. 2. When performing programming using programmer mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. Notes: 1. The flash memory is initially in the erased state when the device is shipped by Hitachi. For other chips for which the erasure history is unknown, it is recommended that autoerasing be executed to check and supplement the initialization (erase) level. 2. Auto-programming should be performed once only on the same address block. Additional programming cannot be performed on previously programmed address blocks. 666 19.12 Flash Memory and Power-Down States In addition to its normal operating state, the flash memory has power-down states in which power consumption is reduced by halting part or all of the internal power supply circuitry. There are three flash memory operating states: (1) Normal operating mode: The flash memory can be read and written to. (2) Power-down mode: Part of the power supply circuitry is halted, and the flash memory can be read when the LSI is operating on the subclock. (3) Standby mode: All flash memory circuits are halted, and the flash memory cannot be read or written to. States (2) and (3) are flash memory power-down states. Table 19-22 shows the correspondence between the operating states of the LSI and the flash memory. Table 19-22 Flash Memory Operating States LSI Operating State High-speed mode Medium-speed mode Sleep mode Subactive mode Subsleep mode Watch mode Software standby mode Hardware standby mode When PDWND = 0: Power-down mode (read-only) When PDWND = 1: Normal mode (read-only) Standby mode Flash Memory Operating State Normal mode (read/write) 19.12.1 Note on Power-Down States When the flash memory is in a power-down state, part or all of the internal power supply circuitry is halted. Therefore, a power supply circuit stabilization period must be provided when returning to normal operation. When the flash memory returns to its normal operating state from a powerdown state, bits STS2 to STS0 in SBYCR must be set to provide a wait time of at least 20 s (power supply stabilization time), even if an oscillation stabilization period is not necessary. 667 19.13 Flash Memory Programming and Erasing Precautions Precautions concerning the use of on-board programming mode, the RAM emulation function, and programmer mode are summarized below. 1. Use the specified voltages and timing for programming and erasing. Applied voltages in excess of the rating can permanently damage the device. Use a PROM programmer that supports the Hitachi microcomputer device type with 256-kbyte on-chip flash memory (FZTAT256V3A). Do not select the HN27C4096 setting for the PROM programmer, and only use the specified socket adapter. Failure to observe these points may result in damage to the device. 2. Powering on and off (see figures 19-26 to 19-28) Do not apply a high level to the FWE pin until VCC has stabilized. Also, drive the FWE pin low before turning off VCC. When applying or disconnecting VCC power, fix the FWE pin low and place the flash memory in the hardware protection state. The power-on and power-off timing requirements should also be satisfied in the event of a power failure and subsequent recovery. 3. FWE application/disconnection (see figures 19-26 to 19-28) FWE application should be carried out when MCU operation is in a stable condition. If MCU operation is not stable, fix the FWE pin low and set the protection state. The following points must be observed concerning FWE application and disconnection to prevent unintentional programming or erasing of flash memory: * Apply FWE when the VCC voltage has stabilized within its rated voltage range. Apply FWE when oscillation has stabilized (after the elapse of the oscillation settling time). * In boot mode, apply and disconnect FWE during a reset. * In user program mode, FWE can be switched between high and low level regardless of RES input. FWE input can also be switched during execution of a program in flash memory. * Do not apply FWE if program runaway has occurred. * Disconnect FWE only when the SWE1, ESU1, PSU1, EV1, PV1, P1, and E1 bits in FLMCR1 are cleared. Make sure that the SWE1, ESU1, PSU1, EV1, PV1, P1, and E1 bits are not set by mistake when applying or disconnecting FWE. 668 4. Do not apply a constant high level to the FWE pin. Apply a high level to the FWE pin only when programming or erasing flash memory. A system configuration in which a high level is constantly applied to the FWE pin should be avoided. Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. 5. Use the recommended algorithm when programming and erasing flash memory. The recommended algorithm enables programming and erasing to be carried out without subjecting the device to voltage stress or sacrificing program data reliability. When setting the P1 or E1 bit in FLMCR1, the watchdog timer should be set beforehand as a precaution against program runaway, etc. 6. Do not set or clear the SWE1 bit during execution of a program in flash memory. Do not set or clear the SWE1 bit during execution of a program in flash memory. Wait for at least 100 s after clearing the SWE1 bit before executing a program or reading data in flash memory. When the SWE1 bit is set, data in flash memory can be rewritten, but when SWE1 = 1, flash memory can only be read in program-verify or erase-verify mode. Access flash memory only for verify operations (verification during programming/erasing). Do not clear the SWE1 bit during programming, erasing, or verifying. Similarly, when using the RAM emulation function while a high level is being input to the FWE pin, the SWE1 bit must be cleared before executing a program or reading data in flash memory. However, the RAM area overlapping flash memory space can be read and written to regardless of whether the SWE1 bit is set or cleared. 7. Do not use interrupts while flash memory is being programmed or erased. All interrupt requests, including NMI, should be disabled during FWE application to give priority to program/erase operations. 8. Do not perform additional programming. Erase the memory before reprogramming. In on-board programming, perform only one programming operation on a 128-byte programming unit block. In programmer mode, also, perform only one programming operation on a 128-byte programming unit block. 9. Before programming, check that the chip is correctly mounted in the PROM programmer. Overcurrent damage to the device can result if the index marks on the PROM programmer socket, socket adapter, and chip are not correctly aligned. 10. Do not touch the socket adapter or chip during programming. Touching either of these can cause contact faults and write errors. 669 Wait time: x Programming/ erasing possible Wait time: 100 s tOSC1 VCC tMDS*3 Min 0 s FWE Min 0 s MD2 to MD0*1 tMDS*3 RES SWE1 set SWE1 bit SWE1 cleared Period during which flash memory access is prohibited (x: Wait time after setting SWE1 bit)*2 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: *1 Except when switching modes, the level of the mode pins (MD2-MD0) must be fixed until poweroff by pulling the pins up or down. *2 See section 22.6, Flash Memory Characteristics. *3 Mode programming setup time tMDS (min) = 200 ns Figure 19-26 Power-On/Off Timing (Boot Mode) 670 Wait time: x Programming/ erasing possible Wait time: 100 s tOSC1 VCC Min 0 s FWE MD2 to MD0*1 tMDS*3 RES SWE1 set SWE1 bit SWE1 cleared Period during which flash memory access is prohibited (x: Wait time after setting SWE1 bit)*2 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: *1 Except when switching modes, the level of the mode pins (MD2-MD0) must be fixed until poweroff by pulling the pins up or down. *2 See section 22.6, Flash Memory Characteristics. *3 Mode programming setup time tMDS (min) = 200 ns Figure 19-27 Power-On/Off Timing (User Program Mode) 671 Wait time: 100 s Wait time: x Programming/ erasing possible Wait time: 100 s Wait time: x Programming/ erasing possible Wait time: 100 s tOSC1 VCC Min 0s FWE tMDS tMDS*2 MD2 to MD0 tMDS tRESW RES SWE1 set SWE1 cleared SWE1 bit Mode change*1 Boot mode Mode User change*1 mode User program mode User mode User program mode Period during which flash memory access is prohibited (x: Wait time after setting SWE1 bit)*3 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: *1 When entering boot mode or making a transition from boot mode to another mode, mode switching must be carried out by means of RES input. The state of ports with multiplexed address functions and bus control output pins (AS, RD, WR) will change during this switchover interval (the interval during which the RES pin input is low), and therefore these pins should not be used as output signals during this time. *2 When making a transition from boot mode to another mode, a mode programming setup time, tMDS (min), of 200 ns is necessary with respect to the RES clearance timing. *3 See section 22.6, Flash Memory Characteristics. Figure 19-28 Mode Transition Timing (Example: Boot Mode User Mode User Program Mode) 672 Wait time: 100 s Wait time: x Programming/ erasing possible Programming/ erasing possible Wait time: x 19.14 Note on Switching from F-ZTAT Version to Mask ROM Version The mask ROM version does not have the internal registers for flash memory control that are provided in the F-ZTAT version. Table 19-23 lists the registers that are present in the F-ZTAT version but not in the mask ROM version. If a register listed in table 19-23 is read in the mask ROM version, an undefined value will be returned. Therefore, if application software developed on the F-ZTAT version is switched to a mask ROM version product, it must be modified to ensure that the registers in table 19-23 have no effect. Table 19-23 Registers Present in F-ZTAT Version but Absent in Mask ROM Version Register Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 RAM emulation register Flash memory power control register Abbreviation FLMCR1 FLMCR2 EBR1 EBR2 RAMER FLPWCR Address H'FFA8 H'FFA9 H'FFAA H'FFAB H'FEDB H'FFAC 673 674 Section 20 Clock Pulse Generator 20.1 Overview The H8S/2626 Series and H8S/2623 Series have an on-chip clock pulse generator (CPG) that generates the system clock (o), the bus master clock, and internal clocks. The clock pulse generator consists of an oscillator, PLL (phase-locked loop) circuit, clock selection circuit, medium-speed clock divider, bus master clock selection circuit, subclock oscillator*, and waveform shaping circuit*. The frequency can be changed by means of the PLL circuit in the CPG. Frequency changes are performed by software by means of settings in the system clock control register (SCKCR) and low-power control register (LPWRCR). Note: * Supported only in the H8S/2626 Series; not available in the H8S/2623 Series. 675 20.1.1 Block Diagram Figure 20-1 shows a block diagram of the clock pulse generator. LPWRCR STC1, STC0 SCKCR SCK2 to SCK0 EXTAL XTAL System clock oscillator PLL circuit (x1, x2, x4) Clock selection circuit o SUB Mediumspeed clock divider o/2 to o/32 Bus master clock selection circuit o OSC1 OSC2 Subclock oscillator* Waveform shaping circuit* System clock Internal clock to to o pin supporting modules Bus master clock to CPU and DTC WDT1 count clock Legend: LPWRCR: Low-power control register SCKCR: System clock control register Note: * Supported only in the H8S/2626 Series, not available in the H8S/2623 Series. Figure 20-1 Block Diagram of Clock Pulse Generator 20.1.2 Register Configuration The clock pulse generator is controlled by SCKCR and LPWRCR. Table 20-1 shows the register configuration. Table 20-1 Clock Pulse Generator Register Name System clock control register Low-power control register Abbreviation SCKCR LPWRCR R/W R/W R/W Initial Value H'00 H'00 Address* H'FDE6 H'FDEC Note:* Lower 16 bits of the address. 676 20.2 20.2.1 Bit Register Descriptions System Clock Control Register (SCKCR) : 7 PSTOP 0 R/W 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 STCS 0 R/W 2 SCK2 0 R/W 1 SCK1 0 R/W 0 SCK0 0 R/W Initial value: R/W : SCKCR is an 8-bit readable/writable register that performs o clock output control, selection of operation when the PLL circuit frequency multiplication factor is changed, and medium-speed mode control. SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7--o Clock Output Disable (PSTOP): Controls o output. Description Bit 7 PSTOP 0 1 High-speed Mode, Medium-Speed Mode o output (initial value) Fixed high Software Standby Mode Fixed high Fixed high Hardware Standby Mode High impedance High impedance Sleep Mode o output Fixed high Bits 6 to 4--Reserved: These bits are always read as 0 and cannot be modified. Bit 3--Frequency Multiplication Factor Switching Mode Select (STCS): Selects the operation when the PLL circuit frequency multiplication factor is changed. Bit 3 STCS 0 1 Description Specified multiplication factor is valid after transition to software standby mode (Initial value) Specified multiplication factor is valid immediately after STC bits are rewritten 677 Bits 2 to 0--System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the bus master clock. Bit 2 SCK2 0 Bit 1 SCK1 0 Bit 0 SCK0 0 1 1 0 1 1 0 0 1 1 -- Description Bus master is in high-speed mode Medium-speed clock is o/2 Medium-speed clock is o/4 Medium-speed clock is o/8 Medium-speed clock is o/16 Medium-speed clock is o/32 -- (Initial value) 20.2.2 Bit Low-Power Control Register (LPWRCR) 7 DTON 0 R/W 6 LSON 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 -- 0 R/W 1 STC1 0 R/W 0 STC0 0 R/W NESEL SUBSTP RFCUT Initial value Read/Write LPWRCR is an 8-bit readable/writable register that performs power-down mode control. LPWRCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. Bits 7 to 2--Reserved: The function of these bits differs between the H8S/2623 Series and H8S/2626 Series. For details see sections 21A.2.3, 21B.2.3, Low-Power Control Register (LPWRCR). Bits 1 and 0--Frequency Multiplication Factor (STC1, STC0): The STC bits specify the frequency multiplication factor of the PLL circuit. Bit 1 STC1 0 Bit 0 STC0 0 1 1 0 1 Description x1 x2 x4 Setting prohibited (Initial value) 678 Note: A system clock frequency multiplied by the multiplication factor (STC1 and STC0) should not exceed the maximum operating frequency defined in sections 21A and 21B, Electrical Characteristics. 20.3 Oscillator Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. In either case, the input clock should not exceed 20 MHz. 20.3.1 Connecting a Crystal Resonator Circuit Configuration: A crystal resonator can be connected as shown in the example in figure 20-2. Select the damping resistance Rd according to table 20-2. An AT-cut parallel-resonance crystal should be used. CL1 EXTAL XTAL Rd CL2 CL1 = CL2 = 10 to 22pF Figure 20-2 Connection of Crystal Resonator (Example) Table 20-2 Damping Resistance Value Frequency (MHz) Rd () 4 500 8 200 12 0 16 0 20 0 Crystal Resonator: Figure 20-3 shows the equivalent circuit of the crystal resonator. Use a crystal resonator that has the characteristics shown in table 20-3. The crystal resonator frequency should not exceed 20 MHz. CL L XTAL Rs EXTAL AT-cut parallel-resonance type C0 Figure 20-3 Crystal Resonator Equivalent Circuit 679 Table 20-3 Crystal Resonator Parameters Frequency (MHz) RS max () C0 max (pF) 4 120 7 8 80 7 12 60 7 16 50 7 20 40 7 Note on Board Design: When a crystal resonator is connected, the following points should be noted: Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation. See figure 20-4. When designing the board, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins. Avoid CL2 Signal A Signal B H8S/2626 Series or H8S/2623 Series XTAL EXTAL CL1 Figure 20-4 Example of Incorrect Board Design 680 External circuitry such as that shown below is recommended around the PLL. R1: 3 k PLLCAP C1: 470 pF Rp: 200 PLLVCC PLLVSS CPB: 0.1 F* PVCC1 to PVCC4 VCC VSS CB: 1000pF* CB: 300pF* (Values are preliminary recommended values.) Note: * CB and CPB are laminated ceramic capacitors. Figure 20-5 Points for Attention when Using PLL Oscillation Circuit Place oscillation stabilization capacitor C1 and resistor R1 close to the PLLCAP pin, and ensure that no other signal lines cross this line. Supply the C1 ground from PLLVSS. Separate PLLVCC and PLLVSS from the other VCC/VSS and PVCC/PVSS lines at the board power supply source, and be sure to insert bypass capacitors CPB and CB close to the pins. 681 20.3.2 External Clock Input Circuit Configuration: An external clock signal can be input as shown in the examples in figure 20-6. If the XTAL pin is left open, make sure that stray capacitance is no more than 10 pF. In example (b), make sure that the external clock is held high in standby mode. EXTAL XTAL Open External clock input (a) XTAL pin left open EXTAL XTAL External clock input (b) Complementary clock input at XTAL pin Figure 20-6 External Clock Input (Examples) 682 External Clock: Use an external clock frequency of 20 MHz or less. Table 20-4 and figure 20-7 show the input conditions for the external clock. Table 20-4 External Clock Input Conditions VCC = 3.0 V to 3.6 V, PVCC = 5.0 V 10% Item External clock input low pulse width External clock input high pulse width External clock rise time External clock fall time Clock low pulse width level Symbol t EXL t EXH t EXr t EXf t CL Min 15 15 -- -- 0.4 80 Clock high pulse width level t CH 0.4 80 Max -- -- 5 5 0.6 -- 0.6 -- Unit ns ns ns ns t cyc ns t cyc ns o 5 MHz o < 5 MHz o 5 MHz o < 5 MHz Figure 22-2 Test Conditions Figure 20-7 tEXH tEXL EXTAL VCC x 0.5 tEXr tEXf Figure 20-7 External Clock Input Timing 683 20.4 PLL Circuit The PLL circuit has the function of multiplying the frequency of the clock from the oscillator by a factor of 1, 2, or 4. The multiplication factor is set with the STC bits in LPWRCR. The phase of the rising edge of the internal clock is controlled so as to match that at the EXTAL pin. When setting the multiplication factor, ensure that the clock frequency after multiplication does not exceed the maximum operating frequency of the chip. When the multiplication factor of the PLL circuit is changed, the operation varies according to the setting of the STCS bit in SCKCR. When STCS = 0 (initial value), the setting becomes valid after a transition to software standby mode. The transition time count is performed in accordance with the setting of bits STS2 to STS0 in SBYCR. [1] The initial PLL circuit multiplication factor is 1. [2] A value is set in bits STS2 to STS0 to give the specified transition time. [3] The target value is set in STC1 and STC0, and a transition is made to software standby mode. [4] The clock pulse generator stops and the value set in STC1 and STC0 becomes valid. [5] Software standby mode is cleared, and a transition time is secured in accordance with the setting in STS2 to STS0. [6] After the set transition time has elapsed, the LSI resumes operation using the target multiplication factor. If a PC break is set for the SLEEP instruction that causes a transition to software standby mode in [3], software standby mode is entered and break exception handling is executed after the oscillation stabilization time. In this case, the instruction following the SLEEP instruction is executed after execution of the RTE instruction. When STCS = 1, the LSI operates on the changed multiplication factor immediately after bits STC1 and STC0 are rewritten. 20.5 Medium-Speed Clock Divider The medium-speed clock divider divides the system clock to generate o/2, o/4, o/8, o/16, and o/32. 20.6 Bus Master Clock Selection Circuit The bus master clock selection circuit selects the system clock (o) or one of the medium-speed clocks (o/2, o/4, o/8, o/16, and o/32) to be supplied to the bus master, according to the settings of the SCK2 to SCK0 bits in SCKCR. 684 20.7 Subclock Oscillator (H8S/2626 Series Only) (1) Connecting 32.768kHz Crystal Oscillator To supply a clock to the subclock oscillator, connect a 32.768kHz crystal oscillator, as shown in figure 20-8. See section 20.3.1, Note on Board Design for notes on connecting crystal oscillators. C1 OSC1 C2 OSC2 C1 = C2 = 15 pF (typ) Figure 20-8 Example Connection of 32.768 kHz Crystal Oscillator Figure 20-9 shows the equivalence circuit for a 32.768kHz oscillator. Ls Cs Rs OSC1 Co Co = 1.5 pF (typ.) Rs = 14 k (typ.) fw = 32.768 kHz OSC2 Type No.: MX38T (Nihon Dempa Kogyo) Figure 20-9 Equivalence Circuit for 32.768 kHz Oscillator 685 (2) Handling pins when subclock not required If no subclock is required, connect the OSC1 pin to Vcc and leave OSC2 open, as shown in figure 20-10. VCC OSC1 OSC2 Open Figure 20-10 Pin Handling When Subclock Not Required 20.8 Subclock Waveform Shaping Circuit (H8S/2626 Series Only) To eliminate noise from the subclock input to OSC1, the subclock is sampled using the dividing clock o. The sampling frequency is set using the NESEL bit of LPWRCR. For details, see section 21B.2.3, Low Power Control Register (LPWRCR). No sampling is performed in sub-active mode, sub-sleep mode, or watch mode. 20.9 Note on Crystal Resonator Since various characteristics related to the crystal resonator are closely linked to the user's board design, thorough evaluation is necessary on the user's part, for both the mask versions and F-ZTAT versions, using the resonator connection examples shown in this section as a guide. As the resonator circuit ratings will depend on the floating capacitance of the resonator and the mounting circuit, the ratings should be determined in consultation with the resonator manufacturer. The design must ensure that a voltage exceeding the maximum rating is not applied to the oscillator pin. 686 Section 21A Power-Down Modes [H8S/2623 Series] Subclock functions are not available in the H8S/2623 Series. 21A.1 Overview In addition to the normal program execution state, the H8S/2623 Series has five power-down modes in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip supporting modules, and so on. The H8S/2623 operating modes are as follows: (1) High-speed mode (2) Medium-speed mode (3) Sleep mode (4) Module stop mode (5) Software standby mode (6) Hardware standby mode (2) to (6) are power-down modes. Sleep mode is CPU states, medium-speed mode is a CPU and bus master state, and module stop mode is an internal peripheral function (including bus masters other than the CPU) state. Some of these states can be combined. After a reset, the LSI is in high-speed mode with modules other than the DTC in module stop mode. Note: Subclock functions (subactive mode, subsleep mode, and watch mode) are not available in the H8S/2623 Series. Table 21A-1 shows the internal state of the LSI in the respective modes. Figure 21A-1 is a mode transition diagram. 687 Table 21A-1 LSI Internal States in Each Mode Function System clock pulse generator CPU Instructions Registers NMI IRQ0-IRQ5 WDT0 DTC TPU PBC PPG SCI0 SCI1 SCI2 PWM A/D RAM I/O HCAN Functioning Functioning Functioning Functioning Functioning Functioning* Functioning (DTC) Functioning Functioning Functioning Functioning Halted (reset) Retained Retained Halted (reset) Retained High impedance Halted (reset) Functioning Functioning Functioning Functioning Functioning Functioning Halted (retained) Halted (retained) Halted (retained) Halted (retained) Halted (retained) Halted (reset) Halted (reset) Halted (reset) HighSpeed Functioning Functioning MediumSpeed Functioning Sleep Functioning Module Stop Functioning Software Standby Halted Hardware Standby Halted Halted (undefined) Halted Medium-speed Halted operation (retained) Functioning Functioning High/medium- Halted speed (retained) operation Functioning Functioning External interrupts Peripheral functions Functioning Medium-speed Functioning operation Functioning Functioning (PBC mediumspeed operation) Functioning Functioning Halted (reset) Halted (reset) Halted (reset) Notes: "Halted (retained)" means that internal register values are retained. The internal state is "operation suspended." "Halted (reset)" means that internal register values and internal states are initialized. In module stop mode, only modules for which a stop setting has been made are halted (reset or retained). * Note, however, that registers cannot be read or written to. 688 Program-halted state STBY pin = Low Reset state Hardware standby mode STBY pin = High RES pin = Low RES pin = High Program execution state SLEEP command High-speed mode (main clock) Any interrupt SCK2 to SCK0= 0 SCK2 to SCK0 0 SLEEP command SSBY = 0 Sleep mode (main clock) SSBY = 1 Software standby mode Medium-speed mode (main clock) External interrupt * : Transition after exception processing Notes: * NMI and IRQ0 to IRQ5 : Low power dissipation mode * When a transition is made between modes by means of an interrupt, the transition cannot be made on interrupt source generation alone. Ensure that interrupt handling is performed after accepting the interrupt request. * From any state except hardware standby mode, a transition to the reset state occurs when RES is driven low. * From any state, a transition to hardware standby mode occurs when STBY is driven low. Figure 21A-1 Mode Transition Diagram 689 21A.1.1 Register Configuration Power-down modes are controlled by the SBYCR, SCKCR, LPWRCR, and MSTPCR registers. Table 21A-2 summarizes these registers. Table 21A-2 Power-Down Mode Registers Name Standby control register System clock control register Low power control register Module stop control register A, B, C Abbreviation SBYCR SCKCR LPWRCR MSTPCRA MSTPCRB MSTPCRC Note: * Lower 16 bits of the address. R/W R/W R/W R/W R/W R/W R/W Initial Value H'08 H'00 H'00 H'3F H'FF H'FF Address* H'FDE4 H'FDE6 H'FDEC H'FDE8 H'FDE9 H'FDEA 21A.2 Register Descriptions 21A.2.1 Standby Control Register (SBYCR) Bit : 7 SSBY Initial value : R/W : 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 OPE 1 R/W 2 -- 0 -- 1 -- 0 -- 0 -- 0 -- SBYCR is an 8-bit readable/writable register that performs power-down mode control. SBYCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7--Software Standby (SSBY): When making a low power dissipation mode transition by executing the SLEEP instruction, the operating mode is determined in combination with other control bits. Note that the value of the SSBY bit does not change even when shifting between modes using interrupts. 690 Bit 7 SSBY 0 1 Description Shifts to sleep mode when the SLEEP instruction is executed in high-speed mode or medium-speed mode. (Initial value) Shifts to software standby mode when the SLEEP instruction is executed in highspeed mode or medium-speed mode. Bits 6 to 4--Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the MCU wait time for clock stabilization when shifting to high-speed mode or medium-speed mode by using a specific interrupt or command to cancel software standby mode. With a quartz oscillator (table 21A-4), select a wait time of 8ms (oscillation stabilization time) or more, depending on the operating frequency. With an external clock, there are no specific wait requirements. Bit 6 STS2 0 Bit 5 STS1 0 Bit 4 STS0 0 1 1 0 1 1 0 0 1 1 0 1 Description Standby time = 8192 states Standby time = 16384 states Standby time = 32768 states Standby time = 65536 states Standby time = 131072 states Standby time = 262144 states Reserved Standby time = 16 states (Initial value) Bit 3--Output Port Enable (OPE): This bit specifies whether the output of the address bus and bus control signals (AS, RD, HWR, LWR) is retained or set to high-impedance state in the software standby mode. Bit 3 OPE 0 1 Description In software standby mode, address bus and bus control signals are high-impedance. In software standby mode, the output state of the address bus and bus control signals is retained. (Initial value) Bits 2 to 0--Reserved: These bits always return 0 when read, and cannot be written to. 691 21A.2.2 System Clock Control Register (SCKCR) Bit : 7 PSTOP Initial value : R/W : 0 R/W 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 STCS 0 R/W 2 SCK2 0 R/W 1 SCK1 0 R/W 0 SCK0 0 R/W SCKCR is an 8-bit readable/writable register that performs o clock output control and mediumspeed mode control. SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7--o Clock Output Disable (PSTOP): In combination with the DDR of the applicable port, this bit controls o output. See section 21A.8, o Clock Output Disable Function, for details. Description Bit 7 PSTOP 0 1 High-Speed Mode, Medium-Speed Mode o output (initial value) Fixed high Software Standby Mode Fixed high Fixed high Hardware Standby Mode High impedance High impedance Sleep Mode o output Fixed high Bits 6 to 4--Reserved: These bits are always read as 0 and cannot be modified. Bit 3--Frequency Multiplication Factor Switching Mode Select (STCS): Selects the operation when the PLL circuit frequency multiplication factor is changed. Bit 3 STCS 0 1 Description Specified multiplication factor is valid after transition to software standby mode (Initial value) Specified multiplication factor is valid immediately after STC bits are rewritten 692 Bits 2 to 0--System clock select (SCK2 to SCK0): These bits select the bus master clock in high-speed mode, and medium-speed mode. Bit 2 SCK2 0 Bit 1 SCK1 0 Bit 0 SCK0 0 1 1 0 1 1 0 0 1 1 -- Description Bus master in high-speed mode Medium-speed clock is o/2 Medium-speed clock is o/4 Medium-speed clock is o/8 Medium-speed clock is o/16 Medium-speed clock is o/32 -- (Initial value) 21A.2.3 Low-Power Control Register (LPWRCR) Bit : 7 DTON Initial value : R/W : 0 R/W 6 LSON 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 -- 0 R/W 1 STC1 0 R/W 0 STC0 0 R/W NESEL SUBSTP RFCUT The LPWRCR is an 8-bit read/write register that controls the low power dissipation modes. The LPWRCR is initialized to H'00 at a reset and when in hardware standby mode. It is not initialized in software standby mode. The following describes bits 7 to 2. For details of other bits, see section 20.2.2, Low-Power Control Register (LPWRCR). Bits 7 to 4--Reserved: Bits DTON, LSON, NESEL, and SUBSTP must always be written with 0 in the H8S/2623 Series, as this version does not support subclock operation. Bit 3--Oscillation Circuit Feedback Resistance Control Bit (RFCUT): This bit turns the internal feedback resistance of the main clock oscillation circuit ON/OFF. Bit 3 RFCUT 0 1 Description When the main clock is oscillating, sets the feedback resistance ON. When the main clock is stopped, sets the feedback resistance OFF. (Initial value) Sets the feedback resistance OFF. Bit 2--Reserved: Only write 0 to this bit. 693 21A.2.4 Module Stop Control Register (MSTPCR) MSTPCRA Bit : 7 6 5 4 3 2 1 0 MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value : R/W MSTPCRB Bit : 7 6 5 4 3 2 1 0 : 0 R/W 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0 Initial value : R/W MSTPCRC Bit : 7 6 5 4 3 2 1 0 : 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 Initial value : R/W : 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W MSTPCR, comprising three 8-bit readable/writable registers, performs module stop mode control. MSTPCRA to MSTPCRC are initialized to H'3FFFFF by a reset and in hardware standby mode. They are not initialized in software standby mode. MSTPCRA/MSTPCRB/MSTPCRC Bits 7 to 0--Module Stop (MSTPA7 to MSTPA0, MSTPB7 to MSTPB0, MSTPC7 to MSTPC0, MSTPD7 and MSTPD6): These bits specify module stop mode. See table 21A-3 for the method of selecting the on-chip peripheral functions. MSTPCRA/MSTPCRB/ MSTPCRC Bits 7 to 0 MSTPA7 to MSTPA0, MSTPB7 to MSTPB0, MSTPC7 to MSTPC0 0 1 Description Module stop mode is cleared (initial value of MSTPA7 and MSTPA6) Module stop mode is set (initial value of MSTPA5-0, MSTPB7-0, MSTPC7-0) 694 21A.3 Medium-Speed Mode In high-speed mode, when the SCK2 to SCK0 bits in SCKCR are set to 1, the operating mode changes to medium-speed mode as soon as the current bus cycle ends. In medium-speed mode, the CPU operates on the operating clock (o/2, o/4, o/8, o/16, or o/32) specified by the SCK2 to SCK0 bits. The bus masters other than the CPU (DTC) also operate in medium-speed mode. On-chip supporting modules other than the bus masters always operate on the high-speed clock (o). In medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. For example, if o/4 is selected as the operating clock, on-chip memory is accessed in 4 states, and internal I/O registers in 8 states. Medium-speed mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to high-speed mode and medium-speed mode is cleared at the end of the current bus cycle. If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by an interrupt, medium-speed mode is restored. When the SLEEP instruction is executed with the SSBY bit = 1, operation shifts to the software standby mode. When software standby mode is cleared by an external interrupt, medium-speed mode is restored. When the RES pin is set low and medium-speed mode is cancelled, operation shifts to the reset state. The same applies in the case of a reset caused by overflow of the watchdog timer. When the STBY pin is driven low, a transition is made to hardware standby mode. Figure 21A-2 shows the timing for transition to and clearance of medium-speed mode. Medium-speed mode o, supporting module clock Bus master clock Internal address bus SBYCR SBYCR Internal write signal Figure 21A-2 Medium-Speed Mode Transition and Clearance Timing 695 21A.4 Sleep Mode 21A.4.1 Sleep Mode When the SLEEP instruction is executed when the SBYCR SSBY bit = 0, the CPU enters the sleep mode. In sleep mode, CPU operation stops but the contents of the CPUis internal registers are retained. Other supporting modules do not stop. 21A.4.2 Exiting Sleep Mode Sleep mode is exited by any interrupt, or signals at the RES, or STBY pins. Exiting Sleep Mode by Interrupts: When an interrupt occurs, sleep mode is exited and interrupt exception processing starts. Sleep mode is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the CPU. Exiting Sleep Mode by RES pin: Setting the RES pin level Low selects the reset state. After the stipulated reset input duration, driving the RES pin High starts the CPU performing reset exception processing. Exiting Sleep Mode by STBY Pin: When the STBY pin level is driven Low, a transition is made to hardware standby mode. 21A.5 Module Stop Mode 21A.5.1 Module Stop Mode Module stop mode can be set for individual on-chip supporting modules. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues operating independently. Table 21A-3 shows MSTP bits and the corresponding on-chip supporting modules. When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module starts operating at the end of the bus cycle. In module stop mode, the internal states of modules other than the SCI, A/D converter and HCAN are retained. After reset clearance, all modules other than DTC are in module stop mode. When an on-chip supporting module is in module stop mode, read/write access to its registers is disabled. 696 Table 21A-3 MSTP Bits and Corresponding On-Chip Supporting Modules Register MSTPCRA Bit MSTPA7* MSTPA6 MSTPA5 MSTPA4* MSTPA3 MSTPA2* MSTPA1 MSTPA0* MSTPCRB MSTPB7 MSTPB6 MSTPB5 MSTPB4* MSTPB3* MSTPB2* MSTPB1* MSTPB0* MSTPCRC MSTPC7* MSTPC6* MSTPC5* MSTPC4 MSTPC3 MSTPC2* MSTPC1* MSTPC0* Note: * MSTPA7 is a readable/writable bit with an initial value of 0. MSTPA4, MSTPA2, MSTPA0, MSTPB4 to MSTPB0, MSTPC7 to MSTPC5, and MSTPC2 to MSTPC0 are readable/writable bits with an initial value of 1 and should always be written with 1. PC break controller (PBC) HCAN Serial communication interface 0 (SCI0) Serial communication interface 1 (SCI1) Serial communication interface 2 (SCI2) A/D converter Programmable pulse generator (PPG) Data transfer controller (DTC) 16-bit timer pulse unit (TPU) Module 697 21A.5.2 Usage Notes DTC Module Stop: Depending on the operating status of the DTC, the MSTPA7 and MSTPA6 bits may not be set to 1. Setting of the DTC module stop mode should be carried out only when the respective module is not activated. For details, refer to section 8, Data Transfer Controller (DTC). On-Chip Supporting Module Interrupt: Relevant interrupt operations cannot be performed in module stop mode. Consequently, if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DTC activation source. Interrupts should therefore be disabled before entering module stop mode. Writing to MSTPCR: MSTPCR should only be written to by the CPU. 21A.6 Software Standby Mode 21A.6.1 Software Standby Mode A transition is made to software standby mode when the SLEEP instruction is executed when the SBYCR SSBY bit = 1. In this mode, the CPU, on-chip supporting modules, and oscillator all stop. However, the contents of the CPU's internal registers, RAM data, and the states of on-chip supporting modules other than the SCI, A/D converter, HCAN and I/O ports, are retained. Whether the address bus and bus control signals are placed in the high-impedance state or retain the output state can be specified by the OPE bit in SBYCR. In this mode the oscillator stops, and therefore power dissipation is significantly reduced. 21A.6.2 Clearing Software Standby Mode Software standby mode is cleared by an external interrupt (NMI pin, or pins IRQ0 to IRQ5), or by means of the RES pin or STBY pin. * Clearing with an interrupt When an NMI or IRQ0 to IRQ5 interrupt request signal is input, clock oscillation starts, and after the elapse of the time set in bits STS2 to STS0 in SYSCR, stable clocks are supplied to the entire chip, software standby mode is cleared, and interrupt exception handling is started. When clearing software standby mode with an IRQ0 to IRQ5 interrupt, set the corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ5 is generated. Software standby mode cannot be cleared if the interrupt has been masked on the CPU side or has been designated as a DTC activation source. 698 * Clearing with the RES pin When the RES pin is driven low, clock oscillation is started. At the same time as clock oscillation starts, clocks are supplied to the entire chip. Note that the RES pin must be held low until clock oscillation stabilizes. When the RES pin goes high, the CPU begins reset exception handling. * Clearing with the STBY pin When the STBY pin is driven low, a transition is made to hardware standby mode. 21A.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode Bits STS2 to STS0 in SBYCR should be set as described below. Using a Crystal Oscillator: Set bits STS2 to STS0 so that the standby time is at least 8 ms (the oscillation stabilization time). Table 21A-4 shows the standby times for different operating frequencies and settings of bits STS2 to STS0. Table 21A-4 Oscillation Stabilization Time Settings STS2 STS1 STS0 Standby Time 0 0 0 1 1 0 1 1 0 0 1 1 0 1 8192 states 16384 states 32768 states 65536 states 131072 states 262144 states Reserved 16 states* 20 16 12 10 8 6 4 MHz MHz MHz MHz MHz MHz MHz Unit 0.41 0.51 0.68 0.8 0.82 1.0 1.6 3.3 6.6 2.0 4.1 8.2 1.3 2.7 5.5 1.6 3.3 6.6 1.0 2.0 4.1 8.2 1.3 2.7 5.5 2.0 4.1 8.2 ms 10.9 16.4 10.9 13.1 16.4 21.8 32.8 13.1 16.4 21.8 26.2 32.8 43.6 65.6 -- 0.8 -- 1.0 -- 1.3 -- 1.6 -- 2.0 -- 1.7 -- 4.0 s : Recommended time setting Note: * Do not use this setting. Using an External Clock: It is necessary to allow time for the PLL circuit to stabilize. Therefore, the standby time should be set to a value of 2 ms or greater. 699 21A.6.4 Software Standby Mode Application Example Figure 21A-3 shows an example in which a transition is made to software standby mode at the falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI pin. In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set to 1, and a SLEEP instruction is executed, causing a transition to software standby mode. Software standby mode is then cleared at the rising edge on the NMI pin. Oscillator o NMI NMIEG SSBY NMI exception Software standby mode handling (power-down mode) NMIEG=1 SSBY=1 SLEEP instruction Oscillation stabilization time tOSC2 NMI exception handling Figure 21A-3 Software Standby Mode Application Example 700 21A.6.5 Usage Notes I/O Port Status: In software standby mode, I/O port states are retained. If the OPE bit is set to 1, the address bus and bus control signal output is also retained. Therefore, there is no reduction in current dissipation for the output current when a high-level signal is output. Current Dissipation during Oscillation Stabilization Wait Period: Current dissipation increases during the oscillation stabilization wait period. Write Data Buffer Function: The write data buffer function and software standby mode cannot be used at the same time. When the write data buffer function is used, the WDBE bit in BCRL should be cleared to 0 to cancel the write data buffer function before entering software standby mode. Also check that external writes have finished, by reading external addresses, etc., before executing a SLEEP instruction to enter software standby mode. See section 7.7, Write Data Buffer Function, for details of the write data buffer function. 21A.7 Hardware Standby Mode 21A.7.1 Hardware Standby Mode When the STBY pin is driven low, a transition is made to hardware standby mode from any mode. In hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip RAM data is retained. I/O ports are set to the high-impedance state. In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before driving the STBY pin low. Do not change the state of the mode pins (MD2 to MD0) while the H8S/2623 Series is in hardware standby mode. Hardware standby mode is cleared by means of the STBY pin and the RES pin. When the STBY pin is driven high while the RES pin is low, the reset state is set and clock oscillation is started. Ensure that the RES pin is held low until the clock oscillator stabilizes (at least 8 ms--the oscillation stabilization time--when using a crystal oscillator). When the RES pin is subsequently driven high, a transition is made to the program execution state via the reset exception handling state. 701 21A.7.2 Hardware Standby Mode Timing Figure 21A-4 shows an example of hardware standby mode timing. When the STBY pin is driven low after the RES pin has been driven low, a transition is made to hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high, waiting for the oscillation stabilization time, then changing the RES pin from low to high. Oscillator RES STBY Oscillation stabilization time Reset exception handling Figure 21A-4 Hardware Standby Mode Timing 21A.8 o Clock Output Disabling Function Output of the o clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the corresponding port. When the PSTOP bit is set to 1, the o clock stops at the end of the bus cycle, and o output goes high. o clock output is enabled when the PSTOP bit is cleared to 0. When DDR for the corresponding port is cleared to 0, o clock output is disabled and input port mode is set. Table 21A-5 shows the state of the o pin in each processing state. Table 21A-5 o Pin State in Each Processing State DDR PSTOP Hardware standby mode Software standby Sleep mode High-speed mode, medium-speed mode 0 -- High impedance High impedance High impedance High impedance 1 0 High impedance Fixed high o output o output 1 1 High impedance Fixed high Fixed high Fixed high 702 Section 21B Power-Down Modes [H8S/2626 Series] 21B.1 Overview In addition to the normal program execution state, the H8S/2626 Series has nine power-down modes in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip supporting modules, and so on. The H8S/2626 operating modes are as follows: (1) High-speed mode (2) Medium-speed mode (3) Subactive mode* (4) Sleep mode (5) Subsleep mode* (6) Watch mode* (7) Module stop mode (8) Software standby mode (9) Hardware standby mode (2) to (9) are power-down modes. Sleep mode and sub-sleep mode are CPU states, medium-speed mode is a CPU and bus master state, sub-active mode is a CPU and bus master and internal peripheral function state, and module stop mode is an internal peripheral function (including bus masters other than the CPU) state. Some of these states can be combined. After a reset, the LSI is in high-speed mode with modules other than the DTC in module stop mode. Note: * Subclock functions are available in the H8S/2626 Series. See section 20.7, Subclock Oscillator, for the method of fixing pins OSC1 and OSC2 when not used. Table 21B-1 shows the internal state of the LSI in the respective modes. Table 21B-2 shows the conditions for shifting between the low power dissipation modes. Figure 21B-1 is a mode transition diagram. 703 Table 21B-1 LSI Internal States in Each Mode Function System clock pulse generator Subclock pulse generator CPU HighSpeed MediumSpeed Sleep Module Stop Watch Subactive Halted Software Hardware Subsleep Standby Standby Halted Halted Halted Function- Function- Function- Function- Halted ing ing ing ing Function- Function- Function- Function- Function- Function- Function- Function- Halted ing ing ing ing ing ing ing ing Instructions Function- Medium- Halted High/ Halted Subclock Halted Halted Halted Registers ing speed (retained) medium- (retained) operation (retained) (retained) (undefined) operation speed operation External NMI Function- Function- Function- Function- Function- Function- Function- Function- Halted interrupts ing ing ing ing ing ing ing ing IRQ0-IRQ5 Peripheral WDT1 functions WDT0 Function- Function- Function- ing ing ing Function- Function- Function ing ing ing Subclock Subclock Subclock Halted Halted operation operation operation (retained) (reset) Halted Subclock Subclock Halted Halted (retained) operation operation (retained) (reset) DTC Function- Medium- Function- Halted Halted Halted Halted Halted Halted ing speed ing (retained) (retained) (retained) (retained) (retained) (reset) operation Function- Function- Function- Halted Halted Halted Halted Halted Halted ing ing ing (retained) (retained) (retained) (retained) (retained) (reset) (PBC mediumspeed operation) Function- Function- Function- Halted ing ing ing (reset) Halted (reset) (PBC subclock operation) Halted (reset) Halted (reset) Halted (reset) Halted (reset) TPU PBC PPG D/A2, 3 SCI0 SCI1 SCI2 PWM A/D RAM I/O HCAN Function- Function- Function- Function- Retained Function- Retained Retained Retained ing ing ing (DTC) ing ing Function- Function- Function- Function- Retained Function- Retained Retained High ing ing ing ing ing impedance Function- Function- Function- Halted ing ing* ing (reset) Halted (reset) Halted (reset) Halted (reset) Halted (reset) Halted (reset) Notes: "Halted (retained)" means that internal register values are retained. The internal state is "operation suspended." "Halted (reset)" means that internal register values and internal states are initialized. In module stop mode, only modules for which a stop setting has been made are halted (reset or retained). * Note, however, that registers cannot be read or written to. 704 Program-halted state STBY pin = Low Reset state STBY pin = High RES pin = Low Hardware standby mode RES pin = High Program execution state SLEEP command High-speed mode (main clock) Any interrupt SCK2 to SCK0= 0 SCK2 to SCK0 0 SLEEP command SSBY= 1, PSS= 0, LSON= 0 Software standby mode SSBY= 0, LSON= 0 Sleep mode (main clock) Medium-speed mode (main clock) External interrupt *3 SLEEP command Interrupt *1 LSON bit = 0 SSBY= 1, PSS= 1, DTON= 0 Watch mode (subclock) SLEEP command SSBY = 1, PSS = 1 DTON = 1, LSON = 0 After the oscillation stabilization time (STS2 to 0), clock switching exception processing SLEEP command SSBY = 1, PSS = 1 DTON = 1, LSON = 1 Clock switching exception processing SLEEP command Interrupt *1 LSON bit = 1 SLEEP command Interrupt *2 SSBY= 0, PSS= 1, LSON= 1 Sub-sleep mode (subclock) Sub-active mode (subclock) : Transition after exception processing Notes: *1 NMI, IRQ0 to IRQ5, and WDT1 interrupts *2 NMI, IRQ0 to IRQ5, WDT0 interrupts, and WDT1 interrupt. *3 NMI and IRQ0 to IRQ5 : Low power dissipation mode * When a transition is made between modes by means of an interrupt, the transition cannot be made on interrupt source generation alone. Ensure that interrupt handling is performed after accepting the interrupt request. * From any state except hardware standby mode, a transition to the reset state occurs when RES is driven Low. * From any state, a transition to hardware standby mode occurs when STBY is driven low. * Always select high-speed mode before making a transition to watch mode or sub-active mode. Figure 21B-1 Mode Transition Diagram 705 Table 21B-2 Low Power Dissipation Mode Transition Conditions Status of Control Bit at Transition State After Transition State After Transition Back from Low Power Invoked by SLEEP Mode Invoked by LSON DTON Command Interrupt 0 1 0 1 0 1 0 1 * 0 1 * 0 1 0 1 * * * * 0 0 1 1 * * * * 0 0 1 1 Sleep -- Software standby -- Watch Watch -- Sub-active -- -- Sub-sleep -- Watch Watch High-speed -- High-speed/Medium-speed -- High-speed/Medium-speed -- High-speed Sub-active -- -- -- -- Sub-active -- High-speed Sub-active -- -- * : Don't care Pre-Transition State SSBY PSS High-speed/ 0 Medium-speed 0 1 1 1 1 1 1 Sub-active 0 0 0 1 1 1 1 1 --: Do not set. * * 0 0 1 1 1 1 0 1 1 0 1 1 1 1 706 21B.1.1 Register Configuration Power-down modes are controlled by the SBYCR, SCKCR, LPWRCR, TCSR (WDT1), and MSTPCR registers. Table 21B-3 summarizes these registers. Table 21B-3 Power-Down Mode Registers Name Standby control register System clock control register Low-power control register Timer control/status register Module stop control register A, B, C Abbreviation SBYCR SCKCR LPWRCR TCSR MSTPCRA MSTPCRB MSTPCRC Note: * Lower 16 bits of the address. R/W R/W R/W R/W R/W R/W R/W R/W Initial Value H'08 H'00 H'00 H'00 H'3F H'FF H'FF Address* H'FDE4 H'FDE6 H'FDEC H'FFA2 H'FDE8 H'FDE9 H'FDEA 707 21B.2 Register Descriptions 21B.2.1 Standby Control Register (SBYCR) Bit : 7 SSBY Initial value : R/W : 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 OPE 1 R/W 2 -- 0 -- 1 -- 0 -- 0 -- 0 -- SBYCR is an 8-bit readable/writable register that performs power-down mode control. SBYCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7--Software Standby (SSBY): When making a low power dissipation mode transition by executing the SLEEP instruction, the operating mode is determined in combination with other control bits. Note that the value of the SSBY bit does not change even when shifting between modes using interrupts. Bit 7 SSBY 0 Description Shifts to sleep mode when the SLEEP instruction is executed in high-speed mode or medium-speed mode. Shifts to sub-sleep mode when the SLEEP instruction is executed in sub-active mode. (Initial value) Shifts to software standby mode, sub-active mode, and watch mode when the SLEEP instruction is executed in high-speed mode or medium-speed mode. Shifts to watch mode or high-speed mode when the SLEEP instruction is executed in sub-active mode. 1 708 Bits 6 to 4--Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the MCU wait time for clock stabilization when shifting to high-speed mode or medium-speed mode by using a specific interrupt or command to cancel software standby mode, watch mode, or sub-active mode. With a quartz oscillator (table 21B-5), select a wait time of 8ms (oscillation stabilization time) or more, depending on the operating frequency. With an external clock, there are no specific wait requirements. Bit 6 STS2 0 Bit 5 STS1 0 Bit 4 STS0 0 1 1 0 1 1 0 0 1 1 0 1 Description Standby time = 8192 states Standby time = 16384 states Standby time = 32768 states Standby time = 65536 states Standby time = 131072 states Standby time = 262144 states Reserved Standby time = 16 states (Initial value) Bit 3--Output Port Enable (OPE): This bit specifies whether the output of the address bus and bus control signals (AS, RD, HWR, LWR) is retained or set to high-impedance state in the software standby mode, watch mode, and when making a direct transition. Bit 3 OPE 0 1 Description In software standby mode, watch mode, and when making a direct transition, address bus and bus control signals are high-impedance. In software standby mode, watch mode, and when making a direct transition, the output state of the address bus and bus control signals is retained. (Initial value) Bits 2 to 0--Reserved: These bits always return 0 when read, and cannot be written to. 709 21B.2.2 System Clock Control Register (SCKCR) Bit : 7 PSTOP Initial value : R/W : 0 R/W 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 STCS 0 R/W 2 SCK2 0 R/W 1 SCK1 0 R/W 0 SCK0 0 R/W SCKCR is an 8-bit readable/writable register that performs o clock output control and mediumspeed mode control. SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7--o Clock Output Disable (PSTOP): In combination with the DDR of the applicable port, this bit controls o output. See section 21B.12, o Clock Output Disable Function for details. Description Bit 7 PSTOP 0 1 High-Speed Mode, Medium-Speed Mode, Sleep Mode, Sub-Active Mode Sub-Sleep Mode o output (initial value) Fixed high o output Fixed high Software Standby Mode, Watch Mode, Hardware Standby Direct Transition Mode Fixed high Fixed high High impedance High impedance Bits 6 to 4--Reserved: These bits are always read as 0 and cannot be modified. Bit 3--Frequency Multiplication Factor Switching Mode Select (STCS): Selects the operation when the PLL circuit frequency multiplication factor is changed. Bit 3 STCS 0 1 Description Specified multiplication factor is valid after transition to software standby mode, watch mode, or subactive mode (Initial value) Specified multiplication factor is valid immediately after STC bits are rewritten 710 Bits 2 to 0--System clock select (SCK2 to SCK0): These bits select the bus master clock in high-speed mode, medium-speed mode, and sub-active mode. Set SCK2 to SCK0 all to 0 when shifting to operation in watch mode or sub-active mode. Bit 2 SCK2 0 Bit 1 SCK1 0 Bit 0 SCK0 0 1 1 0 1 1 0 0 1 1 -- Description Bus master in high-speed mode Medium-speed clock is o/2 Medium-speed clock is o/4 Medium-speed clock is o/8 Medium-speed clock is o/16 Medium-speed clock is o/32 -- (Initial value) 21B.2.3 Low-Power Control Register (LPWRCR) Bit : 7 DTON Initial value : R/W : 0 R/W 6 LSON 0 R/W 5 NESEL 0 R/W 4 3 2 -- 0 R/W 1 STC1 0 R/W 0 STC0 0 R/W SUBSTP RFCUT 0 R/W 0 R/W The LPWRCR is an 8-bit read/write register that controls the low power dissipation modes. The LPWRCR is initialized to H'00 at a reset and when in hardware standby mode. It is not initialized in software standby mode. The following describes bits 7 to 2. For details of other bits, see section 20.2.2, Low-Power Control Register (LPWRCR). Bit 7--Direct Transition ON Flag (DTON): When shifting to low power dissipation mode by executing the SLEEP instruction, this bit specifies whether or not to make a direct transition between high-speed mode or medium-speed mode and the sub-active modes. The selected operating mode after executing the SLEEP instruction is determined by the combination of other control bits. 711 Bit 7 DTON 0 Description * * 1 * When the SLEEP instruction is executed in high-speed mode or medium-speed mode, operation shifts to sleep mode, software standby mode, or watch mode*. When the SLEEP instruction is executed in sub-active mode, operation shifts to sub-sleep mode or watch mode. (Initial value) When the SLEEP instruction is executed in high-speed mode or medium-speed mode, operation shifts directly to sub-active mode*, or shifts to sleep mode or software standby mode. When the SLEEP instruction is executed in sub-active mode, operation shifts directly to high-speed mode, or shifts to sub-sleep mode. * Note: * Always set high-speed mode when shifting to watch mode or sub-active mode. Bit 6--Low-Speed ON Flag (LSON): When shifting to low power dissipation mode by executing the SLEEP instruction, this bit specifies the operating mode, in combination with other control bits. This bit also controls whether to shift to high-speed mode or sub-active mode when watch mode is cancelled. Bit 6 LSON 0 Description * * * 1 * * * When the SLEEP instruction is executed in high-speed mode or medium-speed mode, operation shifts to sleep mode, software standby mode, or watch mode*. When the SLEEP instruction is executed in sub-active mode, operation shifts to watch mode or shifts directly to high-speed mode. Operation shifts to high-speed mode when watch mode is cancelled. (Initial value) When the SLEEP instruction is executed in high-speed mode, operation shifts to watch mode or sub-active mode. When the SLEEP instruction is executed in sub-active mode, operation shifts to subsleep mode or watch mode. Operation shifts to sub-active mode when watch mode is cancelled. Note: * Always set high-speed mode when shifting to watch mode or sub-active mode. 712 Bit 5--Noise Elimination Sampling Frequency Select (NESEL): This bit selects the sampling frequency of the subclock (oSUB) generated by the subclock oscillator is sampled by the clock (o) generated by the system clock oscillator. Set this bit to 0 when o=5MHz or more. Bit 5 NESEL 0 1 Description Sampling using 1/32 xo Sampling using 1/4 xo (Initial value) Bit 4--Subclock enable (SUBSTP): This bit enables/disables subclock generation. Bit 4 SUBSTP Description 0 1 Enables subclock generation Disables subclock generation (Initial value) Bit 3--Oscillation Circuit Feedback Resistance Control Bit (RFCUT): This bit turns the internal feedback resistance of the main clock oscillation circuit ON/OFF. Bit 3 RFCUT 0 1 Description When the main clock is oscillating, sets the feedback resistance ON. When the main clock is stopped, sets the feedback resistance OFF. (Initial value) Sets the feedback resistance OFF. Bit 2--Reserved: Only write 0 to this bit. 21B.2.4 Timer Control/Status Register (TCSR) Bit : 7 OVF Initial value : R/W : 0 R/(W)* 6 WT/IT 0 R/W 5 TME 0 R/W 4 PSS 0 R/W 3 RST/NMI 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Note: * Only write 0 to clear the flag. TCSR is an 8-bit read/write register that selects the clock input to WDT1 TCNT and the mode. Here, we describe bit 4. For details of the other bits in this register, see section 12.2.2, Timer Control/Status Register (TCSR). 713 The TCSR is initialized to H'00 at a reset and when in hardware standby mode. It is not initialized in software standby mode. Bit 4--Prescaler select (PSS): This bit selects the clock source input to WDT1 TCNT. It also controls operation when shifting low power dissipation modes. The operating mode selected after the SLEEP instruction is executed is determined in combination with other control bits. For details, see the description for clock selection in section 12.2.2, Timer Control/Status Register (TCSR), and this section. Bit 4 PSS 0 Description * * 1 * * * TCNT counts the divided clock from the o -based prescaler (PSM). When the SLEEP instruction is executed in high-speed mode or medium-speed mode, operation shifts to sleep mode or software standby mode. (Initial value) TCNT counts the divided clock from the osubclock-based prescaler (PSS). When the SLEEP instruction is executed in high-speed mode or medium-speed mode, operation shifts to sleep mode, watch mode*, or sub-active mode*. When the SLEEP instruction is executed in sub-active mode*, operation shifts to subsleep mode*, watch mode*, or high-speed mode. Note: * Always set high-speed mode when shifting to watch mode or sub-active mode. 714 21B.2.5 Module Stop Control Register (MSTPCR) MSTPCRA Bit : 7 6 5 4 3 2 1 0 MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value : R/W MSTPCRB Bit : 7 6 5 4 3 2 1 0 : 0 R/W 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0 Initial value : R/W MSTPCRC Bit : 7 6 5 4 3 2 1 0 : 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 Initial value : R/W : 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W MSTPCR, comprising three 8-bit readable/writable registers, performs module stop mode control. MSTPCRA to MSTPCRC are initialized to H'3FFFFF by a reset and in hardware standby mode. They are not initialized in software standby mode. MSTPCRA/MSTPCRB/MSTPCRC Bits 7 to 0--Module Stop (MSTPA7 to MSTPA0, MSTPB7 to MSTPB0, MSTPC7 to MSTPC0): These bits specify module stop mode. See table 21B-4 for the method of selecting the on-chip peripheral functions. MSTPCRA/MSTPCRB/ MSTPCRC Bits 7 to 0 MSTPA7 to MSTPA0, MSTPB7 to MSTPB0, MSTPC7 to MSTPC0 0 1 Description Module stop mode is cleared (initial value of MSTPA7 and MSTPA6) Module stop mode is set (initial value of MSTPA5-0, MSTPB7-0, MSTPC7-0) 715 21B.3 Medium-Speed Mode In high-speed mode, when the SCK2 to SCK0 bits in SCKCR are set to 1, the operating mode changes to medium-speed mode as soon as the current bus cycle ends. In medium-speed mode, the CPU operates on the operating clock (o/2, o/4, o/8, o/16, or o/32) specified by the SCK2 to SCK0 bits. The bus masters other than the CPU (DTC) also operate in medium-speed mode. On-chip supporting modules other than the bus masters always operate on the high-speed clock (o). In medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. For example, if o/4 is selected as the operating clock, on-chip memory is accessed in 4 states, and internal I/O registers in 8 states. Medium-speed mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to high-speed mode and medium-speed mode is cleared at the end of the current bus cycle. If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, and LSON bit in LPWRCR is cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by an interrupt, medium-speed mode is restored. When the SLEEP instruction is executed with the SSBY bit = 1, LPWRCR LSON bit = 0, and TCSR (WDT1) PSS bit = 0, operation shifts to the software standby mode. When software standby mode is cleared by an external interrupt, medium-speed mode is restored. When the RES pin is set low and medium-speed mode is cancelled, operation shifts to the reset state. The same applies in the case of a reset caused by overflow of the watchdog timer. When the STBY pin is driven low, a transition is made to hardware standby mode. Figure 21B-2 shows the timing for transition to and clearance of medium-speed mode. Medium-speed mode o, supporting module clock Bus master clock Internal address bus SBYCR SBYCR Internal write signal Figure 21B-2 Medium-Speed Mode Transition and Clearance Timing 716 21B.4 Sleep Mode 21B.4.1 Sleep Mode When the SLEEP instruction is executed when the SBYCR SSBY bit = 0 and the LPWRCR LSON bit = 0, the CPU enters the sleep mode. In sleep mode, CPU operation stops but the contents of the CPUis internal registers are retained. Other supporting modules do not stop. 21B.4.2 Exiting Sleep Mode Sleep mode is exited by any interrupt, or signals at the RES, or STBY pins. Exiting Sleep Mode by Interrupts: When an interrupt occurs, sleep mode is exited and interrupt exception processing starts. Sleep mode is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the CPU. Exiting Sleep Mode by RES pin: Setting the RES pin level Low selects the reset state. After the stipulated reset input duration, driving the RES pin High starts the CPU performing reset exception processing. Exiting Sleep Mode by STBY Pin: When the STBY pin level is driven Low, a transition is made to hardware standby mode. 21B.5 Module Stop Mode 21B.5.1 Module Stop Mode Module stop mode can be set for individual on-chip supporting modules. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues operating independently. Table 21B-4 shows MSTP bits and the corresponding on-chip supporting modules. When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module starts operating at the end of the bus cycle. In module stop mode, the internal states of modules other than the SCI, A/D converter and HCAN are retained. After reset clearance, all modules other than DTC are in module stop mode. When an on-chip supporting module is in module stop mode, read/write access to its registers is disabled. 717 Table 21B-4 MSTP Bits and Corresponding On-Chip Supporting Modules Register MSTPCRA Bit MSTPA7* MSTPA6 MSTPA5 MSTPA4* MSTPA3 MSTPA2* MSTPA1 MSTPA0* MSTPCRB MSTPB7 MSTPB6 MSTPB5 MSTPB4* MSTPB3* MSTPB2* MSTPB1* MSTPB0* MSTPCRC MSTPC7* MSTPC6* MSTPC5 MSTPC4 MSTPC3 MSTPC2* MSTPC1* MSTPC0* Note: * MSTPA7 is a readable/writable bit with an initial value of 0. MSTPA4, MSTPA2, MSTPA0, MSTPB4 to MSTPB0, MSTPC7 to MSTPC4, and MSTPC2 to MSTPC0 are readable/writable bits with an initial value of 1 and should always be written with 1. D/A converter (channels 2, 3) PC break controller (PBC) HCAN Serial communication interface 0 (SCI0) Serial communication interface 1 (SCI1) Serial communication interface 2 (SCI2) A/D converter Programmable pulse generator (PPG) Data transfer controller (DTC) 16-bit timer pulse unit (TPU) Module 718 21B.5.2 Usage Notes DTC Module Stop: Depending on the operating status of the DTC, the MSTPA7 and MSTPA6 bits may not be set to 1. Setting of the DTC module stop mode should be carried out only when the respective module is not activated. For details, refer to section 8, Data Transfer Controller (DTC). On-Chip Supporting Module Interrupt: Relevant interrupt operations cannot be performed in module stop mode. Consequently, if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DTC activation source. Interrupts should therefore be disabled before entering module stop mode. Writing to MSTPCR: MSTPCR should only be written to by the CPU. 21B.6 Software Standby Mode 21B.6.1 Software Standby Mode A transition is made to software standby mode when the SLEEP instruction is executed when the SBYCR SSBY bit = 1 and the LPWRCR LSON bit = 0, and the TCSR (WDT1) PSS bit = 0. In this mode, the CPU, on-chip supporting modules, and oscillator all stop. However, the contents of the CPU's internal registers, RAM data, and the states of on-chip supporting modules other than the SCI, A/D converter, HCAN and I/O ports, are retained. Whether the address bus and bus control signals are placed in the high-impedance state or retain the output state can be specified by the OPE bit in SBYCR. In this mode the oscillator stops, and therefore power dissipation is significantly reduced. 21B.6.2 Clearing Software Standby Mode Software standby mode is cleared by an external interrupt (NMI pin, or pins IRQ0 to IRQ5), or by means of the RES pin or STBY pin. * Clearing with an interrupt When an NMI or IRQ0 to IRQ5 interrupt request signal is input, clock oscillation starts, and after the elapse of the time set in bits STS2 to STS0 in SYSCR, stable clocks are supplied to the entire chip, software standby mode is cleared, and interrupt exception handling is started. When clearing software standby mode with an IRQ0 to IRQ5 interrupt, set the corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ5 is generated. Software standby mode cannot be cleared if the interrupt has been masked on the CPU side or has been designated as a DTC activation source. 719 * Clearing with the RES pin When the RES pin is driven Low, clock oscillation is started. At the same time as clock oscillation starts, clocks are supplied to the entire chip. Note that the RES pin must be held Low until clock oscillation stabilizes. When the RES pin goes high, the CPU begins reset exception handling. * Clearing with the STBY pin When the STBY pin is driven Low, a transition is made to hardware standby mode. 21B.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode Bits STS2 to STS0 in SBYCR should be set as described below. Using a Crystal Oscillator: Set bits STS2 to STS0 so that the standby time is at least 8 ms (the oscillation stabilization time). Table 21B-5 shows the standby times for different operating frequencies and settings of bits STS2 to STS0. Table 21B-5 Oscillation Stabilization Time Settings STS2 STS1 STS0 Standby Time 0 0 0 1 1 0 1 1 0 0 1 1 0 1 8192 states 16384 states 32768 states 65536 states 131072 states 262144 states Reserved 16 states* 20 16 12 10 8 6 4 MHz MHz MHz MHz MHz MHz MHz Unit 0.41 0.51 0.68 0.8 0.82 1.0 1.6 3.3 6.6 2.0 4.1 8.2 1.3 2.7 5.5 1.6 3.3 6.6 1.0 2.0 4.1 8.2 1.3 2.7 5.5 2.0 4.1 8.2 ms 10.9 16.4 10.9 13.1 16.4 21.8 32.8 13.1 16.4 21.8 26.2 32.8 43.6 65.6 -- 0.8 -- 1.0 -- 1.3 -- 1.6 -- 2.0 -- 1.7 -- 4.0 s : Recommended time setting Note: * Do not use this setting. Using an External Clock: It is necessary to allow time for the PLL circuit to stabilize. Therefore, the standby time should be set to a value of 2 ms or greater. 720 21B.6.4 Software Standby Mode Application Example Figure 21B-3 shows an example in which a transition is made to software standby mode at the falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI pin. In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set to 1, and a SLEEP instruction is executed, causing a transition to software standby mode. Software standby mode is then cleared at the rising edge on the NMI pin. Oscillator o NMI NMIEG SSBY NMI exception Software standby mode handling (power-down mode) NMIEG=1 SSBY=1 SLEEP instruction Oscillation stabilization time tOSC2 NMI exception handling Figure 21B-3 Software Standby Mode Application Example 721 21B.6.5 Usage Notes I/O Port Status: In software standby mode, I/O port states are retained. If the OPE bit is set to 1, the address bus and bus control signal output is also retained. Therefore, there is no reduction in current dissipation for the output current when a high-level signal is output. Current Dissipation during Oscillation Stabilization Wait Period: Current dissipation increases during the oscillation stabilization wait period. Write Data Buffer Function: The write data buffer function and software standby mode cannot be used at the same time. When the write data buffer function is used, the WDBE bit in BCRL should be cleared to 0 to cancel the write data buffer function before entering software standby mode. Also check that external writes have finished, by reading external addresses, etc., before executing a SLEEP instruction to enter software standby mode. See section 7.7, Write Data Buffer Function, for details of the write data buffer function. 21B.7 Hardware Standby Mode 21B.7.1 Hardware Standby Mode When the STBY pin is driven low, a transition is made to hardware standby mode from any mode. In hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip RAM data is retained. I/O ports are set to the high-impedance state. In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before driving the STBY pin low. Do not change the state of the mode pins (MD2 to MD0) while the H8S/2626 Series is in hardware standby mode. Hardware standby mode is cleared by means of the STBY pin and the RES pin. When the STBY pin is driven high while the RES pin is low, the reset state is set and clock oscillation is started. Ensure that the RES pin is held low until the clock oscillator stabilizes (at least 8 ms--the oscillation stabilization time--when using a crystal oscillator). When the RES pin is subsequently driven high, a transition is made to the program execution state via the reset exception handling state. 722 21B.7.2 Hardware Standby Mode Timing Figure 21B-4 shows an example of hardware standby mode timing. When the STBY pin is driven low after the RES pin has been driven low, a transition is made to hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high, waiting for the oscillation stabilization time, then changing the RES pin from low to high. Oscillator RES STBY Oscillation stabilization time Reset exception handling Figure 21B-4 Hardware Standby Mode Timing 21B.8 Watch Mode 21B.8.1 Watch Mode CPU operation makes a transition to watch mode when the SLEEP instruction is executed in highspeed mode or sub-active mode with SBYCR SSBY=1, LPWRCR DTON = 0, and TCSR (WDT1) PSS = 1. In watch mode, the CPU is stopped and supporting modules other than WDT1 are also stopped. The contents of the CPU is internal registers, the data in internal RAM, and the statuses of the internal supporting modules (excluding the SCI, ADC, HCAN) and I/O ports are retained. 723 21B.8.2 Exiting Watch Mode Watch mode is exited by any interrupt (WOVI interrupt, NMI pin, or IRQ0 to IRQ5), or signals at the RES, or STBY pins. (1) Exiting Watch Mode by Interrupts When an interrupt occurs, watch mode is exited and a transition is made to high-speed mode or medium-speed mode when the LPWRCR LSON bit = 0 or to sub-active mode when the LSON bit = 1. When a transition is made to high-speed mode, a stable clock is supplied to all LSI circuits and interrupt exception processing starts after the time set in SBYCR STS2 to STS0 has elapsed. In the case of IRQ0 to IRQ5 interrupts, no transition is made from watch mode if the corresponding enable bit has been cleared to 0, and, in the case of interrupts from the internal supporting modules, the interrupt enable register has been set to disable the reception of that interrupt, or is masked by the CPU. See section 21B.6.3, Setting Oscillation Stabilization Time after clearing Software Standby Mode, for how to set the oscillation stabilization time when making a transition from watch mode to high-speed mode. (2) Exiting Watch Mode by RES pins For exiting watch mode by the RES pins, see, Clearing with the RES pins in section 21B.6.2, Clearing Software Standby Mode. (3) Exiting Watch Mode by STBY pin When the STBY pin level is driven Low, a transition is made to hardware standby mode. 21B.8.3 Notes (1) I/O Port Status The status of the I/O ports is retained in watch mode. Also, when the OPE bit is set to 1, the address bus and bus control signals continue to be output. Therefore, when a High level is output, the current consumption is not diminished by the amount of current to support the High level output. (2) Current Consumption when Waiting for Oscillation Stabilization The current consumption increases during stabilization of oscillation. 724 21B.9 Sub-Sleep Mode 21B.9.1 Sub-Sleep Mode When the SLEEP instruction is executed with the SBYCR SSBY bit = 0, LPWRCR LSON bit = 1, and TCSR (WDT1) PSS bit = 1, CPU operation shifts to sub-sleep mode. In sub-sleep mode, the CPU is stopped. Supporting modules other than WDT0, and WDT1 are also stopped. The contents of the CPUis internal registers, the data in internal RAM, and the statuses of the internal supporting modules (excluding the SCI, ADC, HCAN) and I/O ports are retained. 21B.9.2 Exiting Sub-Sleep Mode Sub-sleep mode is exited by an interrupt (interrupts from internal supporting modules, NMI pin, or IRQ0 to IRQ5), or signals at the RES or STBY pins. (1) Exiting Sub-Sleep Mode by Interrupts When an interrupt occurs, sub-sleep mode is exited and interrupt exception processing starts. In the case of IRQ0 to IRQ5 interrupts, sub-sleep mode is not cancelled if the corresponding enable bit has been cleared to 0, and, in the case of interrupts from the internal supporting modules, the interrupt enable register has been set to disable the reception of that interrupt, or is masked by the CPU. (2) Exiting Sub-Sleep Mode by RES For exiting sub-sleep mode by the RES pins, see, Clearing with the RES pins in section 21B.6.2, Clearing Software Standby Mode. (3) Exiting Sub-Sleep Mode by STBY Pin When the STBY pin level is driven Low, a transition is made to hardware standby mode. 725 21B.10 Sub-Active Mode 21B.10.1 Sub-Active Mode When the SLEEP instruction is executed in high-speed mode with the SBYCR SSBY bit = 1, LPWRCR DTON bit = 1, LSON bit = 1, and TCSR (WDT1) PSS bit = 1, CPU operation shifts to sub-active mode. When an interrupt occurs in watch mode, and if the LSON bit of LPWRCR is 1, a transition is made to sub-active mode. And if an interrupt occurs in sub-sleep mode, a transition is made to sub-active mode. In sub-active mode, the CPU operates at low speed on the subclock, and the program is executed step by step. Supporting modules other than WDT0, and WDT1 are also stopped. When operating the CPU in sub-active mode, the SCKCR SCK2 to SCK0 bits must be set to 0. 21B.10.2 Exiting Sub-Active Mode Sub-active mode is exited by the SLEEP instruction or the RES or STBY pins. (1) Exiting Sub-Active Mode by SLEEP Instruction When the SLEEP instruction is executed with the SBYCR SSBY bit = 1, LPWRCR DTON bit = 0, and TCSR (WDT1) PSS bit = 1, the CPU exits sub-active mode and a transition is made to watch mode. When the SLEEP instruction is executed with the SBYCR SSBY bit = 0, LPWRCR LSON bit = 1, and TCSR (WDT1) PSS bit = 1, a transition is made to sub-sleep mode. Finally, when the SLEEP instruction is executed with the SBYCR SSBY bit = 1, LPWRCR DTON bit = 1, LSON bit = 0, and TCSR (WDT1) PSS bit = 1, a direct transition is made to high-speed mode (SCK0 to SCK2 all 0). See section 21B.11, Direct Transitions, for details of direct transitions. (2) Exiting Sub-Active Mode by RES Pins For exiting sub-active mode by the RES pins, see, Claering with the RES pins in section 21B.6.2, Clearing Software Standby Mode. (3) Exiting Sub-Active Mode by STBY Pin When the STBY pin level is driven Low, a transition is made to hardware standby mode. 726 21B.11 Direct Transitions 21B.11.1 Overview of Direct Transitions There are three modes, high-speed, medium-speed, and sub-active, in which the CPU executes programs. When a direct transition is made, there is no interruption of program execution when shifting between high-speed and sub-active modes. Direct transitions are enabled by setting the LPWRCR DTON bit to 1, then executing the SLEEP instruction. After a transition, direct transition interrupt exception processing starts. (1) Direct Transitions from High-Speed Mode to Sub-Active Mode Execute the SLEEP instruction in high-speed mode when the SBYCR SSBY bit = 1, LPWRCR LSON bit = 1, and DTON bit = 1, and TSCR (WDT1) PSS bit = 1 to make a transition to subactive mode. (2) Direct Transitions from Sub-Active Mode to High-Speed Mode Execute the SLEEP instruction in sub-active mode when the SBYCR SSBY bit = 1, LPWRCR LSON bit = 0, and DTON bit = 1, and TSCR (WDT1) PSS bit = 1 to make a direct transition to high-speed mode after the time set in SBYCR STS2 to STS0 has elapsed. 21B.12 o Clock Output Disabling Function Output of the o clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the corresponding port. When the PSTOP bit is set to 1, the o clock stops at the end of the bus cycle, and o output goes high. o clock output is enabled when the PSTOP bit is cleared to 0. When DDR for the corresponding port is cleared to 0, o clock output is disabled and input port mode is set. Table 21B-6 shows the state of the o pin in each processing state. Table 21B-6 o Pin State in Each Processing State DDR PSTOP Hardware standby mode Software standby mode, watch mode, and direct transition Sleep mode and subsleep mode High-speed mode, medium-speed mode, and subactive mode 0 -- High impedance High impedance High impedance High impedance 1 0 High impedance Fixed high o output o output 1 1 High impedance Fixed high Fixed high Fixed high 727 21B.13 Usage Notes 1. When making a transition to sub-active mode or watch mode, set the DTC to enter module stop mode (write 1 to the relevant bits in MSTPCR), and then read the relevant bits to confirm that they are set to 1 before mode transition. Do not clear module stop mode (write 0 to the relevant bits in MSTPCR) until a transition from sub-active mode to high-speed mode or medium-speed mode has been performed. If a DTC activation source occurs in sub-active mode, the DTC will be activated only after module stop mode has been cleared and high-speed mode or medium-speed mode has been entered. 2. The on-chip peripheral modules (DTC and TPU) which halt operation in sub-active mode cannot clear an interrupt in sub-active mode. Therefore, if a transition is made to sub-active mode while an interrupt is requested, the CPU interrupt source cannot be cleared. Disable the interrupts of each on-chip peripheral module before executing a SLEEP instruction to enter sub-active mode or watch mode. 728 Section 22 Electrical Characteristics 22.1 Absolute Maximum Ratings Table 22-1 lists the absolute maximum ratings. Table 22-1 Absolute Maximum Ratings Item Power supply voltage Symbol VCC PLLVCC PVCC1-4 Input voltage (XTAL, EXTAL, OSC1, OSC2) Input voltage (port 4 and 9) Vin Vin -0.3 to +7.0 -0.3 to VCC +0.3 -0.3 to AVCC +0.3 -0.3 to PVCC +0.3 -0.3 to AVCC +0.3 -0.3 to +7.0 -0.3 to AVCC +0.3 Regular specifications: -20 to +75 Wide-range specifications: -40 to +85 Storage temperature Tstg -55 to +125 V V V V V V V C C C Value -0.3 to +4.3 -- Preliminary -- Unit V Input voltage (except port 4 and 9) Vin Reference voltage Analog power supply voltage Analog input voltage Operating temperature Vref AVCC VAN Topr Caution: Permanent damage to the chip may result if absolute maximum rating are exceeded. 729 22.2 DC Characteristics Table 22-2 lists the DC characteristics. Table 22-3 lists the permissible output currents. Table 22-2 DC Characteristics -- Preliminary -- Conditions: VCC = PLLVCC = 3.0 V to 3.6 V, PV CC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)*1 Item Schmitt trigger input voltage Input high voltage Symbol IRQ0 to IRQ5 VT- VT + + - Min -- Typ -- Max -- -- Unit V V Test Conditions PVCC x 0.2 -- PVCC x 0.05 -- PVCC x 0.9 -- PVCC x 0.7 V PVCC + 0.3 V VT - VT RES, STBY, VIH NMI, MD2 to MD0, FWE EXTAL, OSC1 Port 1, A to F, HRxD Port 4 and 9 VCC x 0.7 -- VCC + 0.3 V PVCC x 0.7 -- AVCC x 0.7 -- -0.3 -- PVCC + 0.3 V AVCC + 0.3 V PVCC x 0.1 V Input low voltage RES, STBY, VIL NMI, MD2 to MD0, FWE EXTAL, OSC1 Port 1, A to F, HRxD Port 4, 9 -0.3 -0.3 -0.3 -- -- -- VCC x 0.2 V PVCC x 0.2 V AVCC x 0.2 V -- -- 0.4 1.0 1.0 V V V A A I OH = -200 A I OH = -1 mA I OL = 1.6 mA Vin = 0.5 to PVCC - 0.5 V Output high voltage Output low voltage All output pins VOH All output pins VOL PVCC - 0.5 -- PVCC - 1.0 -- -- -- -- -- -- -- Input leakage RES | Iin | current STBY, NMI, HRxD, MD2 to MD0, FWE Port 4, 9 -- -- 1.0 A Vin = 0.5 to AVCC - 0.5 V 730 Item Three-state leakage current (off state) Symbol Port 1, A to F ITSI Min -- Typ -- Max 1.0 Unit A Test Conditions Vin = 0.5 to PVCC - 0.5 V MOS input Port A to E pull-up current Input capacitance RES NMI All input pins except RES and NMI Current dissipation* 2 Normal operation Sleep mode All modules stopped -I P Cin 30 -- -- -- -- -- -- -- 300 30 30 15 A pF pF pF Vin = 0 V Vin = 0 V f = 1 MHz Ta = 25C I CC* 4 -- -- -- 55 65 mA VCC = 3.3 V VCC = 3.6 V 40 50 mA VCC = 3.3 V VCC = 3.6 V 40 -- mA f = 20 MHz f = 20 MHz f = 20 MHz, VCC = 3.3 V (reference values) f = 20 MHz, VCC = 3.3 V (reference values) Using 32.768 kHz crystal resonator Using 32.768 kHz crystal resonator Using 32.768 kHz crystal resonator Ta 50C 50C < Ta Medium-speed mode (o/32) -- 30 -- mA Subactive mode Subsleep mode Watch mode -- 90 VCC = 3.3 V 200 A -- 60 VCC = 3.3 V 120 A -- 12 VCC = 3.3 V 30 A Standby mode* 3 -- -- 2.0 -- 5.0 20 A A 731 Item Port power supply current During operation Symbol PI CC Min -- Typ 15 PVCC = 5.0 V Max 20 PVCC = 5.5 V 5.0 PVCC = 5.5 V Unit mA Test Conditions In standby mode* 3 -- -- A During A/D Analog power supply and D/A conversion current Idle Reference During A/D power supply and D/A current conversion Idle RAM standby voltage AlCC -- 1.0 2.0 mA AVCC = 5.0 V -- AlCC -- -- 2.5 5.0 4.0 A mA Vref = 5.0 V -- VRAM 2.0 -- -- 5.0 -- A V Notes: *1 If the A/D and D/A converter is not used, do not leave the AVCC, Vref , and AV SS pins open. Apply a voltage between 4.5 V and 5.5 V to the AV CC and Vref pins by connecting them to PV CC, for instance. Set Vref AV CC. *2 Current dissipation values are for V IH = VCC (EXTAL, OSC1), AVCC (ports 4 and 9), or PVCC (other), and VIL = 0 V, with all output pins unloaded and the on-chip MOS pull-up transistors in the off state. *3 The values are for VRAM PV CC < 3.0 V, VIH min = VCC - 0.1 V, and VIL max = 0.1 V. *4 I CC depends on VCC and f as follows: I CC max = 8.0 (mA) + 0.8 (mA/(MHz x V)) x V CC x f (normal operation) I CC max = 8.0 (mA) + 0.58 (mA/(MHz x V)) x V CC x f (sleep mode) *5 Applies to the mask ROM version only. 732 Table 22-3 Permissible Output Currents -- Preliminary -- Conditions: VCC = PLLVCC = 3.0 V to 3.6 V, PV CC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)* Item Permissible output low current (per pin) Permissible output low current (total) All output pins Total of all output pins PVCC = 4.5 V to 5.5 V PVCC = 4.5 V to 5.5 V PVCC = 4.5 V to 5.5 V PVCC = 4.5 V to 5.5 V Symbol Min I OL IOL -I OH -IOH -- -- -- -- Typ -- -- -- -- Max 10 100 2.0 30 Unit mA mA mA mA Permissible output All output high current (per pin) pins Permissible output high current (total) Total of all output pins Note: * To protect chip reliability, do not exceed the output current values in table 22-3. 22.3 AC Characteristics Figure 22-1 show, the test conditions for the AC characteristics. 3V RL LSI output pin C RH C = 50 pF: Ports 10 to 13, A to F (In case of expansion bus control signal output pin setting) C = 30 pF: All ports RL = 2.4 k RH = 12 k Input/output timing measurement levels * Low level : 0.8 V * High level : 2.0 V Figure 22-1 Output Load Circuit 733 22.3.1 Clock Timing Table 22-4 lists the clock timing Table 22-4 Clock Timing -- Preliminary -- Conditions : VCC = PLLVCC = 3.0 V to 3.6 V, PV CC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, o = 32.768 kHz, 4 to 20 MHz, T a = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Clock cycle time Clock high pulse width Clock low pulse width Clock rise time Clock fall time Oscillation stabilization time at reset (crystal) Oscillation stabilization time in software standby (crystal) External clock output stabilization delay time 32 kHz clock oscillation settling time Sub clock oscillator frequency Sub clock (oSUB) cycle time Symbol t cyc t CH t CL t Cr t Cf t OSC1 t OSC2 t DEXT t OSC3 f SUB t SUB Min 50 15 15 -- -- 20 8 2 -- 32.768 30.5 Max 250 -- -- 5 5 -- -- -- 2 -- -- Unit ns ns ns ns ns ms ms ms s kHz s Figure 22-3 Figure 21A-3, Figure 21B-3 Figure 22-3 Test Conditions Figure 22-2 tcyc tCH o tCL tCr tCf Figure 22-2 System Clock Timing 734 EXTAL tDEXT VCC tDEXT STBY tOSC1 RES tOSC1 o Figure 22-3 Oscillation Stabilization Timing 22.3.2 Control Signal Timing Table 22-5 lists the control signal timing. Table 22-5 Control Signal Timing Conditions: VCC = PLLVCC = 3.0 V to 3.6 V, PV CC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, o = 32.768 kHz, 4 to 20 MHz, T a = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item RES setup time RES pulse width NMI setup time NMI hold time NMI pulse width (exiting software standby mode) IRQ setup time IRQ hold time IRQ pulse width (exiting software standby mode) Symbol t RESS t RESW t NMIS t NMIH t NMIW t IRQS t IRQH t IRQW Min 200 20 150 10 200 150 10 200 Max -- -- -- -- -- -- -- -- ns ns ns ns Unit ns t cyc ns Figure 22-5 Test Conditions Figure 22-4 735 o tRESS RES tRESW tRESS Figure 22-4 Reset Input Timing o tNMIS NMI tNMIW tNMIH IRQi (i = 0 to 2) tIRQW tIRQS IRQ Edge input tIRQS IRQ Level input tIRQH Figure 22-5 Interrupt Input Timing 736 22.3.3 Bus Timing Table 22-6 lists the bus timing. Table 22-6 Bus Timing -- Preliminary -- Conditions: VCC = PLLVCC = 3.0 V to 3.6 V, PV CC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, o = 32.768 kHz, 4 to 20 MHz, T a = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Address delay time Address setup time Address hold time AS delay time RD delay time 1 RD delay time 2 Read data setup time Read data hold time Read data access time1 Read data access time2 Read data access time3 Read data access time 4 Read data access time 5 WR delay time 1 WR delay time 2 WR pulse width 1 WR pulse width 2 Write data delay time Write data setup time Write data hold time WAIT setup time WAIT hold time Symbol t AD t AS t AH t ASD t RSD1 t RSD2 t RDS t RDH t ACC1 t ACC2 t ACC3 t ACC4 t ACC5 t WRD1 t WRD2 t WSW1 t WSW2 t WDD t WDS t WDH t WTS t WTH Min -- Max 25 Unit ns ns ns ns ns ns ns ns Test Conditions Figure 22-6 to Figure 22-10 0.5 x tcyc - 20 -- 0.5 x tcyc - 15 -- -- -- -- 15 0 -- -- -- -- -- -- -- 20 20 20 -- -- 1.0 x tcyc - 35 ns 1.5 x tcyc - 25 ns 2.0 x tcyc - 35 ns 2.5 x tcyc - 25 ns 3.0 x tcyc - 35 ns 20 20 ns ns ns ns ns ns ns ns ns Figure 22-8 1.0 x tcyc - 20 -- 1.5 x tcyc - 20 -- -- 30 0.5 x tcyc - 20 -- 0.5 x tcyc - 10 -- 30 5 -- -- 737 Item BREQ setup time BACK delay time Bus-floating time BREQO delay time Symbol t BRQS t BACD t BZD t BRQOD Min 30 -- -- -- Max -- 15 50 25 Unit ns ns ns ns Test Conditions Figure 22-11 Figure 22-12 T1 T2 o tAD A23 to A0 tAS tASD AS tASD tAH tRSD1 RD (read) tACC2 tRSD2 tAS tACC3 tRDS tRDH D15 to D0 (read) tWRD2 HWR, LWR (write) tWRD2 tAH tAS tWDD tWSW1 tWDH D15 to D0 (write) Figure 22-6 Basic Bus Timing (Two-State Access) 738 T1 T2 T3 o tAD A23 to A0 tAS tASD AS tRSD1 RD (read) tASD tAH tACC4 tRSD2 tAS tACC5 tRDS tRDH D15 to D0 (read) tWRD1 HWR, LWR (write) tWDD tWDS D15 to D0 (write) tWSW2 tWRD2 tAH tWDH Figure 22-7 Basic Bus Timing (Three-State Access) 739 T1 T2 TW T3 o A23 to A0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tWTS tWTH WAIT tWTS tWTH Figure 22-8 Basic Bus Timing (Three-State Access with One Wait State) 740 T1 T2 or T3 T1 T2 o tAD A23 to A0 tAS tAH tASD tASD AS tRSD2 RD (read) tACC3 D15 to D0 (read) tRDS tRDH Figure 22-9 Burst ROM Access Timing (Two-State Access) T1 o T2 or T3 T1 tAD A23 to A0 AS tRSD2 RD (read) tACC1 D15 to D0 (read) tRDS tRDH Figure 22-10 Burst ROM Access Timing (One-State Access) 741 o tBRQS tBRQS BREQ tBACD BACK tBZD A23 to A0, AS, RD, HWR, LWR tBACD tBZD Figure 22-11 External Bus Release Timing o tBRQOD BREQO tBRQOD Figure 22-12 External Bus Request Output Timing 742 22.3.4 Timing of On-Chip Supporting Modules Table 22-7 lists the timing of on-chip supporting modules. Table 22-7 Timing of On-Chip Supporting Modules -- Preliminary -- Conditions: VCC = PLLVCC = 3.0 V to 3.6 V, PV CC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, o = 32.768 kHz, 4 to 20 MHz, T a = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item I/O port Output data delay time Symbol t PWD Min -- 30 30 -- 30 30 1.5 2.5 4 6 t SCKW t SCKr t SCKf t TXD t RXS t RXH 0.4 -- -- -- 50 50 Max 50 -- -- 50 -- -- -- -- -- -- 0.6 1.5 1.5 50 -- -- ns Figure 22-17 t Scyc t cyc t cyc Figure 22-16 ns t cyc Figure 22-15 ns Figure 22-14 Unit ns Test Conditions Figure 22-13 Input data setup time t PRS Input data hold time TPU Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width SCI Input clock cycle Single edge Both edges t PRH t TOCD t TICS t TCKS t TCKWH t TCKWL Asynchro- t Scyc nous Synchronous Input clock pulse width Input clock rise time Input clock fall time Transmit data delay time Receive data setup time (synchronous) Receive data hold time (synchronous) 743 Item A/D Trigger input setup converter time HCAN* Transmit data delay time Transmit data setup time Transmit data hold time PPG WDT0 WDT1 Pulse output delay time Symbol t TRGS t HTXD t HRXS t HRXH t POD Min 30 -- 100 100 -- -- -- Max -- 100 -- -- 50 50 50 Unit ns ns Test Conditions Figure 22-18 Figure 22-19 ns ns ns Figure 22-20 Figure 22-21 Figure 22-22 Overflow output delay t WOVD time Buzz output delay time t BUZD Note: * The HCAN input signal is asynchronous. However, its state is judged to have changed at the leading edge (two clock cycles) of the CK clock signal shown in figure 22-19. The HCAN output signal is also asynchronous. Its state changes based on the leading edge (two clock cycles) of the CK clock signal shown in figure 22-19. T1 o T2 tPRS Port 1, 4, 9 A to F (read) tPRH tPWD Port 1, A to F (write) Figure 22-13 I/O Port Input/Output Timing 744 o tTOCD Output compare output* tTICS Input capture input* Note: * TIOCA0 to TIOCA5, TIOCB0 to TIOCB5, TIOCC0, TIOCC3, TIOCD0, TIOCD3 Figure 22-14 TPU Input/Output Timing o tTCKS TCLKA to TCLKD tTCKWL tTCKWH tTCKS Figure 22-15 TPU Clock Input Timing tSCKW SCK0 to SCK3 tScyc tSCKr tSCKf Figure 22-16 SCK Clock Input Timing 745 SCK0 to SCK3 tTXD TxD0 to TxD3 (transit data) tRXS RxD0 to RxD3 (receive data) tRXH Figure 22-17 SCI Input/Output Timing (Clock Synchronous Mode) o tTRGS ADTRG Figure 22-18 A/D Converter External Trigger Input Timing (Preliminary) VOL CK tHTXD TX (transmit data ) tHRXS RX (receive data) tHRXH VOL Figure 22-19 HCAN Input/Output Timing o tPOD PO15 to 8 Figure 22-20 PPG Output Timing 746 o tWOVD WDTOVF tWOVD Figure 22-21 WDT0 Output Timing o tBUZD BUZZ tBUZD Figure 22-22 WDT1 Output Timing 22.4 A/D Conversion Characteristics Table 22-8 lists the A/D conversion characteristics. Table 22-8 A/D Conversion Characteristics -- Preliminary -- Conditions: VCC = PLLVCC = 3.0 V to 3.6 V, PV CC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, o = 4 to 20 MHz, Ta = -20C to +75C (regular specifications), T a = -40C to +85C (wide-range specifications) Item Resolution Conversion time Min 10 -- 10 Analog input capacitance Permissible signal-source impedance Nonlinearity error Offset error Full-scale error Quantization Absolute accuracy -- -- -- -- -- -- -- Typ 10 -- -- -- -- -- -- -- 0.5 -- Max 10 -- -- 20 5 3.5 3.5 3.5 -- 4.0 pF k LSB LSB LSB LSB LSB 747 Unit bits s AVCC < 4.5 V AVCC 4.5 V Test Conditions 22.5 D/A Conversion Characteristics Table 22-9 shows the D/A conversion characteristics. Table 22-9 D/A Conversion Characteristics Conditions: VCC = PLLVCC = 3.0 V to 3.6 V, PV CC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, o = 4 to 20 MHz, Ta = -20C to +75C (regular specifications), T a = -40C to +85C (wide-range specifications) Item Resolution Conversion time Absolute accuracy Min 8 -- -- -- Typ 8 -- 1.5 -- Max 8 10 2.0 1.5 Unit bits s LSB LSB 20-pF capacitive load 2-M resistive load 4-M resistive load Test Conditions 748 22.6 Flash Memory Characteristics Table 22-9 Flash Memory Characteristics Conditions: VCC = 3.0 to 3.6 V, AVCC = 4.5 to 5.5 V, VSS = AVSS = 0 V, Ta = -20 to +75C (regular specifications), T a = -40 to +85C (wide-range specifications) Item Programming time* * * Erase time*1 *3 *5 Number of rewrites Programming Wait time after SWE1 bit setting*1 Wait time after PSU1 bit setting* Wait time after P1 bit setting*1 *4 1 1 2 4 Symbol tP tE NWEC x0 y z0 z1 z2 Wait time after P1 bit clearing* 1 Min -- -- -- 1 50 -- -- -- 5 5 4 2 2 -- -- 100 1 100 -- 10 10 6 2 4 -- Typ 10 100 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max 200 1000 100 -- -- 30 10 200 -- -- -- -- -- 6 994 -- -- -- 10 -- -- -- -- -- 100 Unit ms/128 bytes ms/block Times s s s s s s s s s s Times Times s s s ms s s s s s Times N1 N2 1 Wait time after PSU1 bit clearing*1 Wait time after PV1 bit setting* 1 Wait time after H'FF dummy write*1 Wait time after PV1 bit clearing* Maximum number of writes*1 *4 Wait time after SWE1 bit clearing*1 Wait time after SWE1 bit setting* 1 5 1 Common Erasing x1 x y z Wait time after ESU1 bit setting*1 Wait time after E1 bit setting* * Wait time after E1 bit clearing*1 Wait time after ESU1 bit clearing* Wait time after EV1 bit setting*1 Wait time after H'FF dummy write* Wait time after EV1 bit clearing*1 Maximum number of erases* * Notes: 1 5 1 1 N *1 Follow the program/erase algorithms when making the time settings. *2 Programming time per 128 bytes. (Indicates the total time during which the P1 bit is set in flash memory control register 1 (FLMCR1). Does not include the program-verify time.) *3 Time to erase one block. (Indicates the time during which the E1 bit is set in FLMCR1. Does not include the erase-verify time.) *4 Maximum programming time (tP(max) = Wait time after P1 bit setting (z) x maximum number of writes (N)) (z0 + z1) x 6 + z2 x 994 *5 Maximum erase time (tE(max) = Wait time after E1 bit setting (z) x maximum number of erases (N)) 749 22.7 Usage Note Although both the F-ZTAT and mask ROM versions fully meet the electrical specifications listed in this manual, there may be differences in the actual values of the electrical characteristics, operating margins, noise margins, and so forth, due to differences in the fabrication process, the on-chip ROM, and the layout patterns. Therefore, if a system is evaluated using the F-ZTAT version, a similar evaluation should also be performed using the mask ROM version. 750 Appendix A Instruction Set A.1 Instruction List Operand Notation Rd Rs Rn ERn MAC (EAd) (EAs) EXR CCR N Z V C PC SP #IMM disp + - x / ( ) <> :8/:16/:24/:32 General register (destination)* General register (source)* General register* General register (32-bit register) Multiply-and-accumulate register (32-bit register) Destination operand Source operand Extended control register Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Add Subtract Multiply Divide Logical AND Logical OR Logical exclusive OR Transfer from the operand on the left to the operand on the right, or transition from the state on the left to the state on the right Logical NOT (logical complement) Contents of operand 8-, 16-, 24-, or 32-bit length Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). 751 Condition Code Notation Symbol Changes according to the result of instruction * 0 1 -- Undetermined (no guaranteed value) Always cleared to 0 Always set to 1 Not affected by execution of the instruction 752 Table A-1 Addressing Mode/ Instruction Length (Bytes) Condition Code -- Operation #xx:8Rd8 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- Rs8@aa:16 Rs8@aa:32 #xx:16Rd16 ---- ---- ---- Rs16Rd16 ---- @ERsRd16 ---- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- IHNZVC No. of States*1 Advanced 1 1 2 3 5 3 2 3 4 2 3 5 3 2 3 4 2 1 2 Operand Size #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa Rs8Rd8 Mnemonic B2 B B B B B B B B B B B B B B B W4 W W 2 2 6 4 2 2 8 4 2 Rs8@ERd Rs8@(d:16,ERd) Rs8@(d:32,ERd) ERd32-1ERd32,Rs8@ERd Rs8@aa:8 6 @aa:32Rd8 4 @aa:16Rd8 2 @aa:8Rd8 2 @ERsRd8,ERs32+1ERs32 8 @(d:32,ERs)Rd8 4 @(d:16,ERs)Rd8 2 @ERsRd8 2 MOV MOV.B #xx:8,Rd Instruction Set MOV.B Rs,Rd (1) Data Transfer Instructions MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W @ERs,Rd MOV.W Rs,Rd 753 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa Mnemonic Operation @(d:16,ERs)Rd16 @(d:32,ERs)Rd16 2 4 6 2 4 8 2 4 6 Rs16@(d:16,ERd) Rs16@(d:32,ERd) Rs16@ERd @aa:32Rd16 @aa:16Rd16 ---- ---- W W W W W W W W W W W L6 L L L L L L L 10 4 6 8 6 4 2 8 @ERsRd16,ERs32+2ERs32 -- -- ---- ---- ---- ---- ---- 4 -- MOV.L @aa:32,ERd @aa:32ERd32 ---- 754 Addressing Mode/ Instruction Length (Bytes) Condition Code IHNZVC 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- ---- ---- ---- ERs32ERd32 @ERsERd32 @(d:16,ERs)ERd32 @(d:32,ERs)ERd32 ---- ---- ---- ---- @ERsERd32,ERs32+4ERs32 -- -- @aa:16ERd32 ---- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- Advanced 3 5 3 3 4 2 3 5 3 3 4 3 1 4 5 7 5 5 6 ERd32-2ERd32,Rs16@ERd -- -- Rs16@aa:16 Rs16@aa:32 #xx:32ERd32 No. of States*1 MOV MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16,ERd Addressing Mode/ Instruction Length (Bytes) Condition Code -- Operation ERs32@ERd ---- ---- ---- IHNZVC 0-- 0-- 0-- 0-- ---- ---- ---- ---- ---- ---- 0-- 0-- 0-- 0-- 0-- 0-- ------------ Repeated for each register restored No. of States*1 Advanced 4 5 7 5 5 6 3 5 3 5 7/9/11 [1] Operand Size #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa ERs32@(d:16,ERd) ERs32@(d:32,ERd) 4 6 8 2 4 2 4 4 ERs32@aa:32 @SPRn16,SP+2SP @SPERn32,SP+4SP SP-2SP,Rn16@SP SP-4SP,ERn32@SP (@SPERn32,SP+4SP) ERs32@aa:16 ERd32-4ERd32,ERs32@ERd -- -- Mnemonic L 6 10 4 MOV MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) L MOV.L ERs,@(d:32,ERd) L L L L W L W L L MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 POP POP.W Rn POP.L ERn PUSH.L ERn LDM LDM @SP+,(ERm-ERn) STM L STM (ERm-ERn),@-SP 4 (SP-4SP,ERn32@SP) Repeated for each register saved ------------ PUSH PUSH.W Rn 7/9/11 [1] MOVFPE MOVFPE @aa:16,Rd Cannot be used in the H8S/2626 Series or H8S/2623 Series Cannot be used in the H8S/2626 Series or H8S/2623 Series [2] [2] MOVTPE MOVTPE Rs,@aa:16 755 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa -- ADDX Rs,Rd L L L B W W L L B B W4 2 2 2 2 2 2 2 2 2 2 ERd32+1ERd32 ERd32+2ERd32 ERd32+4ERd32 Rd8+1Rd8 Rd16+1Rd16 Rd16+2Rd16 ERd32+1ERd32 ERd32+2ERd32 B 2 Rd8+Rs8+CRd8 -- [5] -- -- -- [3] SUB SUB.B Rs,Rd Rd8-Rs8Rd8 Rd16-#xx:16Rd16 -- SUB.W #xx:16,Rd -- [3] 756 Addressing Mode/ Instruction Length (Bytes) Condition Code Operation Rd8+#xx:8Rd8 2 Rd16+#xx:16Rd16 2 ERd32+#xx:32ERd32 2 Rd8+#xx:8+CRd8 ERd32+ERs32ERd32 Rd16+Rs16Rd16 -- [3] Rd8+Rs8Rd8 IHNZVC No. of States*1 Advanced 1 1 2 1 -- [4] 3 -- [4] -- 1 [5] 1 1 ---- -- ---- -- ---- -- ---- -- ---- -- ---- -- ---- ---- ---- ---- ---- Rd8 decimal adjustRd8 --* -- -- -- -- -- * 1 1 1 1 1 1 1 1 1 1 2 B2 B W4 W L6 L B2 Mnemonic ADD ADD.B #xx:8,Rd (2) Arithmetic Instructions ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDX ADDX #xx:8,Rd ADDS ADDS #1,ERd ADDS #2,ERd ADDS #4,ERd INC INC.B Rd INC.W #1,Rd INC.W #2,Rd INC.L #1,ERd INC.L #2,ERd DAA DAA Rd Addressing Mode/ Instruction Length (Bytes) Condition Code -- Operation Rd16-Rs16Rd16 ERd32-#xx:32ERd32 -- [4] -- [3] IHNZVC No. of States*1 Advanced 1 3 1 Operand Size #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa ERd32-ERs32ERd32 Rd8-#xx:8-CRd8 Mnemonic W L6 L B2 B L L L B W W L L B B W 2 2 2 2 2 2 2 2 Rd8-1Rd8 Rd16-1Rd16 Rd16-2Rd16 ERd32-1ERd32 ERd32-2ERd32 Rd8 decimal adjustRd8 2 2 ERd32-2ERd32 ERd32-4ERd32 2 ERd32-1ERd32 2 Rd8-Rs8-CRd8 2 -- [4] -- -- 2 SUB SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd [5] [5] SUBX SUBX #xx:8,Rd 1 1 ------------ ------------ ------------ ---- ---- ---- ---- ---- --* -- -- -- -- -- *-- 1 1 1 1 1 1 1 1 1 SUBX Rs,Rd SUBS SUBS #1,ERd SUBS #2,ERd SUBS #4,ERd DEC DEC.B Rd DEC.W #1,Rd DEC.W #2,Rd DEC.L #1,ERd DAS DAS Rd MULXU MULXU.B Rs,Rd Rd8xRs8Rd16 (unsigned multiplication) -- -- -- -- -- -- Rd16xRs16ERd32 (unsigned multiplication) ------------ DEC.L #2,ERd 3 4 MULXU.W Rs,ERd MULXS B W MULXS.B Rs,Rd 4 4 Rd8xRs8Rd16 (signed multiplication) Rd16xRs16ERd32 (signed multiplication) ---- ---- ---- ---- 4 5 MULXS.W Rs,ERd 757 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa Mnemonic Operation B RdL: quotient) (unsigned division) W Rd: quotient) (unsigned division) B 4 2 2 -- NEG.L ERd W L 2 2 L 2 0-ERd32ERd32 0( -- EXTU.L ERd ---- 0 758 Addressing Mode/ Instruction Length (Bytes) Condition Code IHNZVC Advanced 12 Rd16/Rs8Rd16 (RdH: remainder, -- -- [6] [7] -- -- ERd32/Rs16ERd32 (Ed: remainder, -- -- [6] [7] -- -- 20 Rd16/Rs8Rd16 (RdH: remainder, -- -- [8] [7] -- -- RdL: quotient) (signed division) W Rd8-#xx:8 2 Rd8-Rs8 Rd16-#xx:16 2 Rd16-Rs16 ERd32-#xx:32 2 2 2 ERd32-ERs32 0-Rd8Rd8 0-Rd16Rd16 4 ERd32/Rs16ERd32 (Ed: remainder, -- -- [8] [7] -- -- Rd: quotient) (signed division) B2 B W4 W L6 L B W -- -- 1 1 -- [3] 2 -- [3] 1 -- [4] 3 -- [4] -- -- 1 1 1 1 ---- 0 0-- 0-- 1 1 21 13 No. of States*1 DIVXU DIVXU.B Rs,Rd DIVXU.W Rs,ERd DIVXS divxs.B Rs,Rd DIVXS.W Rs,ERd CMP CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd NEG NEG.B Rd NEG.W Rd EXTU EXTU.W Rd Addressing Mode/ Instruction Length (Bytes) Condition Code -- Operation ( No. of States*1 Advanced 1 Operand Size #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa ( Mnemonic W ---- 2 EXTS EXTS.W Rd EXTS.L ERd @ERd-0CCR set, (1) ( L 2 0-- 1 TAS B 4 TAS @ERd *3 MAC MAC @ERn+,@ERm+ -- ---- -- -- -- [10] [10] [10] ---- 0-- 4 4 CLRMAC CLRMAC -- ---- -- -- -- -- ---- -- -- -- -- ---- -- -- -- ---- ---- -- -- 2 [11] 2 [11] 2 [11] 1 [11] 1 [11] LDMAC LDMAC ERs,MACH LDMAC ERs,MACL STMAC STMAC MACH,ERd STMAC MACL,ERd 759 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa Mnemonic Operation Rd8#xx:8Rd8 2 Rd16#xx:16Rd16 2 ERd32#xx:32ERd32 4 Rd8#xx:8Rd8 2 Rd16Rs16Rd16 ERd32#xx:32ERd32 4 ERd32ERs32ERd32 Rd8#xx:8Rd8 2 Rd8Rs8Rd8 Rd16#xx:16Rd16 2 Rd16Rs16Rd16 ERd32#xx:32ERd32 4 2 2 2 ERd32ERs32ERd32 Rd8Rd8 Rd16Rd16 ERd32ERd32 L Rd8Rs8Rd8 Rd16#xx:16Rd16 2 ERd32ERs32ERd32 Rd16Rs16Rd16 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- Rd8Rs8Rd8 ---- ---- B2 B W4 W L6 L B2 B W4 W L6 L B2 B W4 W L6 L B W -- 760 Addressing Mode/ Instruction Length (Bytes) Condition Code IHNZVC 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- No. of States*1 Advanced 1 1 2 1 3 2 1 1 2 1 3 2 1 1 2 1 3 2 1 1 1 (3) Logical Instructions AND AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd OR OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd XOR XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd NOT NOT.B Rd NOT.W Rd NOT.L ERd Addressing Mode/ Instruction Length (Bytes) Condition Code -- Operation ---- ---- 0 C MSB LSB ---- ---- ---- ---- ---- ---- ---- MSB LSB C ---- ---- ---- ---- ---- 0 C MSB LSB ---- ---- ---- ---- IHNZVC No. of States*1 Advanced 1 1 1 1 1 1 Operand Size #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa (4) Shift Instructions Mnemonic B B W W L L B B W W L L B B W W L L 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 SHAL SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR SHAR.B Rd 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd SHLL SHLL.B Rd SHLL.B #2,Rd SHLL.W Rd SHLL.W #2,Rd SHLL.L #2,ERd SHLL.L ERd 761 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa Mnemonic Operation -- -- -- 0 -- -- -- -- -- -- -- C -- -- -- -- -- -- MSB -- -- 2 LSB C MSB LSB MSB LSB C ---- 0 B B W W L L B B W W L L B B W W L L 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 -- ROTXR.L #2,ERd ---- 0 0 0 0 ---- 0 0 ---- 0 0 ---- 0 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- 0 0 0 0 0 0 0 0 0 0 0 0 762 Addressing Mode/ Instruction Length (Bytes) Condition Code IHNZVC Advanced 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ---- 0 ---- 0 No. of States*1 SHLR SHLR.B Rd SHLR.B #2,Rd SHLR.W Rd SHLR.W #2,Rd SHLR.L ERd SHLR.L #2,ERd ROTXL ROTXL.B Rd ROTXL.B #2,Rd ROTXL.W Rd ROTXL.W #2,Rd ROTXL.L ERd ROTXL.L #2,ERd ROTXR ROTXR.B Rd ROTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd Addressing Mode/ Instruction Length (Bytes) Condition Code -- Operation ---- ---- ---- C MSB LSB ---- ---- ---- -- -- -- MSB -- 1 LSB C ---- ---- ---- ---- ---- ---- IHNZVC 0 0 0 0 0 0 0 0 0 0 0 0 No. of States*1 Advanced 1 1 1 1 1 1 1 1 1 1 1 1 Operand Size #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa Mnemonic B B W W L L B B W W L L 2 2 2 2 2 2 2 2 2 2 2 2 ROTL ROTL.B Rd ROTL.B #2,Rd ROTL.W Rd ROTL.W #2,Rd ROTL.L ERd ROTL.L #2,ERd ROTR ROTR.B Rd ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L #2,ERd ROTR.L ERd 763 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa Mnemonic Operation (#xx:3 of Rd8)1 4 4 6 8 2 4 4 6 8 2 4 4 6 8 2 4 4 6 (Rn8 of @aa:8)1 (Rn8 of @aa:16)1 (Rn8 of @aa:32)1 (#xx:3 of Rd8)0 (#xx:3 of @ERd)0 (#xx:3 of @aa:8)0 (#xx:3 of @aa:16)0 (#xx:3 of @aa:32)0 (Rn8 of Rd8)0 (Rn8 of @ERd)0 (Rn8 of @aa:8)0 (Rn8 of @aa:16)0 (Rn8 of @ERd)1 (Rn8 of Rd8)1 (#xx:3 of @aa:32)1 (#xx:3 of @aa:16)1 (#xx:3 of @aa:8)1 (#xx:3 of @ERd)1 B B B B B B B B B B B B B B B B B B B 2 -- 764 Addressing Mode/ Instruction Length (Bytes) Condition Code IHNZVC ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ No. of States*1 Advanced 1 4 4 5 6 1 4 4 5 6 1 4 4 5 6 1 4 4 5 BSET BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 (5) Bit-Manipulation Instructions BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BCLR BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 Addressing Mode/ Instruction Length (Bytes) Condition Code -- Operation (Rn8 of @aa:32)0 IHNZVC ------------ No. of States*1 Advanced 6 1 4 Operand Size #xx Rn @ERn @(d,ERn) @aa 8 @-ERn/@ERn+ @(d,PC) @@aa (#xx:3 of @ERd) [ (#xx:3 of @ERd)] Mnemonic B B B (#xx:3 of @aa:8) [ (#xx:3 of @aa:8)] B 6 (#xx:3 of @aa:16) [ (#xx:3 of @aa:16)] B 8 (#xx:3 of @aa:32) [ (#xx:3 of @aa:32)] B B B B 6 4 4 2 (Rn8 of Rd8)[ (Rn8 of Rd8)] 4 2 BCLR BCLR Rn,@aa:32 BNOT BNOT #xx:3,Rd (#xx:3 of Rd8)[ (#xx:3 of Rd8)] -- -- -- -- -- -- ------------ BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 B 4 ------------ 4 BNOT #xx:3,@aa:16 ------------ 5 BNOT #xx:3,@aa:32 ------------ 6 BNOT Rn,Rd ------------ (Rn8 of @ERd)[ (Rn8 of @ERd)] -- -- -- -- -- -- (Rn8 of @aa:8)[ (Rn8 of @aa:8)] -- -- -- -- -- -- (Rn8 of @aa:16) [ (Rn8 of @aa:16)] ------------ 1 4 4 5 BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 B 8 (Rn8 of @aa:32) [ (Rn8 of @aa:32)] ------------ 6 BTST B B B B BTST #xx:3,Rd 2 4 4 6 (#xx:3 of Rd8)Z (#xx:3 of @ERd)Z (#xx:3 of @aa:8)Z (#xx:3 of @aa:16)Z ------ ------ ------ ------ ---- ---- ---- ---- 1 3 3 4 BTST #xx:3,@ERd BTST #xx:3,@aa:16 BTST #xx:3,@aa:8 765 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa Mnemonic Operation (#xx:3 of @aa:32)Z (Rn8 of Rd8)Z 4 4 6 8 2 4 4 6 8 2 4 4 6 8 2 4 4 (#xx:3 of Rd8)C (#xx:3 of @ERd)C (#xx:3 of @aa:8)C (#xx:3 of @aa:16)C (#xx:3 of @aa:32)C (#xx:3 of Rd8)C (#xx:3 of @ERd)C (#xx:3 of @aa:8)C (#xx:3 of @aa:16)C (#xx:3 of @aa:32)C C(#xx:3 of Rd8) C(#xx:3 of @ERd24) C(#xx:3 of @aa:8) (Rn8 of @aa:32)Z (Rn8 of @aa:16)Z (Rn8 of @aa:8)Z (Rn8 of @ERd)Z ------ ------ ------ ------ ------ ------ B B B B B B B B B B B B B B B B B B B 2 8 -- BILD #xx:3,@aa:32 ---------- 766 Addressing Mode/ Instruction Length (Bytes) Condition Code IHNZVC ---- ---- ---- ---- ---- ---- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- Advanced 5 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 ------------ ------------ ------------ 1 4 4 No. of States*1 BTST BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BLD BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BILD BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BST BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 Addressing Mode/ Instruction Length (Bytes) Condition Code -- Operation C(#xx:3 of @aa:16) C(#xx:3 of @aa:32) C(#xx:3 of Rd8) IHNZVC ------------ ------------ ------------ ------------ ------------ ------------ ------------ ---------- ---------- ---------- ---------- C(#xx:3 of @aa:32)C C[ (#xx:3 of Rd8)]C ---------- ---------- C[ (#xx:3 of @ERd24)]C ---------- C[ (#xx:3 of @aa:8)]C ---------- No. of States*1 Advanced 5 6 1 4 4 5 6 1 3 3 4 5 1 3 3 Operand Size #xx Rn @ERn @(d,ERn) @aa 6 8 @-ERn/@ERn+ @(d,PC) @@aa C(#xx:3 of @ERd24) 4 6 8 C(#xx:3 of @aa:16) C(#xx:3 of @aa:32) C(#xx:3 of Rd8)C C(#xx:3 of @aa:8) C(#xx:3 of @ERd24)C 4 6 8 C(#xx:3 of @aa:8)C C(#xx:3 of @aa:16)C C[ (#xx:3 of @aa:16)]C 6 8 C[ (#xx:3 of @aa:32)]C C(#xx:3 of Rd8)C 4 Mnemonic B B B B B B B B B B B B B B B B B B B 2 4 4 2 4 2 4 2 BST BST #xx:3,@aa:16 BST #xx:3,@aa:32 BIST BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BAND BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 BIAND BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 ---------- ---------- ---------- C(#xx:3 of @ERd24)C ---------- 4 5 1 3 BIAND #xx:3,@aa:32 BOR #xx:3,@ERd BOR BOR #xx:3,Rd 767 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa Mnemonic Operation C(#xx:3 of @aa:8)C C(#xx:3 of @aa:16)C C(#xx:3 of @aa:32)C C[ (#xx:3 of Rd8)]C 4 4 6 8 2 4 4 6 8 2 4 4 6 8 C[ (#xx:3 of @aa:8)]C C[ (#xx:3 of @aa:16)]C C[ (#xx:3 of @aa:32)]C C(#xx:3 of Rd8)C C(#xx:3 of @ERd24)C C(#xx:3 of @aa:8)C C(#xx:3 of @aa:16)C C(#xx:3 of @aa:32)C C[ (#xx:3 of Rd8)]C C[ (#xx:3 of @ERd24)]C C[ (#xx:3 of @aa:8)]C C[ (#xx:3 of @aa:16)]C C[ (#xx:3 of @aa:32)]C C[ (#xx:3 of @ERd24)]C B B B B B B B B B B B B B B B B B B 2 8 6 4 -- BIXOR #xx:3,@aa:32 ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- 768 Addressing Mode/ Instruction Length (Bytes) Condition Code IHNZVC Advanced 3 4 5 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 No. of States*1 BOR BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BIOR BIOR #xx:3,Rd BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 BXOR BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 BIXOR BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 Addressing Mode/ Instruction Length (Bytes) Operation Condition Code Branching Condition No. of States*1 Advanced 2 3 2 3 2 Operand Size #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa -- Mnemonic -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 4 2 4 V=0 2 4 Z=1 2 4 Z=0 2 4 C=1 2 4 C=0 2 4 CZ=1 2 CZ=0 4 2 else next; Never 4 PCPC+d 2 if condition is true then Always IHNZVC ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ (6) Branch Instructions Bcc BRA d:8(BT d:8) BRA d:16(BT d:16) BRN d:8(BF d:8) BRN d:16(BF d:16) BHI d:8 BHI d:16 3 2 3 2 3 2 3 2 3 2 3 2 3 BLS d:8 BLS d:16 BCC d:B(BHS d:8) BCC d:16(BHS d:16) BCS d:8(BLO d:8) BCS d:16(BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 769 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa Mnemonic -- -- -- -- -- -- -- -- -- -- -- -- -- -- 4 2 4 2 4 2 4 NV=1 2 4 NV=0 2 N=1 4 2 N=0 4 2 V=1 -- 770 Addressing Mode/ Instruction Length (Bytes) Operation Condition Code Branching Condition No. of States*1 Advanced 2 3 2 IHNZVC ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ Bcc BVS d:8 BVS d:16 BPL d:8 BPL d:16 3 2 3 2 3 2 3 BMI d:8 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 Z(NV)=0 -- -- -- -- -- -- ------------ Z(NV)=1 -- -- -- -- -- -- ------------ 2 3 2 3 BGT d:16 BLE d:8 BLE d:16 Addressing Mode/ Instruction Length (Bytes) Condition Code -- Operation PCERn IHNZVC ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ No. of States*1 Advanced 2 3 5 4 5 4 5 6 5 Operand Size #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa PCaa:24 2 2 4 PC@-SP,PCPC+d:16 PC@-SP,PCERn 4 2 2 PC@SP+ PC@-SP,PCaa:24 PC@-SP,PC@aa:8 PC@-SP,PCPC+d:8 PC@aa:8 4 Mnemonic -- -- -- -- -- -- -- -- -- 2 2 JMP JMP @ERn JMP @aa:24 JMP @@aa:8 BSR BSR d:8 BSR d:16 JSR JSR @ERn JSR @aa:24 JSR @@aa:8 RTS RTS 771 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa Mnemonic Operation PC@-SP,CCR@-SP, EXR@-SP, -- LDC LDC #xx:8,CCR LDC Rs,CCR LDC @ERs,CCR LDC @(d:16,ERs),CCR LDC @(d:32,ERs),CCR 772 Addressing Mode/ Instruction Length (Bytes) Condition Code IHNZVC 1 ---------- No. of States*1 Advanced 8 [13] -- 5 [13] ------------ 2 1 ------------ 2 1 ------------ 1 3 ------------ 3 4 ------------ 4 6 ------------ 6 4 ------------ 4 4 ------------ 4 5 ------------ 5 TRAPA TRAPA #xx:2 (7) System Control Instructions RTE RTE SLEEP SLEEP LDC #xx:8,EXR LDC Rs,EXR LDC @ERs,EXR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR Addressing Mode/ Instruction Length (Bytes) Condition Code -- Operation CCRRd8 EXRRd8 IHNZVC ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ No. of States*1 Advanced 1 1 3 3 4 4 6 6 4 Operand Size #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa CCR@ERd EXR@ERd CCR@(d:16,ERd) EXR@(d:16,ERd) CCR@(d:32,ERd) EXR@(d:32,ERd) 4 4 6 6 8 8 ERd32-2ERd32,EXR@ERd CCR@aa:16 EXR@aa:16 CCR@aa:32 EXR@aa:32 CCR#xx:8CCR EXR#xx:8EXR CCR#xx:8CCR EXR#xx:8EXR CCR#xx:8CCR EXR#xx:8EXR Mnemonic B B W W W W W W W W W W W W B2 B4 B2 B4 B2 B4 -- 10 10 6 6 4 4 2 2 STC STC CCR,Rd STC EXR,Rd STC CCR,@ERd STC EXR,@ERd STC CCR,@(d:16,ERd) STC EXR,@(d:16,ERd) STC CCR,@(d:32,ERd) STC EXR,@(d:32,ERd) STC CCR,@-ERd ERd32-2ERd32,CCR@ERd -- -- -- -- -- -- ------------ ------------ ------------ ------------ ------------ STC EXR,@-ERd 4 4 4 5 5 1 ------------ 2 1 ------------ 2 1 ------------ 2 STC CCR,@aa:16 STC EXR,@aa:16 STC CCR,@aa:32 STC EXR,@aa:32 ANDC ANDC #xx:8,CCR ANDC #xx:8,EXR ORC ORC #xx:8,CCR ORC #xx:8,EXR XORC XORC #xx:8,CCR XORC #xx:8,EXR NOP NOP 2 PCPC+2 ------------ 1 773 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa Mnemonic Operation -- 4 if R4L0 Repeat @ER5@ER6 ER5+1ER5 ER6+1ER6 R4L-1R4L Until R4L=0 else next; 4 if R40 Repeat @ER5@ER6 ER5+1ER5 ER6+1ER6 R4-1R4 Until R4=0 else next; -- 774 Addressing Mode/ Instruction Length (Bytes) Condition Code IHNZVC No. of States*1 Advanced -- -- -- -- -- -- 4+2n *2 -- -- -- -- -- -- -- 4+2n *2 (8) Block Transfer Instructions EEPMOV EEPMOV.B EEPMOV.W Notes: *1 *2 *3 The number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory. n is the initial value of R4L or R4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. [1] Seven states for saving or restoring two registers, nine states for three registers, or eleven states for four registers. [2] Cannot be used in the H8S/2626 Series or H8S/2623 Series. [3] Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. [4] Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. [5] Retains its previous value when the result is zero; otherwise cleared to 0. [6] [7] [8] [9] [10] [11] Set to 1 when the divisor is negative; otherwise cleared to 0. Set to 1 when the divisor is zero; otherwise cleared to 0. Set to 1 when the quotient is negative; otherwise cleared to 0. One additional state is required for execution when EXR is valid. MAC instruction results are indicated in the flags when the STMAC instruction is executed. A maximum of three additional states are required for execution of one of these instructions within three states after execution of a MAC instruction. For example, if there is a one-state instruction (such as NOP) between a MAC instruction and one of these instructions, that instruction will be two states longer. 775 A.2 Instruction Codes Table A-2 shows the instruction codes. 776 Instruction Size 1st byte 8 IMM rs 1 IMM rs 1 0 erd IMM 1 ers 0 erd 0 0 erd 0 erd 0 erd IMM rs IMM rs 6 IMM rs 6 0 erd IMM 6 0 ers 0 erd 6 0 IMM 4 IMM 0 IMM 0 erd abs 1 3 disp 0 disp 1 0 disp 0 disp 0 0 abs abs 7 6 0 IMM 0 0 IMM 7 6 0 0 7 6 0 IMM 0 7 6 0 IMM 0 rd 1 0 6 F rd rd rd rd 8 9 rd rd rd 0 7 0 7 0 0 0 0 9 0 E 1 7 6 7 0 0 0 7 7 7 6 6 4 5 4 5 8 1 8 0 A A E C 6 1 6 1 A 6 9 6 rd E rd B B B A A 9 9 8 rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B W W L L L L L B B B B W W L L B B B B B B B -- -- -- -- Mnemonic Instruction Format 10th byte Table A-2 ADD ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDS ADDS #1,ERd ADDS #2,ERd Instruction Codes ADDS #4,ERd ADDX ADDX #xx:8,Rd ADDX Rs,Rd AND AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd ANDC ANDC #xx:8,CCR ANDC #xx:8,EXR BAND BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 Bcc BRA d:8 (BT d:8) BRA d:16 (BT d:16) BRN d:8 (BF d:8) BRN d:16 (BF d:16) 777 778 Instruction Format Size 1st byte 4 5 0 disp 3 0 disp 4 0 disp 5 0 disp 6 0 disp 7 0 disp 8 0 disp 9 0 disp A 0 disp B 0 disp C 0 disp D 0 disp E disp F 0 disp 0 disp disp disp disp disp disp disp disp disp disp disp disp 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 8 F 8 E 8 D 8 C 8 B 8 A 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 disp 2 2 disp 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Instruction Mnemonic 10th byte Bcc BHI d:8 BHI d:16 BLS d:8 BLS d:16 BCC d:8 (BHS d:8) BCC d:16 (BHS d:16) BCS d:8 (BLO d:8) BCS d:16 (BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 BVS d:8 BVS d:16 BPL d:8 BPL d:16 BMI d:8 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 BLE d:8 BLE d:16 Instruction Size 1st byte 7 7 7 abs 1 abs 0 IMM 7 0 IMM 2 0 abs 3 rn 0 erd abs 1 abs abs 6 3 1 IMM 0 erd 1 IMM 1 IMM abs abs 7 6 0 1 IMM 0 7 6 1 IMM 0 abs 1 3 1 IMM 0 erd 1 IMM 1 IMM abs abs 0 7 7 1 IMM 0 7 7 1 IMM 0 abs 1 3 1 IMM 0 erd abs 1 3 0 0 7 0 7 4 4 rd 1 IMM 1 IMM abs abs 0 0 7 4 1 IMM 0 7 4 1 IMM 0 0 0 7 7 0 7 7 0 rd 0 0 7 6 0 7 6 0 rd 8 8 6 2 rn 0 2 rn 0 6 2 rn 0 0 6 2 rn 0 rd 8 8 7 2 0 6 6 6 7 7 6 6 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 A A E C 4 A A E C 7 A A E C 6 A A F D 2 A A F 0 IMM 7 2 0 D 0 IMM 0 erd 0 7 2 0 2 0 IMM rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B B B B B B B B B B B B B B B B B B B B B B B B Mnemonic Instruction Format 10th byte BCLR BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BIAND BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR BIOR #xx:3,Rd BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 779 780 Instruction Format Size 1st byte 6 1 IMM 0 erd abs 1 abs abs 6 1 IMM 7 0 1 IMM 3 1 IMM 0 erd abs 1 abs abs 7 1 IMM 3 0 IMM 0 erd abs 1 abs abs 3 0 IMM 0 erd abs 1 abs abs 3 rn 0 erd abs 1 3 8 8 6 0 6 1 1 abs abs rd rn rn 0 0 6 1 rn 0 6 1 rn 0 8 8 7 0 IMM 1 0 7 1 0 IMM 0 7 1 0 IMM 0 0 0 IMM 7 1 0 rd 0 0 7 7 7 0 IMM 7 0 0 IMM 0 7 7 0 IMM 0 0 0 IMM 7 7 0 rd 0 0 7 5 0 5 1 IMM 0 7 1 IMM 5 0 0 1 IMM 7 5 0 rd 8 8 6 7 0 6 1 IMM 7 0 0 1 IMM 6 7 0 7 7 6 6 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 6 7 7 6 6 A A F D 1 A A F D 1 A A E C 7 A A E C 5 A A F D 7 rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B B B B B B B B B B B B B B B B B B B B B B B B Instruction Mnemonic 10th byte BIST BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BIXOR BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 BLD BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BNOT BNOT #xx:3,Rd BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 Instruction Size 1st byte 7 0 IMM 0 erd abs 1 abs abs 7 0 IMM 4 0 0 IMM 3 0 IMM 0 erd abs 1 abs abs 7 0 IMM 3 rn 0 erd abs 1 abs abs 3 disp 0 disp 0 IMM 0 erd abs 1 3 0 IMM 0 erd abs 1 3 rn 0 erd 0 0 rd 0 C 6 3 rn 0 0 7 7 rd 3 3 0 IMM 0 IMM abs abs 0 0 7 3 0 IMM 0 7 3 0 IMM 0 8 8 abs abs 6 7 0 IMM 0 0 IMM 6 7 0 0 6 7 0 IMM 0 6 7 0 IMM 0 rd 0 8 8 6 0 6 0 rn 0 rn 0 6 0 rn 0 0 6 0 rn 0 rd 8 8 7 0 0 0 0 IMM 0 7 0 IMM 0 0 0 0 IMM 7 0 0 rd 0 0 7 4 0 7 0 IMM 4 0 0 0 IMM 7 4 0 7 7 6 6 7 7 7 6 6 6 7 7 6 6 5 5 6 7 7 6 6 7 7 7 6 6 6 7 3 A A E C 3 A A F D 7 C 5 A A F D 0 A A F D 0 A A E C 4 rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B B B B B B B B B B B B B B -- -- B B B B B B B B B B B B Mnemonic Instruction Format 10th byte BOR BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BSR BSR d:8 BSR d:16 BST BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 BTST BTST #xx:3,Rd BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd 781 782 Instruction Format Size 1st byte 7 6 6 7 7 7 6 0 IMM 7 5 6 0 A 1 7 1 7 1 0 1 1 1 1 1 1 0 0 5 5 7 7 B D B 5 3 rs 1 rs rd 0 erd C 4 5 5 9 9 8 8 F F 1 D 0 5 1 D 0 5 1 3 B 0 erd rs rs rd 0 erd F B 0 erd 7 B D rd B 5 rd A 0 rd F 0 rd F 0 rd F 1 ers 0 erd A 0 erd IMM 2 D rs rd 9 IMM 2 rd C rs rd rd IMM 1 A 0 A abs 3 0 A abs 1 0 7 5 0 0 IMM 0 E abs 0 IMM 7 5 0 C 0 IMM 0 erd 0 7 5 0 5 0 IMM rd A abs 3 0 6 3 rn 0 A abs 1 0 6 3 rn 0 E abs 6 3 rn 0 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B B B B B B B -- B B W W L L B B B W W L L B W B W -- -- Instruction Mnemonic 10th byte BTST BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 CLRMAC CLRMAC CMP CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA DAA Rd DAS DAS Rd DEC DEC.B Rd DEC.W #1,Rd DEC.W #2,Rd DEC.L #1,ERd DEC.L #2,ERd DIVXS DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU DIVXU.B Rs,Rd DIVXU.W Rs,ERd EEPMOV EEPMOV.B EEPMOV.W Instruction Size 1st byte 1 1 0 erd rd 0 erd rd rd rd 0 erd 0 erd 0 abs abs 0 ern abs abs IMM 4 IMM 0 1 4 4 4 4 4 4 4 4 4 4 1 0 1 0 1 1 0 7 7 6 6 6 6 1 6 0 6 F F 8 8 D D B B 1 6 9 0 6 9 0 ers 0 ers 0 ers 0 ers 0 ers 0 ers 0 ers 0 ers 0 0 rs 0 0 0 0 0 0 0 0 0 0 disp disp 6 6 B B disp disp 2 2 0 0 disp disp rs 1 0 7 0 1 1 0 0 0 0 0 5 5 5 5 5 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 3 3 1 7 F E D B A 9 0 ern B F B 7 B D B 5 A 0 7 7 7 5 7 F 7 D rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte W L W L B W W L L -- -- -- -- -- -- B B B B W W W W W W W W W W Mnemonic Instruction Format 10th byte EXTS EXTS.W Rd EXTS.L ERd EXTU EXTU.W Rd EXTU.L ERd INC INC.B Rd INC.W #1,Rd INC.W #2,Rd INC.L #1,ERd INC.L #2,ERd JMP JMP @ERn JMP @aa:24 JMP @@aa:8 JSR JSR @ERn JSR @aa:24 JSR @@aa:8 LDC LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR 783 784 Instruction Format Size 1st byte 0 0 0 0 0 0 0 0 F IMM rs 0 ers 0 ers disp 6 A 2 rd disp 0 ers 0 ers abs 0 abs abs 2 1 erd 1 erd disp 6 A A rs disp 0 erd 1 erd abs 8 A 0 rs 0 ers 0 ers 0 ers rd rd rd 0 8 6 B disp 2 rd disp rd rs IMM rs abs abs rs 0 rs rs rd rd rd 0 rd rd rd 0 6 6 7 6 2 6 6 6 6 7 6 3 6 6 7 0 6 6 7 F 9 D 9 A A rs C 8 E 8 A A rd C 8 E 8 C rd 1 0 ern 0 erm 6 0 6 D 3 0 ers 3 3 0 ers 2 1 0 ern+3 3 0 6 D 7 1 0 ern+2 2 0 6 D 7 1 0 ern+1 1 0 6 D 7 1 0 abs 4 1 6 B 2 1 0 abs 4 0 6 B 2 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte W W L L L L L -- B B B B B B B B B B B B B B B B W W W W W Instruction Mnemonic 10th byte LDC LDC @aa:32,CCR LDC @aa:32,EXR LDM LDM.L @SP+, (ERn-ERn+1) LDM.L @SP+, (ERn-ERn+2) LDM.L @SP+, (ERn-ERn+3) LDMAC LDMAC ERs,MACH LDMAC ERs,MACL MAC MAC @ERn+,@ERm+ MOV MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa :16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd Instruction Size 1st byte 6 6 6 abs 6 6 7 6 6 6 abs IMM 7 0 erd 0 0 0 ers 0 erd 0 ers 0 erd disp 6 B 2 0 erd disp 0 ers 0 ers 0 erd 0 0 erd 0 erd 2 1 erd 0 ers 1 erd 0 ers 0 erd 0 6 B disp A 0 ers disp abs abs 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 6 1 0 0 6 B B 1 0 0 6 D 1 0 0 7 8 1 0 0 6 F 1 0 0 6 9 1 0 0 6 B 1 0 0 6 B 1 0 0 6 D 1 0 0 7 8 1 0 0 6 F 1 0 0 6 9 F 1 ers 0 erd A 0 B A rs B 8 rs D 1 erd rs 8 0 erd disp 0 6 B A rs F 1 erd rs 9 1 erd rs B 2 rd B 0 rd D 0 ers rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte W W W W W W W W W L L L L L L L L L L Mnemonic Instruction Format 10th byte MOV MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,Rd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16 ,ERd MOV.L @aa:32 ,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd)*1 L L L L B B B W B W 5 2 5 0 0 1 C rs rs 0 1 C 0 0 rd 0 erd 5 5 0 2 MOV.L ERs,@-ERd 1 erd 0 ers 8 A 0 ers 0 ers abs abs MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MOVFPE MOVFPE @aa:16,Rd Cannot be used in the H8S/2626 Series or H8S/2623 Series. MOVTPE MOVTPE Rs,@aa:16 MULXS MULXS.B Rs,Rd rs rs rd 0 erd MULXS.W Rs,ERd MULXU MULXU.B Rs,Rd MULXU.W Rs,ERd 785 786 Instruction Format Size 1st byte 1 1 1 0 1 1 1 C IMM rs 4 IMM rs 4 0 erd IMM 6 4 0 ers 0 erd 0 IMM 4 0 4 IMM 7 0 6 D 7 0 ern F 0 6 D F 8 C 9 D B 0 erd 0 erd F rd rd rd rd 0 rn 0 ern 0 rn 1 F rd rd rd 1 7 6 7 0 0 0 6 0 6 0 1 1 1 1 1 1 2 2 2 2 2 2 1 D 1 D 1 4 1 A 4 9 4 rd 7 0 erd 3 7 1 rd 7 0 rd 0 0 0 7 0 erd B 7 9 rd 7 8 rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B W L -- B W L B B W W L L B B W L W L B B W W L L Instruction Mnemonic 10th byte NEG NEG.B Rd NEG.W Rd NEG.L ERd NOP NOP NOT NOT.B Rd NOT.W Rd NOT.L ERd OR OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC ORC #xx:8,CCR ORC #xx:8,EXR POP POP.W Rn POP.L ERn PUSH PUSH.W Rn PUSH.L ERn ROTL ROTL.B Rd ROTL.B #2, Rd ROTL.W Rd ROTL.W #2, Rd ROTL.L ERd ROTL.L #2, ERd Instruction Size 1st byte 1 1 1 1 1 0 erd 0 erd rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd 0 0 rd rd rd rd 0 erd 0 erd 1 1 1 1 1 1 1 1 1 1 1 1 1 5 5 1 1 1 1 1 1 0 F 0 B 0 D 0 9 0 C 0 8 4 7 6 7 3 7 3 3 3 5 3 1 3 4 3 0 2 7 2 3 2 5 2 1 2 4 2 0 3 F 3 B 3 D rd 3 9 rd 3 C rd 3 8 rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B W W L L B B W W L L B B W W L L -- -- B B W W L L Mnemonic Instruction Format 10th byte ROTR ROTR.B Rd ROTR.B #2, Rd ROTR.W Rd ROTR.W #2, Rd ROTR.L ERd ROTR.L #2, ERd ROTXL ROTXL.B Rd ROTXL.B #2, Rd ROTXL.W Rd ROTXL.W #2, Rd ROTXL.L ERd ROTXL.L #2, ERd ROTXR ROTXR.B Rd ROTXR.B #2, Rd ROTXR.W Rd ROTXR.W #2, Rd ROTXR.L ERd ROTXR.L #2, ERd RTE RTE RTS RTS SHAL SHAL.B Rd SHAL.B #2, Rd SHAL.W Rd SHAL.W #2, Rd SHAL.L ERd SHAL.L #2, ERd 787 788 Instruction Format Size 1st byte 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 4 4 1 4 1 4 0 1 0 1 1 4 1 1 4 0 6 6 7 7 6 6 1 6 4 1 1 6 4 0 9 9 F F 8 8 D D 2 1 rd 1 erd 1 erd 1 erd 1 erd 0 erd 0 erd 1 erd 1 erd 0 0 0 0 0 0 0 0 6 6 B B disp disp A A 0 0 disp disp 2 0 rd 1 8 0 1 0 erd 7 1 0 erd 3 1 5 rd 1 1 rd 1 4 rd 1 0 rd 0 0 erd 7 0 0 erd 3 0 5 rd 0 1 rd 0 4 rd 0 0 rd 1 0 erd F 1 0 erd B 1 D rd 1 9 rd 1 C rd 1 8 rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B W W L L B B W W L L B B W W L L -- B B W W W W Instruction Mnemonic 10th byte SHAR SHAR.B Rd SHAR.B #2, Rd SHAR.W Rd SHAR.W #2, Rd SHAR.L ERd SHAR.L #2, ERd SHLL SHLL.B Rd SHLL.B #2, Rd SHLL.W Rd SHLL.W #2, Rd SHLL.L ERd SHLL.L #2, ERd SHLR SHLR.B Rd SHLR.B #2, Rd SHLR.W Rd SHLR.W #2, Rd SHLR.L ERd SHLR.L #2, ERd SLEEP SLEEP STC STC.B CCR,Rd STC.B EXR,Rd STC.W CCR,@ERd STC.W EXR,@ERd STC.W CCR,@(d:16,ERd) W STC.W EXR,@(d:16,ERd) W STC.W CCR,@(d:32,ERd) W STC.W EXR,@(d:32,ERd) W STC.W CCR,@-ERd STC.W EXR,@-ERd Instruction Size 1st byte 0 0 0 0 0 0 0 0 0 ers 0 ers rd rd IMM rd 0 erd IMM 0 1 7 1 7 1 1 ers 0 erd 0 0 erd 0 erd 0 erd IMM rs E 00 IMM IMM rs 5 rs 5 F rd 0 erd 0 6 5 IMM 0 ers 0 erd rd rd IMM 0 0 7 B 0 erd rd C 8 9 1 1 1 B 1 0 5 D 1 7 6 7 0 1 A 5 9 5 rd 7 1 E rd B B B A A 3 9 rs 9 3 8 rs 2 3 2 2 1 0 ern 3 0 6 D F 1 0 ern 2 0 6 D F 1 0 ern 1 0 6 D F 1 abs 4 1 6 B A 0 1 abs 4 0 6 B A 0 1 abs 4 1 6 B 8 0 1 abs 4 0 6 B 8 0 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte W W W W L L L L L B W W L L L L L B B B -- B B W W L L Mnemonic Instruction Format 10th byte STC STC.W CCR,@aa:16 STC.W EXR,@aa:16 STC.W CCR,@aa:32 STC.W EXR,@aa:32 STM STM.L(ERn-ERn+1), @-SP STM.L (ERn-ERn+2), @-SP STM.L (ERn-ERn+3), @-SP STMAC STMAC MACH,ERd STMAC MACL,ERd SUB SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS SUBS #1,ERd SUBS #2,ERd SUBS #4,ERd SUBX SUBX #xx:8,Rd SUBX Rs,Rd TAS TAS @ERd *2 TRAPA TRAPA #x:2 XOR XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd 789 790 Instruction Format Size 1st byte 0 0 1 4 1 0 5 IMM 5 IMM 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B Instruction Mnemonic 10th byte XORC XORC #xx:8,CCR XORC #xx:8,EXR Notes: *1 Bit 7 of the 4th byte of the MOV.L ERs, @(d:32,ERd) instruction can be either 1 or 0. *2 Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Legend IMM: abs: disp: rs, rd, rn: ers, erd, ern, erm: Immediate data (2, 3, 8, 16, or 32 bits) Absolute address (8, 16, 24, or 32 bits) Displacement (8, 16, or 32 bits) Register field (4 bits specifying an 8-bit or 16-bit register. The symbols rs, rd, and rn correspond to operand symbols Rs, Rd,and Rn.) Register field (3 bits specifying an address register or 32-bit register. The symbols ers, erd, ern, and erm correspond to operand symbols ERs, ERd, ERn, and ERm.) The register fields specify general registers as follows. 16-Bit Register Register Field 0000 0001 * * * 0111 1000 1001 * * * 1111 R0 R1 * * * R7 E0 E1 * * * E7 0000 0001 * * * 0111 1000 1001 * * * 1111 General Register Register Field General Register R0H R1H * * * R7H R0L R1L * * * R7L 8-Bit Register Address Register 32-Bit Register Register Field General Register 000 001 * * * 111 ER0 ER1 * * * ER7 A.3 Instruction when most significant bit of BH is 0. BL Instruction when most significant bit of BH is 1. Instruction code 1st byte 2nd byte AH AL BH AL 3 ORC OR MOV.B XOR AND Table A.3(2) SUB CMP XORC ANDC LDC ADD MOV 4 9 C D A B 5 6 7 8 E AH 0 1 2 F 0 NOP ADDX SUBX 1 Table A.3(2) LDC Table STC * * A.3(2) STMAC LDMAC Table Table Table A.3(2) A.3(2) A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) Operation Code Map Table A-3 Operation Code Map (1) 2 Table A-3 shows the operation code map. 3 BLS DIVXU BST MOV MOV Table A.3(2) BTST RTS BSR RTE TRAPA Table A.3(2) JMP BCC BVS BPL BMI BCS BNE BEQ BVC BGE BSR MOV Table A.3(3) BLT BGT JSR BLE 4 BRA BRN BHI 5 MULXU DIVXU MULXU 6 OR XOR AND BIST BOR BLD BXOR BAND BIXOR BIAND BIOR BILD ADD ADDX CMP SUBX OR XOR AND MOV BSET BNOT BCLR 7 Table A.3(2) Table A.3(2) EEPMOV 8 9 A B C D E F Note: * Cannot be used in the H8S/2626 Series or H8S/2623 Series. 791 792 2nd byte BH BL 2 7 8 B Table A.3(3) ADD INC INC ADDS MOV SHLL SHLL SHLR ROTXL ROTXR EXTU EXTU NEG ROTR NEG SUB DEC DEC SUBS CMP BHI MOV CMP CMP SUB OR XOR SUB OR XOR Table A.3(4) MOVFPE AND AND BLS BCC BCS BNE BEQ BVC MOV BVS BPL MOV BMI BGE MOVTPE BLT BGT BLE DEC DEC ROTL SHAR SHAL SHLR ROTXL ROTXR NOT SHAL SHAR ROTL ROTR EXTS SHAL SHAR ROTL ROTR EXTS INC INC C SLEEP STM STC LDC MAC 3 4 5 6 9 A D Table A.3(3) E TAS F Table A.3(3) Instruction code 1st byte AH AL BH AH AL 0 1 01 MOV LDM * * CLRMAC 0A INC 0B ADDS Table A-3 Operation Code Map (2) 0F DAA 10 SHLL 11 SHLR 12 ROTXL 13 ROTXR 17 NOT 1A DEC 1B SUBS 1F DAS 58 BRA BRN 6A MOV Table A.3(4) 79 MOV ADD 7A MOV ADD Note: * Cannot be used in the H8S/2626 Series or H8S/2623 Series. Instruction code BH BL CH CL DH DL 1st byte 2nd byte 3rd byte 4th byte AH AL Instruction when most significant bit of DH is 0. Instruction when most significant bit of DH is 1. CL 2 MULXS DIVXS OR BTST BTST BCLR BCLR BTST BTST BCLR BCLR XOR AND 3 4 5 6 7 8 9 A B AH AL BH BL CH 0 1 C D E F Table A-3 Operation Code Map (3) 01C05 MULXS 01D05 DIVXS 01F06 7Cr06 *1 7Cr07 *1 7Dr06 *1 BSET BNOT BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST 7Dr07 *1 BSET BNOT 7Eaa6 *2 7Eaa7 *2 7Faa6 *2 BSET BNOT BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST 7Faa7 *2 BSET BNOT Notes: *1 r is the register specification field. *2 aa is the absolute address specification. 793 794 2nd byte BH BL CH CL DH DL EH EL FH FL Instruction when most significant bit of FH is 0. Instruction when most significant bit of FH is 1. 2 4 5 6 7 8 9 A B C BTST BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST 3 D E F 3rd byte 4th byte 5th byte 6th byte BCLR 2nd byte BH BL CH CL DH DL EH EL FH 3rd byte 4th byte 5th byte 6th byte FL 7th byte GH GL 8th byte HH HL Instruction when most significant bit of HH is 0. Instruction when most significant bit of HH is 1. 2 4 5 6 BTST 3 7 8 9 A B C D E F BCLR BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST nstruction code 1st byte AH AL EL AHALBHBLCHCLDHDLEH 0 1 6A10aaaa6* Table A-3 Operation Code Map (4) 6A10aaaa7* 6A18aaaa6* BSET BNOT 6A18aaaa7* nstruction code 1st byte AH AL GL AHALBHBL ... FHFLGH 0 1 6A30aaaaaaaa6* 6A30aaaaaaaa7* 6A38aaaaaaaa6* BSET BNOT 6A38aaaaaaaa7* Note: * aa is the absolute address specification. A.4 Number of States Required for Instruction Execution The tables in this section can be used to calculate the number of states required for instruction execution by the CPU. Table A-5 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. Table A-4 indicates the number of states required for each cycle. The number of states required for execution of an instruction can be calculated from these two tables as follows: Execution states = I x SI + J x SJ + K x SK + L xS L + M x SM + N x SN Examples: Advanced mode, program code and stack located in external memory, on-chip supporting modules accessed in two states with 8-bit bus width, external devices accessed in three states with one wait state and 16-bit bus width. 1. BSET #0, @FFFFC7:8 From table A-5: I = L = 2, J = K = M = N = 0 From table A-4: S I = 4, SL = 2 Number of states required for execution = 2 x 4 + 2 x 2 = 12 2. JSR @@30 From table A-5: I = J = K = 2, L = M = N = 0 From table A-4: S I = SJ = SK = 4 Number of states required for execution = 2 x 4 + 2 x 4 + 2 x 4 = 24 795 Table A-4 Number of States per Cycle Access Conditions On-Chip Supporting Module External Device 8-Bit Bus 16-Bit Bus 2 16-Bit Bus Cycle Instruction fetch SI On-Chip 8-Bit Memory Bus 1 4 2-State 3-State 2-State 3-State Access Access Access Access 4 6 + 2m 2 3+m Branch address read SJ Stack operation Byte data access Word data access Internal operation SK SL SM SN 1 2 4 1 1 2 4 1 3+m 6 + 2m 1 1 1 Legend m: Number of wait states inserted into external device access 796 Table A-5 Number of Cycles in Instruction Execution Instruction Branch Stack Fetch Address Read Operation I J K 1 1 2 1 3 1 1 1 1 1 1 2 1 3 2 1 2 1 2 2 3 4 2 2 2 2 (BHS d:8) (BLO d:8) 2 2 2 2 2 2 2 2 2 2 2 2 (BT d:16) (BF d:16) 2 2 1 1 1 1 1 1 Byte Data Access L Word Data Access M Internal Operation N Instruction ADD Mnemonic ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDS ADDX ADDS #1/2/4,ERd ADDX #xx:8,Rd ADDX Rs,Rd AND AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd ANDC ANDC #xx:8,CCR ANDC #xx:8,EXR BAND BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 Bcc BRA d:8 BRN d:8 BHI d:8 BLS d:8 BCC d:8 BCS d:8 BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 BRA d:16 BRN d:16 (BT d:8) (BF d:8) 797 Instruction Bcc Mnemonic BHI d:16 BLS d:16 BCC d:16 BCS d:16 BNE d:16 BEQ d:16 BVC d:16 BVS d:16 BPL d:16 BMI d:16 BGE d:16 BLT d:16 BGT d:16 BLE d:16 (BHS d:16) (BLO d:16) Instruction Branch Stack Fetch Address Read Operation I J K 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 Byte Data Access L Word Data Access M Internal Operation N 1 1 1 1 1 1 1 1 1 1 1 1 1 1 BCLR BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 2 2 2 2 2 2 2 2 BIAND BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 1 1 1 1 BILD BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 1 1 1 1 BIOR BIOR #xx:8,Rd BIOR #xx:8,@ERd BIOR #xx:8,@aa:8 BIOR #xx:8,@aa:16 BIOR #xx:8,@aa:32 1 1 1 1 798 Instruction BIST Mnemonic BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 Instruction Branch Stack Fetch Address Read Operation I J K 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 Byte Data Access L Word Data Access M Internal Operation N 2 2 2 2 BIXOR BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 1 1 1 1 BLD BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 1 1 1 1 BNOT BNOT #xx:3,Rd BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 2 2 2 2 2 2 2 2 BOR BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 1 1 1 1 BSET BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 2 2 2 2 2 2 2 2 799 Instruction BSR Mnemonic BSR d:8 BSR d:16 Instruction Branch Stack Fetch Address Read Operation I J K 2 2 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 1 1 2 1 3 1 1 1 1 1 1 2 2 1 1 2 2 Byte Data Access L Word Data Access M Internal Operation N 1 BST BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 2 2 2 2 BTST BTST #xx:3,Rd BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 1 1 1 1 1 1 1 1 BXOR BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 1 1 1 1 1* 3 CLRMAC CMP CLRMAC CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA DAS DEC DAA Rd DAS Rd DEC.B Rd DEC.W #1/2,Rd DEC.L #1/2,ERd DIVXS DIVXS.B Rs,Rd DIVXS.W Rs,ERd 11 19 11 19 DIVXU DIVXU.B Rs,Rd DIVXU.W Rs,ERd 800 Instruction EEPMOV Mnemonic EEPMOV.B EEPMOV.W Instruction Branch Stack Fetch Address Read Operation I J K 2 2 1 1 1 1 1 1 1 2 2 2 2 2 2 1 2 1 1 2 2 3 3 5 5 2 2 3 3 4 4 4 6 8 2 2 2 2 2 Byte Data Access L 2n + 2* 2 2n + 2* 2 Word Data Access M Internal Operation N EXTS EXTS.W Rd EXTS.L ERd EXTU EXTU.W Rd EXTU.L ERd INC INC.B Rd INC.W #1/2,Rd INC.L #1/2,ERd JMP JMP @ERn JMP @aa:24 JMP @@aa:8 1 1 JSR JSR @ERn JSR @aa:24 JSR @@aa:8 1 LDC LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1* 3 1* 3 1 1 LDM LDM.L @SP+, (ERn-ERn+1) 2 LDM.L @SP+, (ERn-ERn+2) 2 LDM.L @SP+, (ERn-ERn+3) 2 LDMAC LDMAC ERs,MACH LDMAC ERs,MACL 1 1 801 Instruction MAC MOV Mnemonic MAC @ERn+,@ERm+ MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16,ERd MOV.L @aa:32,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) Instruction Branch Stack Fetch Address Read Operation I J K 2 1 1 1 2 4 1 1 2 3 1 2 4 1 1 2 3 2 1 1 2 4 1 2 3 1 2 4 1 2 3 3 1 2 3 5 2 3 4 2 3 Byte Data Access L Word Data Access M 2 Internal Operation N 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 1 802 Instruction MOV Mnemonic MOV.L ERs,@(d:32,ERd) MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 Instruction Branch Stack Fetch Address Read Operation I J K 5 2 3 4 Byte Data Access L Word Data Access M 2 2 2 2 Internal Operation N 1 MOVFPE MOVTPE MULXS MOVFPE @:aa:16,Rd MOVTPE Rs,@:aa:16 MULXS.B Rs,Rd MULXS.W Rs,ERd Can not be used in the H8S/2626 Series or H8S/2623 Series. 2 2 1 1 1 1 1 1 1 1 1 1 1 2 1 3 2 1 2 1 2 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 2 2* 3 3* 3 2* 3 3* 3 MULXU MULXU.B Rs,Rd MULXU.W Rs,ERd NEG NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT NOP NOT.B Rd NOT.W Rd NOT.L ERd OR OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC ORC #xx:8,CCR ORC #xx:8,EXR POP POP.W Rn POP.L ERn 1 1 1 1 PUSH PUSH.W Rn PUSH.L ERn ROTL ROTL.B Rd ROTL.B #2,Rd ROTL.W Rd ROTL.W #2,Rd ROTL.L ERd ROTL.L #2,ERd ROTR ROTR.B Rd ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L ERd ROTR.L #2,ERd 803 Instruction ROTXL Mnemonic ROTXL.B Rd ROTXL.B #2,Rd ROTXL.W Rd ROTXL.W #2,Rd ROTXL.L ERd ROTXL.L #2,ERd Instruction Branch Stack Fetch Address Read Operation I J K 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2/3* 1 2 Byte Data Access L Word Data Access M Internal Operation N ROTXR ROTXR.B Rd ROTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd ROTXR.L #2,ERd RTE RTS SHAL RTE RTS SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd 1 1 SHAR SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd SHLL SHLL.B Rd SHLL.B #2,Rd SHLL.W Rd SHLL.W #2,Rd SHLL.L ERd SHLL.L #2,ERd SHLR SHLR.B Rd SHLR.B #2,Rd SHLR.W Rd SHLR.W #2,Rd SHLR.L ERd SHLR.L #2,ERd SLEEP SLEEP 1 804 Instruction STC Mnemonic STC.B CCR,Rd STC.B EXR,Rd STC.W CCR,@ERd STC.W EXR,@ERd STC.W CCR,@(d:16,ERd) STC.W EXR,@(d:16,ERd) STC.W CCR,@(d:32,ERd) STC.W EXR,@(d:32,ERd) STC.W CCR,@-ERd STC.W EXR,@-ERd STC.W CCR,@aa:16 STC.W EXR,@aa:16 STC.W CCR,@aa:32 STC.W EXR,@aa:32 Instruction Branch Stack Fetch Address Read Operation I J K 1 1 2 2 3 3 5 5 2 2 3 3 4 4 2 2 2 1 1 1 2 1 3 1 1 1 1 2 2 1 1 2 1 3 2 1 2 2 2/3* 1 4 6 8 Byte Data Access L Word Data Access M Internal Operation N 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 *3 *3 1 1 STM STM.L (ERn-ERn+1),@-SP STM.L (ERn-ERn+2),@-SP STM.L (ERn-ERn+3),@-SP STMAC* 3 STMAC MACH,ERd STMAC MACL,ERd SUB SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS SUBX SUBS #1/2/4,ERd SUBX #xx:8,Rd SUBX Rs,Rd TAS TRAPA XOR TAS @ERd * 4 2 2 TRAPA #x:2 XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd XORC XORC #xx:8,CCR XORC #xx:8,EXR Notes: *1 2 when EXR is invalid, 3 when EXR is valid. *2 5 for concatenated execution, 4 otherwise. *3 An internal operation may require between 0 and 3 additional states, depending on the preceding instruction. *4 Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. 805 A.5 Bus States during Instruction Execution Table A-6 indicates the types of cycles that occur during instruction execution by the CPU. See table A-4 for the number of states per cycle. How to Read the Table: Order of execution Instruction JMP@aa:24 1 R:W 2nd 2 3 4 5 6 7 8 Internal operation R:W EA 2 state End of instruction Read effective address (word-size read) No read or write Read 2nd word of current instruction (word-size read) Legend R:B R:W W:B W:W :M 2nd 3rd 4th 5th NEXT EA VEC Byte-size read Word-size read Byte-size write Word-size write Transfer of the bus is not performed immediately after this cycle Address of 2nd word (3rd and 4th bytes) Address of 3rd word (5th and 6th bytes) Address of 4th word (7th and 8th bytes) Address of 5th word (9th and 10th bytes) Address of next instruction Effective address Vector address 806 Figure A-1 shows timing waveforms for the address bus and the RD, HWR, and LWR signals during execution of the above instruction with an 8-bit bus, using three-state access with no wait states. o Address bus RD HWR, LWR High level R:W 2nd Fetching 3rd byte of instruction Fetching 4th byte of instruction Internal operation R:W EA Fetching 1nd byte of instruction at jump address Fetching 2nd byte of instruction at jump address Figure A-1 Address Bus, RD, HWR, and LWR Timing (8-Bit Bus, Three-State Access, No Wait States) 807 808 2 3 4 5 6 7 8 9 R:W NEXT R:W 3rd R:W NEXT R:W NEXT R:W 3rd R:W NEXT R:W NEXT R:B EA R:B EA R:W 3rd R:W 3rd R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W NEXT Table A-6 Instruction Execution Cycles Instruction ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDS #1/2/4,ERd ADDX #xx:8,Rd ADDX Rs,Rd AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd ANDC #xx:8,CCR ANDC #xx:8,EXR BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 1 R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT 3 R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA Instruction BLE d:8 BRA d:16 (BT d:16) R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd 1 R:W NEXT R:W 2nd 4 5 6 7 8 9 BRN d:16 (BF d:16) BHI d:16 BLS d:16 BCC d:16 (BHS d:16) BCS d:16 (BLO d:16) BNE d:16 BEQ d:16 BVC d:16 BVS d:16 BPL d:16 BMI d:16 BGE d:16 BLT d:16 BGT d:16 BLE d:16 2 R:W EA Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state R:B:M EA R:B:M EA R:W 3rd R:W:M NEXT W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 809 810 2 R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA 3 R:W 4th 4 R:B:M EA 5 6 R:W:M NEXT W:B EA 7 8 9 R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT 1 R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT Instruction BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR #xx:3,Rd BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BNOT #xx:3,Rd 2 R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:W EA Internal operation, 1 state R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B EA R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th W:W:M stack (H) R:W EA R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA W:W stack (L) W:W:M stack (H) W:W stack (L) R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA Instruction BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BSR d:8 BSR d:16 1 R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd 3 R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th 4 5 6 W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA 7 8 9 BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 BTST #xx:3,Rd BTST #xx:3,@ERd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA 811 812 2 R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd Internal operation, 1 state R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT 1 R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT 3 4 5 R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT 6 7 8 9 R:W NEXT R:W 3rd R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT Internal operation, 11 states R:W NEXT Internal operation, 19 states Internal operation, 11 states Internal operation, 19 states R:B EAd*1 R:B EAs*2 W:B EAd*2 R:B EAs*1 R:B EAd*1 R:B EAs*2 W:B EAd*2 R:B EAs*1 Repeated n times*2 R:W NEXT R:W NEXT Instruction BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 CLRMAC CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA Rd DAS Rd DEC.B Rd DEC.W #1/2,Rd DEC.L #1/2,ERd DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU.B Rs,Rd DIVXU.W Rs,ERd EEPMOV.B EEPMOV.W EXTS.W Rd EXTS.L ERd EXTU.W Rd EXTU.L ERd INC.B Rd Instruction INC.W #1/2,Rd INC.L #1/2,ERd JMP @ERn JMP @aa:24 R:W NEXT R:W NEXT R:W 2nd R:W EA R:W EA Internal operation, R:W EA 1 state R:W:M aa:8 R:W aa:8 1 R:W NEXT R:W NEXT R:W NEXT R:W 2nd 2 3 4 5 6 7 8 9 JMP @@aa:8 JSR @ERn JSR @aa:24 Internal operation, R:W EA 1 state R:W EA W:W:M stack (H) W:W stack (L) Internal operation, R:W EA W:W:M stack (H) W:W stack (L) 1 state R:W:M aa:8 R:W aa:8 W:W:M stack (H) W:W stack (L) R:W NEXT JSR @@aa:8 LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR R:W NEXT R:W NEXT R:W 3rd R:W 3rd R:W 3rd R:W 3rd R:W NEXT R:W EA R:W EA R:W 5th R:W 5th R:W EA R:W NEXT R:W NEXT R:W EA R:W EA R:W EA R:W NEXT R:W EA R:W NEXT R:W EA R:W:M stack (H)*3 R:W stack (L)*3 R:W EA R:W EA R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR LDM.L @SP+, (ERn-ERn+1) R:W EA R:W EA R:W NEXT R:W NEXT R:W 4th R:W 4th Internal operation, 1 state R:W NEXT Internal operation, 1 state R:W 3rd R:W NEXT R:W 3rd R:W NEXT R:W 3rd R:W 4th R:W 3rd R:W 4th R:W:M NEXT Internal operation, 1 state 813 814 1 R:W 2nd R:W 2nd R:W NEXT R:W NEXT 2 R:W NEXT 6 7 8 9 3 4 5 Internal operation, R:W:M stack (H)*3 R:W stack (L)*3 1 state R:W NEXT Internal operation, R:W:M stack (H)*3 R:W stack (L)*3 1 state Internal operation, Repeated n times*3 1 state Internal operation, 1 state R:W NEXT R:W EAn R:W EAm R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:B EA R:W 4th R:B EA R:W NEXT R:B EA R:B EA R:W NEXT R:B EA R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT W:B EA R:W 4th W:B EA R:W NEXT W:B EA R:B EA R:W NEXT R:W 3rd Internal operation, 1 state R:B EA R:W NEXT R:W 3rd W:B EA R:W NEXT R:W 3rd Internal operation, 1 state W:B EA R:W NEXT R:W 3rd R:W NEXT W:B EA R:W NEXT W:B EA R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W EA R:W 4th R:W EA R:W EA R:W NEXT R:W NEXT R:W EA R:W 2nd R:W 2nd R:W NEXT R:W EA R:W NEXT R:W 3rd Internal operation, 1 state R:W NEXT R:W 3rd W:W EA R:B EA Instruction LDM.L @SP+,(ERn-ERn+2) LDM.L @SP+,(ERn-ERn+3) LDMAC ERs,MACH LDMAC ERs,MACL MAC @ERn+,@ERm+ MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV.W @ERs+, Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd 4 R:W NEXT W:W EA Instruction MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd 1 R:W 2nd R:W 2nd R:W NEXT 3 W:W EA R:E 4th W:W EA 5 6 7 8 9 2 R:W NEXT R:W 3rd Internal operation, 1 state R:W NEXT R:W 3rd R:W 3rd W:W EA R:W NEXT R:W NEXT W:W EA MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd R:W:M NEXT R:W:M 3rd R:W:M 3rd R:W:M NEXT R:W EA+2 R:W NEXT R:W EA+2 R:W:M EA R:W EA+2 R:W:M EA R:W EA+2 R:W:M EA R:W 5th R:W:M EA R:W EA+2 R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W EA+2 MOV.L @aa:16,ERd MOV.L @aa:32,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd) MOV.L ERs,@-ERd W:W EA+2 R:W NEXT W:W EA+2 W:W EA+2 W:W:M EA R:W 2nd R:W 2nd Cannot be used in the H8S/2626 Series or H8S/2623 Series. R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd W:W:M EA R:W NEXT R:W:M EA R:W NEXT R:W:M 4th Internal operation, 1 state R:W:M 3rd R:W NEXT R:W:M 3rd R:W 4th R:W:M NEXT W:W:M EA R:W:M 3rd R:W NEXT R:W:M 3rd R:W:M 4th R:W:M NEXT Internal operation, 1 state R:W:M 3rd R:W NEXT R:W:M 3rd R:W 4th R:W:M EA R:W NEXT W:W EA+2 W:W:M EA R:W 5th W:W:M EA W:W:M EA W:W EA+2 W:W EA+2 MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MOVFPE @aa:16,Rd*4 MOVTPE Rs,@aa:16*4 MULXS.B Rs,Rd MULXS.W Rs,ERd MULXU.B Rs,Rd MULXU.W Rs,ERd NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT.B Rd NOT.W Rd NOT.L ERd OR.B #xx:8,Rd OR.B Rs,Rd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT Internal operation, 2 states R:W NEXT Internal operation, 3 states Internal operation, 2 states Internal operation, 3 states 815 816 2 R:W NEXT R:W 3rd R:W NEXT R:W NEXT 1 R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT W:W EA+2 R:W EA+2 3 4 5 6 7 8 9 R:W NEXT Internal operation, R:W EA 1 state R:W:M NEXT Internal operation, R:W:M EA 1 state Internal operation, W:W EA 1 state R:W:M NEXT Internal operation, W:W:M EA 1 state Instruction OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC #xx:8,CCR ORC #xx:8,EXR POP.W Rn POP.L ERn PUSH.W Rn PUSH.L ERn ROTL.B Rd ROTL.B #2,Rd ROTL.W Rd ROTL.W #2,Rd ROTL.L ERd ROTL.L #2,ERd ROTR.B Rd ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L ERd ROTR.L #2,ERd ROTXL.B Rd ROTXL.B #2,Rd ROTXL.W Rd ROTXL.W #2,Rd ROTXL.L ERd ROTXL.L #2,ERd ROTXR.B Rd ROTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd 2 R:W stack (EXR) R:W stack (H) R:W:M stack (H) R:W stack (L) R:W stack (L) Instruction ROTXR.L #2,ERd RTE R:W NEXT Internal operation, R:W*5 1 state Internal operation, R:W*5 1 state 1 R:W NEXT R:W NEXT 3 4 5 6 7 8 9 RTS SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd SHLL.B Rd SHLL.B #2,Rd SHLL.W Rd SHLL.W #2,Rd SHLL.L ERd SHLL.L #2,ERd SHLR.B Rd SHLR.B #2,Rd SHLR.W Rd SHLR.W #2,Rd SHLR.L ERd SHLR.L #2,ERd SLEEP STC CCR,Rd STC EXR,Rd STC CCR,@ERd STC EXR,@ERd STC CCR,@(d:16,ERd) Internal operation:M R:W NEXT R:W NEXT R:W 3rd W:W EA W:W EA R:W NEXT W:W EA R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd 817 818 5 R:W NEXT R:W NEXT W:W EA W:W EA 1 R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd W:W:M stack (H)*3 W:W stack (L)*3 W:W:M stack (H)*3 W:W stack (L)*3 W:W EA W:W EA R:W NEXT W:W EA R:W NEXT W:W EA W:W:M stack (H)*3 W:W stack (L)*3 W:W EA 2 R:W 3rd R:W 3rd R:W 3rd R:W NEXT 4 W:W EA R:W 5th R:W 5th W:W EA 6 7 8 9 3 R:W NEXT R:W 4th R:W 4th Internal operation, 1 state R:W NEXT Internal operation, 1 state R:W 3rd R:W NEXT R:W 3rd R:W NEXT R:W 3rd R:W 4th R:W 3rd R:W 4th R:W:M NEXT Internal operation, 1 state R:W:M NEXT Internal operation, 1 state R:W:M NEXT Internal operation, 1 state R:W NEXT R:W 3rd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:B:M EA Internal operation, W:W stack (L) 1 state W:B EA W:W stack (H) W:W stack (EXR) R:W:M VEC R:W VEC+2 Internal operation, R:W*8 1 state R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W 3rd R:W NEXT Instruction STC EXR,@(d:16,ERd) STC CCR,@(d:32,ERd) STC EXR,@(d:32,ERd) STC CCR,@-ERd STC EXR,@-ERd STC CCR,@aa:16 STC EXR,@aa:16 STC CCR,@aa:32 STC EXR,@aa:32 STM.L(ERn-ERn+1),@-SP STM.L(ERn-ERn+2),@-SP STM.L(ERn-ERn+3),@-SP STMAC MACH,ERd STMAC MACL,ERd SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS #1/2/4,ERd SUBX #xx:8,Rd SUBX Rs,Rd TAS @ERd *9 TRAPA #x:2 XOR.B #xx8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd Instruction XOR.L ERs,ERd XORC #xx:8,CCR XORC #xx:8,EXR Reset exception R:W NEXT R:W VEC+2 Internal operation, R:W*6 1 state Internal operation, W:W stack (L) W:W stack (H) 1 state W:W stack (EXR) R:W:M VEC R:W VEC+2 R:W*7 1 R:W 2nd R:W NEXT R:W 2nd R:W VEC 2 R:W NEXT 3 4 5 6 7 8 9 Interrupt exception Internal operation, R:W*8 1 state Notes: *1 *2 *3 *4 *5 *6 *7 *8 *9 EAs is the contents of ER5. EAd is the contents of ER6. EAs is the contents of ER5. EAd is the contents of ER6. Both registers are incremented by 1 after execution of the instruction. n is the initial value of R4L or R4. If n = 0, these bus cycles are not executed. Repeated two times to save or restore two registers, three times for three registers, or four times for four registers. Cannot be used in the H8S/2626 Series or H8S/2623 Series. Start address after return. Start address of the program. Prefetch address, equal to two plus the PC value pushed onto the stack. In recovery from sleep mode or software standby mode the read operation is replaced by an internal operation. Start address of the interrupt-handling routine. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. 819 A.6 Condition Code Modification This section indicates the effect of each CPU instruction on the condition code. The notation used in the table is defined below. m= 31 for longword operands 15 for word operands 7 for byte operands The i-th bit of the source operand The i-th bit of the destination operand The i-th bit of the result The specified bit in the destination operand Not affected Modified according to the result of the instruction (see definition) Si Di Ri Dn -- 0 1 * Z' C' Always cleared to 0 Always set to 1 Undetermined (no guaranteed value) Z flag before instruction execution C flag before instruction execution 820 Table A-7 Instruction ADD Condition Code Modification H N Z V C Definition H = Sm-4 * Dm-4 + Dm-4 * Rm-4 + Sm-4 * Rm-4 N = Rm Z = Rm * Rm-1 * ...... * R0 V = Sm * Dm * Rm + Sm * Dm * Rm C = Sm * Dm + Dm * Rm + Sm * Rm ADDS ADDX ---------- H = Sm-4 * Dm-4 + Dm-4 * Rm-4 + Sm-4 * Rm-4 N = Rm Z = Z' * Rm * ...... * R0 V = Sm * Dm * Rm + Sm * Dm * Rm C = Sm * Dm + Dm * Rm + Sm * Rm AND -- 0 -- N = Rm Z = Rm * Rm-1 * ...... * R0 ANDC Stores the corresponding bits of the result. No flags change when the operand is EXR. BAND Bcc BCLR BIAND BILD BIOR BIST BIXOR BLD BNOT BOR BSET BSR BST BTST BXOR CLRMAC -------- ---------- ---------- -------- -------- -------- ---------- -------- -------- ---------- -------- ---------- ---------- ---------- ---- ---- C = C' * Dn C = C' * Dn C = Dn C = C' + Dn C = C' * Dn + C' * Dn C = Dn C = C' + Dn Z = Dn C = C' * Dn + C' * Dn -------- ---------- 821 Instruction CMP H N Z V C Definition H = Sm-4 * Dm-4 + Dm-4 * Rm-4 + Sm-4 * Rm-4 N = Rm Z = Rm * Rm-1 * ...... * R0 V = Sm * Dm * Rm + Sm * Dm * Rm C = Sm * Dm + Dm * Rm + Sm * Rm DAA * * N = Rm Z = Rm * Rm-1 * ...... * R0 C: decimal arithmetic carry DAS * * N = Rm Z = Rm * Rm-1 * ...... * R0 C: decimal arithmetic borrow DEC -- -- N = Rm Z = Rm * Rm-1 * ...... * R0 V = Dm * Rm DIVXS -- ---- N = Sm * Dm + Sm * Dm Z = Sm * Sm-1 * ...... * S0 N = Sm Z = Sm * Sm-1 * ...... * S0 DIVXU -- ---- EEPMOV EXTS ---------- -- 0 -- N = Rm Z = Rm * Rm-1 * ...... * R0 Z = Rm * Rm-1 * ...... * R0 N = Rm Z = Rm * Rm-1 * ...... * R0 V = Dm * Rm EXTU INC --0 -- 0 -- -- JMP JSR LDC ---------- ---------- Stores the corresponding bits of the result. No flags change when the operand is EXR. LDM LDMAC MAC ---------- ---------- ---------- 822 Instruction MOV H -- N Z V 0 C -- Definition N = Rm Z = Rm * Rm-1 * ...... * R0 MOVFPE MOVTPE MULXS -- ---- Can not be used in the H8S/2626 Series or H8S/2623 Series. N = R2m Z = R2m * R2m-1 * ...... * R0 MULXU NEG ---------- H = Dm-4 + Rm-4 N = Rm Z = Rm * Rm-1 * ...... * R0 V = Dm * Rm C = Dm + Rm NOP NOT ---------- -- 0 -- N = Rm Z = Rm * Rm-1 * ...... * R0 OR -- 0 -- N = Rm Z = Rm * Rm-1 * ...... * R0 ORC Stores the corresponding bits of the result. No flags change when the operand is EXR. POP -- 0 -- N = Rm Z = Rm * Rm-1 * ...... * R0 PUSH -- 0 -- N = Rm Z = Rm * Rm-1 * ...... * R0 ROTL -- 0 N = Rm Z = Rm * Rm-1 * ...... * R0 C = Dm (1-bit shift) or C = Dm-1 (2-bit shift) ROTR -- 0 N = Rm Z = Rm * Rm-1 * ...... * R0 C = D0 (1-bit shift) or C = D1 (2-bit shift) 823 Instruction ROTXL H -- N Z V 0 C Definition N = Rm Z = Rm * Rm-1 * ...... * R0 C = Dm (1-bit shift) or C = Dm-1 (2-bit shift) ROTXR -- 0 N = Rm Z = Rm * Rm-1 * ...... * R0 C = D0 (1-bit shift) or C = D1 (2-bit shift) RTE RTS SHAL ---------- -- Stores the corresponding bits of the result. N = Rm Z = Rm * Rm-1 * ...... * R0 V = Dm * Dm-1 + Dm * Dm-1 (1-bit shift) V = Dm * Dm-1 * Dm-2 * Dm * Dm-1 * Dm-2 (2-bit shift) C = Dm (1-bit shift) or C = Dm-1 (2-bit shift) SHAR -- 0 N = Rm Z = Rm * Rm-1 * ...... * R0 C = D0 (1-bit shift) or C = D1 (2-bit shift) SHLL -- 0 N = Rm Z = Rm * Rm-1 * ...... * R0 C = Dm (1-bit shift) or C = Dm-1 (2-bit shift) SHLR --0 0 N = Rm Z = Rm * Rm-1 * ...... * R0 C = D0 (1-bit shift) or C = D1 (2-bit shift) SLEEP STC STM STMAC ---------- ---------- ---------- -- -- N = 1 if MAC instruction resulted in negative value in MAC register Z = 1 if MAC instruction resulted in zero value in MAC register V = 1 if MAC instruction resulted in overflow 824 Instruction SUB H N Z V C Definition H = Sm-4 * Dm-4 + Dm-4 * Rm-4 + Sm-4 * Rm-4 N = Rm Z = Rm * Rm-1 * ...... * R0 V = Sm * Dm * Rm + Sm * Dm * Rm C = Sm * Dm + Dm * Rm + Sm * Rm SUBS SUBX ---------- H = Sm-4 * Dm-4 + Dm-4 * Rm-4 + Sm-4 * Rm-4 N = Rm Z = Z' * Rm * ...... * R0 V = Sm * Dm * Rm + Sm * Dm * Rm C = Sm * Dm + Dm * Rm + Sm * Rm TAS -- 0 -- N = Dm Z = Dm * Dm-1 * ...... * D0 TRAPA XOR ---------- -- 0 -- N = Rm Z = Rm * Rm-1 * ...... * R0 XORC Stores the corresponding bits of the result. No flags change when the operand is EXR. 825 Appendix B Internal I/O Register B.1 Address H'EBC0 to H'EFBF Address Register Name MRA MRB SAR Bit 7 SM1 CHNE Bit 6 SM0 DISEL Bit 5 DM1 -- Bit 4 DM0 -- Bit 3 MD1 -- Bit 2 MD0 -- Bit 1 DTS -- Bit 0 Sz -- Module Name DTC Data Bus Width 1 16/32* bits DAR CRA CRB H'F800 H'F801 H'F802 H'F803 H'F804 H'F805 H'F806 H'F807 H'F808 H'F809 H'F80A H'F80B H'F80C H'F80D H'F80E H'F80F H'F810 H'F811 H'F812 H'F813 MCR GSR BCR MCR7 -- BCR7 BCR15 -- -- BCR6 BCR14 MBCR6 MBCR14 TXPR6 TXPR14 TXCR6 TXCR14 TXACK6 TXACK14 ABACK6 ABACK14 RXPR6 RXPR14 RFPR6 RFPR14 IRR6 -- MCR5 -- BCR5 BCR13 MBCR5 MBCR13 TXPR5 TXPR13 TXCR5 TXCR13 TXACK5 TXACK13 ABACK5 ABACK13 RXPR5 RXPR13 RFPR5 RFPR13 IRR5 -- -- -- BCR4 BCR12 MBCR4 MBCR12 TXPR4 TXPR12 TXCR4 TXCR12 TXACK4 TXACK12 ABACK4 ABACK12 RXPR4 RXPR12 RFPR4 RFPR12 IRR4 IRR12 -- GSR3 BCR3 BCR11 MBCR3 MBCR11 TXPR3 TXPR11 TXCR3 TXCR11 TXACK3 TXACK11 ABACK3 ABACK11 RXPR3 RXPR11 RFPR3 RFPR11 IRR3 -- MCR2 GSR2 BCR2 BCR10 MBCR2 MBCR10 TXPR2 TXPR10 TXCR2 TXCR10 TXACK2 TXACK10 ABACK2 ABACK10 RXPR2 RXPR10 RFPR2 RFPR10 IRR2 -- MCR1 GSR1 BCR1 BCR9 MBCR1 MBCR9 TXPR1 TXPR9 TXCR1 TXCR9 TXACK1 TXACK9 ABACK1 ABACK9 RXPR1 RXPR9 RFPR1 RFPR9 IRR1 IRR9 MCR0 GSR0 BCR0 BCR8 -- MBCR8 -- TXPR8 -- TXCR8 -- TXACK8 -- ABACK8 RXPR0 RXPR8 RFPR0 RFPR8 IRR0 IRR8 HCAN 8 8 8, 16 16 MBCR MBCR7 MBCR15 TXPR TXPR7 TXPR15 TXCR TXCR7 TXCR15 TXACK TXACK7 TXACK15 ABACK ABACK7 ABACK15 RXPR RXPR7 RXPR15 RFPR RFPR7 RFPR15 IRR IRR7 -- 826 Address H'F814 H'F815 H'F816 H'F817 H'F818 H'F819 H'F81A H'F81B H'F81C H'F81D H'F81E H'F81F H'F820 H'F821 H'F822 H'F823 H'F824 H'F825 H'F826 H'F827 H'F828 H'F829 H'F82A H'F82B H'F82C H'F82D H'F82E H'F82F H'F830 H'F831 H'F832 H'F833 H'F834 H'F835 H'F836 H'F837 H'F838 H'F839 Register Name MBIMR Bit 7 MBIMR7 MBIMR15 Bit 6 MBIMR6 MBIMR14 IMR6 -- Bit 5 MBIMR5 MBIMR13 IMR5 -- Bit 4 MBIMR4 MBIMR12 IMR4 IMR12 Bit 3 MBIMR3 MBIMR11 IMR3 -- Bit 2 MBIMR2 MBIMR10 IMR2 -- Bit 1 MBIMR1 MBIMR9 IMR1 IMR9 Bit 0 MBIMR0 MBIMR8 -- IMR8 Module Name HCAN Data Bus Width 8, 16 IMR IMR7 -- REC TEC UMSR UMSR7 UMSR15 LAFML LAFML7 LAFML15 LAFMH LAFMH7 LAFMH15 MC0[1] MC0[2] MC0[3] MC0[4] MC0[5] MC0[6] MC0[7] MC0[8] MC1[1] MC1[2] MC1[3] MC1[4] MC1[5] MC1[6] MC1[7] MC1[8] MC2[1] MC2[2] MC2[3] MC2[4] MC2[5] MC2[6] MC2[7] MC2[8] MC3[1] MC3[2] -- -- -- -- STD_ID2 UMSR6 UMSR14 LAFML6 LAFML14 LAFMH6 LAFMH14 -- -- -- -- STD_ID1 UMSR5 UMSR13 LAFML5 LAFML13 LAFMH5 LAFMH13 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 UMSR4 UMSR12 LAFML4 LAFML12 -- LAFMH12 -- -- -- -- RTR STD_ID7 EXD_ID4 UMSR3 UMSR11 LAFML3 LAFML11 -- LAFMH11 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 UMSR2 UMSR10 LAFML2 LAFML10 -- LAFMH10 DLC2 -- -- -- -- STD_ID5 EXD_ID2 UMSR1 UMSR9 LAFML1 LAFML9 LAFMH1 LAFMH9 DLC1 -- -- -- UMSR0 UMSR8 LAFML0 LAFML8 LAFMH0 LAFMH8 DLC0 -- -- -- 8 8 8, 16 16 EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 DLC0 -- -- -- STD_ID10 STD_ID9 EXD_ID7 EXD_ID6 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 -- -- -- -- STD_ID2 -- -- -- -- STD_ID1 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 -- -- -- -- RTR STD_ID7 EXD_ID4 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 DLC2 -- -- -- -- STD_ID5 EXD_ID2 DLC1 -- -- -- EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 DLC0 -- -- -- STD_ID10 STD_ID9 EXD_ID7 EXD_ID6 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 -- -- -- -- STD_ID2 -- -- -- -- STD_ID1 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 -- -- -- -- RTR STD_ID7 EXD_ID4 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 DLC2 -- -- -- -- STD_ID5 EXD_ID2 DLC1 -- -- -- EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 DLC0 -- STD_ID10 STD_ID9 EXD_ID7 EXD_ID6 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 -- -- -- -- -- -- -- -- DLC3 -- DLC2 -- DLC1 -- 827 Address H'F83A H'F83B H'F83C H'F83D H'F83E H'F83F H'F840 H'F841 H'F842 H'F843 H'F844 H'F845 H'F846 H'F847 H'F848 H'F849 H'F84A H'F84B H'F84C H'F84D H'F84E H'F84F H'F850 H'F851 H'F852 H'F853 H'F854 H'F855 H'F856 H'F857 H'F858 H'F859 H'F85A H'F85B H'F85C H'F85D H'F85E Register Name MC3[3] MC3[4] MC3[5] MC3[6] MC3[7] MC3[8] MC4[1] MC4[2] MC4[3] MC4[4] MC4[5] MC4[6] MC4[7] MC4[8] MC5[1] MC5[2] MC5[3] MC5[4] MC5[5] MC5[6] MC5[7] MC5[8] MC6[1] MC6[2] MC6[3] MC6[4] MC6[5] MC6[6] MC6[7] MC6[8] MC7[1] MC7[2] MC7[3] MC7[4] MC7[5] MC7[6] MC7[7] Bit 7 -- -- STD_ID2 Bit 6 -- -- STD_ID1 Bit 5 -- -- STD_ID0 STD_ID8 EXD_ID5 Bit 4 -- -- RTR STD_ID7 EXD_ID4 Bit 3 -- -- IDE STD_ID6 EXD_ID3 Bit 2 -- -- -- STD_ID5 EXD_ID2 Bit 1 -- -- Bit 0 -- -- Module Name HCAN Data Bus Width 8, 16 EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 DLC0 -- -- -- STD_ID10 STD_ID9 EXD_ID7 EXD_ID6 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 -- -- -- -- STD_ID2 -- -- -- -- STD_ID1 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 -- -- -- -- RTR STD_ID7 EXD_ID4 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 DLC2 -- -- -- -- STD_ID5 EXD_ID2 DLC1 -- -- -- EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 DLC0 -- -- -- STD_ID10 STD_ID9 EXD_ID7 EXD_ID6 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 -- -- -- -- STD_ID2 -- -- -- -- STD_ID1 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 -- -- -- -- RTR STD_ID7 EXD_ID4 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 DLC2 -- -- -- -- STD_ID5 EXD_ID2 DLC1 -- -- -- EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 DLC0 -- -- -- STD_ID10 STD_ID9 EXD_ID7 EXD_ID6 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 -- -- -- -- STD_ID2 -- -- -- -- STD_ID1 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 -- -- -- -- RTR STD_ID7 EXD_ID4 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 DLC2 -- -- -- -- STD_ID5 EXD_ID2 DLC1 -- -- -- EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 DLC0 -- -- -- STD_ID10 STD_ID9 EXD_ID7 EXD_ID6 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 -- -- -- -- STD_ID2 -- -- -- -- STD_ID1 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 -- -- -- -- RTR STD_ID7 EXD_ID4 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 DLC2 -- -- -- -- STD_ID5 EXD_ID2 DLC1 -- -- -- EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 STD_ID10 STD_ID9 EXD_ID7 EXD_ID6 828 Address H'F85F H'F860 H'F861 H'F862 H'F863 H'F864 H'F865 H'F866 H'F867 H'F868 H'F869 H'F86A H'F86B H'F86C H'F86D H'F86E H'F86F H'F870 H'F871 H'F872 H'F873 H'F874 H'F875 H'F876 H'F877 H'F878 H'F879 H'F87A H'F87B H'F87C H'F87D H'F87E H'F87F H'F880 H'F881 H'F882 H'F883 Register Name MC7[8] MC8[1] MC8[2] MC8[3] MC8[4] MC8[5] MC8[6] MC8[7] MC8[8] MC9[1] MC9[2] MC9[3] MC9[4] MC9[5] MC9[6] MC9[7] MC9[8] MC10[1] MC10[2] MC10[3] MC10[4] MC10[5] MC10[6] MC10[7] MC10[8] MC11[1] MC11[2] MC11[3] MC11[4] MC11[5] MC11[6] MC11[7] MC11[8] MC12[1] MC12[2] MC12[3] MC12[4] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EXD_ID8 DLC0 -- -- -- Module Name HCAN Data Bus Width 8, 16 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 -- -- -- -- STD_ID2 -- -- -- -- STD_ID1 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 -- -- -- -- RTR STD_ID7 EXD_ID4 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 DLC2 -- -- -- -- STD_ID5 EXD_ID2 DLC1 -- -- -- EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 DLC0 -- -- -- STD_ID10 STD_ID9 EXD_ID7 EXD_ID6 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 -- -- -- -- STD_ID2 -- -- -- -- STD_ID1 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 -- -- -- -- RTR STD_ID7 EXD_ID4 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 DLC2 -- -- -- -- STD_ID5 EXD_ID2 DLC1 -- -- -- EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 DLC0 -- -- -- STD_ID10 STD_ID9 EXD_ID7 EXD_ID6 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 -- -- -- -- STD_ID2 -- -- -- -- STD_ID1 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 -- -- -- -- RTR STD_ID7 EXD_ID4 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 DLC2 -- -- -- -- STD_ID5 EXD_ID2 DLC1 -- -- -- EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 DLC0 -- -- -- STD_ID10 STD_ID9 EXD_ID7 EXD_ID6 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 -- -- -- -- STD_ID2 -- -- -- -- STD_ID1 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 -- -- -- -- RTR STD_ID7 EXD_ID4 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 DLC2 -- -- -- -- STD_ID5 EXD_ID2 DLC1 -- -- -- EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 DLC0 -- -- -- STD_ID10 STD_ID9 EXD_ID7 EXD_ID6 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- DLC3 -- -- -- DLC2 -- -- -- DLC1 -- -- -- 829 Address H'F884 H'F885 H'F886 H'F887 H'F888 H'F889 H'F88A H'F88B H'F88C H'F88D H'F88E H'F88F H'F890 H'F891 H'F892 H'F893 H'F894 H'F895 H'F896 H'F897 H'F898 H'F899 H'F89A H'F89B H'F89C H'F89D H'F89E H'F89F H'F8B0 H'F8B1 H'F8B2 H'F8B3 H'F8B4 H'F8B5 H'F8B6 H'F8B7 H'F8B8 Register Name MC12[5] MC12[6] MC12[7] MC12[8] MC13[1] MC13[2] MC13[3] MC13[4] MC13[5] MC13[6] MC13[7] MC13[8] MC14[1] MC14[2] MC14[3] MC14[4] MC14[5] MC14[6] MC14[7] MC14[8] MC15[1] MC15[2] MC15[3] MC15[4] MC15[5] MC15[6] MC15[7] MC15[8] MD0[1] MD0[2] MD0[3] MD0[4] MD0[5] MD0[6] MD0[7] MD0[8] MD1[1] Bit 7 STD_ID2 Bit 6 STD_ID1 Bit 5 STD_ID0 STD_ID8 EXD_ID5 Bit 4 RTR STD_ID7 EXD_ID4 Bit 3 IDE STD_ID6 EXD_ID3 Bit 2 -- STD_ID5 EXD_ID2 Bit 1 Bit 0 Module Name HCAN Data Bus Width 8, 16 EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 DLC0 -- -- -- STD_ID10 STD_ID9 EXD_ID7 EXD_ID6 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 -- -- -- -- STD_ID2 -- -- -- -- STD_ID1 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 -- -- -- -- RTR STD_ID7 EXD_ID4 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 DLC2 -- -- -- -- STD_ID5 EXD_ID2 DLC1 -- -- -- EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 DLC0 -- -- -- STD_ID10 STD_ID9 EXD_ID7 EXD_ID6 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 -- -- -- -- STD_ID2 -- -- -- -- STD_ID1 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 -- -- -- -- RTR STD_ID7 EXD_ID4 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 DLC2 -- -- -- -- STD_ID5 EXD_ID2 DLC1 -- -- -- EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 DLC0 -- -- -- STD_ID10 STD_ID9 EXD_ID7 EXD_ID6 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 -- -- -- -- STD_ID2 -- -- -- -- STD_ID1 -- -- -- -- STD_ID0 STD_ID8 EXD_ID5 -- -- -- -- RTR STD_ID7 EXD_ID4 DLC3 -- -- -- IDE STD_ID6 EXD_ID3 DLC2 -- -- -- -- STD_ID5 EXD_ID2 DLC1 -- -- -- EXD_ID17 EXD_ID16 STD_ID4 EXD_ID1 STD_ID3 EXD_ID0 EXD_ID8 STD_ID10 STD_ID9 EXD_ID7 EXD_ID6 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 830 Address H'F8B9 H'F8BA H'F8BB H'F8BC H'F8BD H'F8BE H'F8BF H'F8C0 H'F8C1 H'F8C2 H'F8C3 H'F8C4 H'F8C5 H'F8C6 H'F8C7 H'F8C8 H'F8C9 H'F8CA H'F8CB H'F8CC H'F8CD H'F8CE H'F8CF H'F8D0 H'F8D1 H'F8D2 H'F8D3 H'F8D4 H'F8D5 H'F8D6 H'F8D7 H'F8D8 H'F8D9 H'F8DA H'F8DB H'F8DC H'F8DD Register Name MD1[2] MD1[3] MD1[4] MD1[5] MD1[6] MD1[7] MD1[8] MD2[1] MD2[2] MD2[3] MD2[4] MD2[5] MD2[6] MD2[7] MD2[8] MD3[1] MD3[2] MD3[3] MD3[4] MD3[5] MD3[6] MD3[7] MD3[8] MD4[1] MD4[2] MD4[3] MD4[4] MD4[5] MD4[6] MD4[7] MD4[8] MD5[1] MD5[2] MD5[3] MD5[4] MD5[5] MD5[6] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name HCAN Data Bus Width 8, 16 831 Address H'F8DE H'F8DF H'F8E0 H'F8E1 H'F8E2 H'F8E3 H'F8E4 H'F8E5 H'F8E6 H'F8E7 H'F8E8 H'F8E9 H'F8EA H'F8EB H'F8EC H'F8ED H'F8EE H'F8EF H'F8F0 H'F8F1 H'F8F2 H'F8F3 H'F8F4 H'F8F5 H'F8F6 H'F8F7 H'F8F8 H'F8F9 H'F8FA H'F8FB H'F8FC H'F8FD H'F8FE H'F8FF H'F900 H'F901 H'F902 Register Name MD5[7] MD5[8] MD6[1] MD6[2] MD6[3] MD6[4] MD6[5] MD6[6] MD6[7] MD6[8] MD7[1] MD7[2] MD7[3] MD7[4] MD7[5] MD7[6] MD7[7] MD7[8] MD8[1] MD8[2] MD8[3] MD8[4] MD8[5] MD8[6] MD8[7] MD8[8] MD9[1] MD9[2] MD9[3] MD9[4] MD9[5] MD9[6] MD9[7] MD9[8] MD10[1] MD10[2] MD10[3] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name HCAN Data Bus Width 8, 16 832 Address H'F903 H'F904 H'F905 H'F906 H'F907 H'F908 H'F909 H'F90A H'F90B H'F90C H'F90D H'F90E H'F90F H'F910 H'F911 H'F912 H'F913 H'F914 H'F915 H'F916 H'F917 H'F918 H'F919 H'F91A H'F91B H'F91C H'F91D H'F91E H'F91F H'F920 H'F921 H'F922 H'F923 H'F924 H'F925 H'F926 H'F927 H'F928 Register Name MD10[4] MD10[5] MD10[6] MD10[7] MD10[8] MD11[1] MD11[2] MD11[3] MD11[4] MD11[5] MD11[6] MD11[7] MD11[8] MD12[1] MD12[2] MD12[3] MD12[4] MD12[5] MD12[6] MD12[7] MD12[8] MD13[1] MD13[2] MD13[3] MD13[4] MD13[5] MD13[6] MD13[7] MD13[8] MD14[1] MD14[2] MD14[3] MD14[4] MD14[5] MD14[6] MD14[7] MD14[8] MD15[1] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name HCAN Data Bus Width 8, 16 833 Address H'F929 H'F92A H'F92B H'F92C H'F92D H'F92E H'F92F H'FDAC H'FDAD H'FDAE H'FDB4 H'FDE4 Register Name MD15[2] MD15[3] MD15[4] MD15[5] MD15[6] MD15[7] MD15[8] DADR2*6 DADR3*6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name HCAN Data Bus Width 8, 16 Bit 7 Bit 7 Bit 6 Bit 6 DAOE0 -- STS2 Bit 5 Bit 5 DAE -- STS1 Bit 4 Bit 4 -- -- STS0 Bit 3 Bit 3 -- FLSHE OPE Bit 2 Bit 2 -- -- -- Bit 1 Bit 1 -- -- -- Bit 0 Bit 0 -- -- -- D/A converter 8 DACR23*6 DAOE1 SCRX SBYCR -- SSBY ROM 8 Power8 down state MCU, RAM interrupt controller 8 H'FDE5 SYSCR MACS -- INTM1 INTM0 NMIEG -- -- RAME H'FDE6 SCKCR PSTOP -- -- -- STCS SCK2 SCK1 SCK0 Clock 8 pulse generator, power-down state MCU 8 H'FDE7 H'FDE8 MDCR -- -- MSTPA6 -- MSTPA5 -- MSTPA4 -- MSTPA3 MDS2 MSTPA2 MDS1 MSTPA1 MDS0 MSTPA0 MSTPCRA MSTPA7 Power8 down state H'FDE9 H'FDEA H'FDEB MSTPCRB MSTPB7 MSTPCRC MSTPC7 PFCR -- MSTPB6 MSTPC6 -- MSTPB5 MSTPC5 BUZZE*4 MSTPB4 MSTPC4 -- MSTPB3 MSTPC3 AE3 MSTPB2 MSTPC2 AE2 MSTPB1 MSTPC1 AE1 MSTPB0 MSTPC0 AE0 MCU, bus controller Clock pulse generator PC break controller 8 H'FDEC LPWRCR DTON*4 LSON*4 NESEL*4 SUBSTP*4 RFCUT -- STC1 STC0 8 H'FE00 BARA -- BAA23 BAA15 BAA7 -- BAA22 BAA14 BAA6 -- BAA22 BAA14 BAA6 CDA CDB -- BAA21 BAA13 BAA5 -- BAA21 BAA13 BAA5 BAMRA2 BAMRB2 -- BAA20 BAA12 BAA4 -- BAA20 BAA12 BAA4 BAMRA1 BAMRB1 -- BAA19 BAA11 BAA3 -- BAA19 BAA11 BAA3 BAMRA0 BAMRA0 -- BAA18 BAA10 BAA2 -- BAA18 BAA10 BAA2 CSELA1 CSELB1 -- BAA17 BAA9 BAA1 -- BAA17 BAA9 BAA1 CSELA0 CSELB0 -- BAA16 BAA8 BAA0 -- BAA16 BAA8 BAA0 BIEA BIEB 8 H'FE04 BARB -- BAA23 BAA15 BAA7 H'FE08 H'FE09 BCRA BCRB CMFA CMFB 834 Address H'FE12 H'FE13 H'FE14 H'FE15 H'FE16 H'FE17 H'FE18 H'FE19 H'FE1A H'FE1B H'FE1C H'FE1F H'FE26 H'FE27 H'FE28 H'FE29 H'FE2A H'FE2B H'FE2C H'FE2D H'FE2E H'FE2F H'FE30 H'FE39 H'FE3A H'FE3B H'FE3C H'FE3D H'FE3E H'FE40 H'FE41 H'FE42 H'FE43 H'FE44 H'FE47 H'FE48 H'FE49 Register Name ISCRH ISCRL IER ISR DTCERA DTCERB DTCERC DTCERD DTCERE DTCERF DTCERG DTVECR PCR PMR NDERH NDERL PODRH PODRL NDRH*2 NDRL* 2 Bit 7 -- IRQ3SCB -- -- DTCEA7 DTCEB7 DTCEC7 DTCED7 DTCEE7 DTCEF7 DTCEG7 SWDTE G3CMS1 G3INV NDER15 NDER7 POD15 POD7 NDR15 NDR7 -- -- P17DDR -- PB7DDR PC7DDR PD7DDR PE7DDR PF7DDR -- PB7PCR PC7PCR PD7PCR PE7PCR -- PB7ODR PC7ODR Bit 6 -- IRQ3SCA -- -- DTCEA6 DTCEB6 DTCEC6 DTCED6 DTCEE6 DTCEF6 DTCEG6 DTVEC6 G3CMS0 G2INV NDER14 NDER6 POD14 POD6 NDR14 NDR6 -- -- P16DDR -- PB6DDR PC6DDR PD6DDR PE6DDR PF6DDR -- PB6PCR PC6PCR PD6PCR PE6PCR -- PB6ODR PC6ODR Bit 5 -- IRQ2SCB IRQ5E IRQ5F DTCEA5 DTCEB5 DTCEC5 DTCED5 DTCEE5 DTCEF5 DTCEG5 DTVEC5 G2CMS1 G1INV NDER13 NDER5 POD13 POD5 NDR13 NDR5 -- -- P15DDR PA5DDR* PB5DDR PC5DDR PD5DDR PE5DDR PF5DDR PA5PCR* PB5PCR PC5PCR PD5PCR PE5PCR 5 5 Bit 4 -- IRQ2SCA IRQ4E IRQ4F DTCEA4 DTCEB4 DTCEC4 DTCED4 DTCEE4 DTCEF4 DTCEG4 DTVEC4 G2CMS0 G0INV NDER12 NDER4 POD12 POD4 NDR12 NDR4 -- -- P14DDR PA4DDR* PB4DDR PC4DDR PD4DDR PE4DDR PF4DDR PA4PCR* PB4PCR PC4PCR PD4PCR PE4PCR 5 5 Bit 3 IRQ5SCB IRQ1SCB IRQ3E IRQ3F DTCEA3 DTCEB3 DTCEC3 DTCED3 DTCEE3 DTCEF3 DTCEG3 DTVEC3 G1CMS1 G3NOV NDER11 NDER3 POD11 POD3 NDR11 NDR3 NDR11 NDR3 P13DDR PA3DDR PB3DDR PC3DDR PD3DDR PE3DDR PF3DDR PA3PCR PB3PCR PC3PCR PD3PCR PE3PCR Bit 2 IRQ5SCA IRQ1SCA IRQ2E IRQ2F DTCEA2 DTCEB2 DTCEC2 DTCED2 DTCEE2 DTCEF2 DTCEG2 DTVEC2 G1CMS0 G2NOV NDER10 NDER2 POD10 POD2 NDR10 NDR2 NDR10 NDR2 P12DDR PA2DDR PB2DDR PC2DDR PD2DDR PE2DDR PF2DDR PA2PCR PB2PCR PC2PCR PD2PCR PE2PCR PA2ODR PB2ODR PC2ODR Bit 1 IRQ4SCB IRQ0SCB IRQ1E IRQ1F DTCEA1 DTCEB1 DTCEC1 DTCED1 DTCEE1 DTCEF1 DTCEG1 DTVEC1 G0CMS1 G1NOV NDER9 NDER1 POD9 POD1 NDR9 NDR1 NDR9 NDR1 P11DDR PA1DDR PB1DDR PC1DDR PD1DDR PE1DDR PF1DDR PA1PCR PB1PCR PC1PCR PD1PCR PE1PCR PA1ODR PB1ODR PC1ODR Bit 0 IRQ4SCA IRQ0SCA IRQ0E IRQ0F DTCEA0 DTCEB0 DTCEC0 DTCED0 DTCEE0 DTCEF0 DTCEG0 DTVEC0 G0CMS0 G0NOV NDER8 NDER0 POD8 POD0 NDR8 NDR0 NDR8 NDR0 P10DDR PA0DDR PB0DDR PC0DDR PD0DDR PE0DDR PF0DDR PA0PCR PB0PCR PC0PCR PD0PCR PE0PCR PA0ODR PB0ODR PC0ODR Module Name Interrupt controller Data Bus Width 8 DTC 8 PPG 8 NDRH*2 NDRL*2 P1DDR PADDR PBDDR PCDDR PDDDR PEDDR PFDDR PAPCR PBPCR PCPCR PDPCR PEPCR PAODR PBODR PCODR I/O port 8 PA5ODR*5 PA4ODR*5 PA3ODR PB5ODR PC5ODR PB4ODR PC4ODR PB3ODR PC3ODR 835 Address H'FE80 H'FE81 H'FE82 H'FE83 H'FE84 H'FE85 H'FE86 H'FE87 H'FE88 H'FE89 H'FE8A H'FE8B H'FE8C H'FE8D H'FE8E H'FE8F H'FE90 H'FE91 H'FE92 H'FE94 H'FE95 H'FE96 H'FE97 H'FE98 H'FE99 H'FE9A H'FE9B H'FEA0 H'FEA1 H'FEA2 H'FEA4 H'FEA5 H'FEA6 H'FEA7 H'FEA8 H'FEA9 H'FEAA H'FEAB Register Name TCR3 TMDR3 TIOR3H TIOR3L TIER3 TSR3 TCNT3 Bit 7 CCLR2 -- IOB3 IOD3 TTGE -- Bit 6 CCLR1 -- IOB2 IOD2 -- -- Bit 5 CCLR0 BFB IOB1 IOD1 -- -- Bit 4 CKEG1 BFA IOB0 IOD0 TCIEV TCFV Bit 3 CKEG0 MD3 IOA3 IOC3 TGIED TGFD Bit 2 TPSC2 MD2 IOA2 IOC2 TGIEC TGFC Bit 1 TPSC1 MD1 IOA1 IOC1 TGIEB TGFB Bit 0 TPSC0 MD0 IOA0 IOC0 TGIEA TGFA Module Name TPU3 Data Bus Width 16 TGR3A TGR3B TGR3C TGR3D TCR4 TMDR4 TIOR4 TIER4 TSR4 TCNT4 -- -- IOB3 TTGE TCFD CCLR1 -- IOB2 -- -- CCLR0 -- IOB1 TCIEU TCFU CKEG1 -- IOB0 TCIEV TCFV CKEG0 MD3 IOA3 -- -- TPSC2 MD2 IOA2 -- -- TPSC1 MD1 IOA1 TGIEB TGFB TPSC0 MD0 IOA0 TGIEA TGFA TPU4 16 TGR4A TGR4B TCR5 TMDR5 TIOR5 TIER5 TSR5 TCNT5 -- -- IOB3 TTGE TCFD CCLR1 -- IOB2 -- -- CCLR0 -- IOB1 TCIEU TCFU CKEG1 -- IOB0 TCIEV TCFV CKEG0 MD3 IOA3 -- -- TPSC2 MD2 IOA2 -- -- TPSC1 MD1 IOA1 TGIEB TGFB TPSC0 MD0 IOA0 TGIEA TGFA TPU5 16 TGR5A TGR5B 836 Address H'FEB0 H'FEB1 H'FEC0 H'FEC1 H'FEC2 H'FEC3 H'FEC4 H'FEC5 H'FEC6 H'FEC7 H'FEC8 H'FEC9 H'FECA H'FECC H'FED0 H'FED1 H'FED2 H'FED3 H'FED4 H'FED5 H'FEDB H'FF00 H'FF09 H'FF0A H'FF0B H'FF0C H'FF0D H'FF0E H'FF10 H'FF11 H'FF12 H'FF13 H'FF14 H'FF15 H'FF16 H'FF17 Register Name TSTR TSYR IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK IPRM ABWCR ASTCR WCRH WCRL BCRH BCRL RAMER*3 P1DR PADR PBDR PCDR PDDR PEDR PFDR TCR0 TMDR0 TIOR0H TIOR0L TIER0 TSR0 TCNT0 Bit 7 -- -- -- -- -- -- -- -- -- -- -- -- -- -- ABW7 AST7 W71 W31 ICIS1 BRLE -- P17DR -- PB7DR PC7DR PD7DR PE7DR PF7DR CCLR2 -- IOB3 IOD3 TTGE -- Bit 6 -- -- IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 ABW6 AST6 W70 W30 ICIS0 BREQOE -- P16DR -- PB6DR PC6DR PD6DR PE6DR PF6DR CCLR1 -- IOB2 IOD2 -- -- Bit 5 CST5 SYNC5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 ABW5 AST5 W61 W21 BRSTRM -- -- P15DR PA5DR*5 PB5DR PC5DR PD5DR PE5DR PF5DR CCLR0 BFB IOB1 IOD1 -- -- Bit 4 CST4 SYNC4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 ABW4 AST4 W60 W20 BRSTS1 -- -- P14DR PA4DR*5 PB4DR PC4DR PD4DR PE4DR PF4DR CKEG1 BFA IOB0 IOD0 TCIEV TCFV Bit 3 CST3 SYNC3 -- -- -- -- -- -- -- -- -- -- -- -- ABW3 AST3 W51 W11 BRSTS0 -- RAMS P13DR PA3DR PB3DR PC3DR PD3DR PE3DR PF3DR CKEG0 MD3 IOA3 IOC3 TGIED TGFD Bit 2 CST2 SYNC2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 ABW2 AST2 W50 W10 -- -- RAM2 P12DR PA2DR PB2DR PC2DR PD2DR PE2DR PF2DR TPSC2 MD2 IOA2 IOC2 TGIEC TGFC Bit 1 CST1 SYNC1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 ABW1 AST1 W41 W01 -- WDBE RAM1 P11DR PA1DR PB1DR PC1DR PD1DR PE1DR PF1DR TPSC1 MD1 IOA1 IOC1 TGIEB TGFB Bit 0 CST0 SYNC0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 ABW0 AST0 W40 W00 -- WAITE RAM0 P10DR PA0DR PB0DR PC0DR PD0DR PE0DR PF0DR TPSC0 MD0 IOA0 IOC0 TGIEA TGFA Module Name TPU All Interrupt controller Data Bus Width 16 8 Bus controller 8 ROM I/O port 8 TPU0 16 837 Address H'FF18 H'FF19 H'FF1A H'FF1B H'FF1C H'FF1D H'FF1E H'FF1F H'FF20 H'FF21 H'FF22 H'FF24 H'FF25 H'FF26 H'FF27 H'FF28 H'FF29 H'FF2A H'FF2B H'FF30 H'FF31 H'FF32 H'FF34 H'FF35 H'FF36 H'FF37 H'FF38 H'FF39 H'FF3A H'FF3B H'FF74 (Write) H'FF75 (Read) H'FF76 (Write) H'FF77 (Read) Register Name TGR0A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name TPU0 Data Bus Width 16 TGR0B TGR0C TGR0D TCR1 TMDR1 TIOR1 TIER1 TSR1 TCNT1 -- -- IOB3 TTGE TCFD CCLR1 -- IOB2 -- -- CCLR0 -- IOB1 TCIEU TCFU CKEG1 -- IOB0 TCIEV TCFV CKEG0 MD3 IOA3 -- -- TPSC2 MD2 IOA2 -- -- TPSC1 MD1 IOA1 TGIEB TGFB TPSC0 MD0 IOA0 TGIEA TGFA TPU1 16 TGR1A TGR1B TCR2 TMDR2 TIOR2 TIER2 TSR2 TCNT2 -- -- IOB3 TTGE TCFD CCLR1 -- IOB2 -- -- CCLR0 -- IOB1 TCIEU TCFU CKEG1 -- IOB0 TCIEV TCFV CKEG0 MD3 IOA3 -- -- TPSC2 MD2 IOA2 -- -- TPSC1 MD1 IOA1 TGIEB TGFB TPSC0 MD0 IOA0 TGIEA TGFA TPU2 16 TGR2A TGR2B TCSR0 TCNT0 TCNT0 OVF WT/IT TME -- -- CKS2 CKS1 CKS0 WDT0 16 RSTCSR WOVF RSTE RSTS -- -- -- -- -- RSTCSR WOVF RSTE RSTS -- -- -- -- -- 838 Address H'FF78 Register Name SMR0 Bit 7 C/A GM Bit 6 CHR BLK Bit 5 PE PE Bit 4 O/E O/E Bit 3 STOP BCP1 Bit 2 MP BCP0 Bit 1 CKS1 CKS1 Bit 0 CKS0 CKS0 Module Name SCI0 Smart card interface 0 SCI0, smart card Data Bus Width 8 H'FF79 BRR0 H'FF7A H'FF7B H'FF7C SCR0 TDR0 SSR0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 interface 0 TDRE TDRE RDRF RDRF ORER ORER FER ERS PER PER TEND TEND MPB MPB MPBT MPBT SCI0 Smart card interface 0 SCI0, smart card H'FF7D RDR0 H'FF7E H'FF80 SCMR0 SMR1 -- C/A GM -- CHR BLK -- PE PE -- O/E O/E SDIR STOP BCP1 SINV MP BCP0 -- CKS1 CKS1 SMIF CKS0 CKS0 interface 0 SCI1 Smart card interface 1 SCI1, smart card 8 H'FF81 BRR1 H'FF82 H'FF83 H'FF84 SCR1 TDR1 SSR1 SSR1 TIE RIE TE RE MPIE TEIE CKE1 CKE0 interface 1 TDRE TDRE RDRF RDRF ORER ORER FER ERS PER PER TEND TEND MPB MPB MPBT MPBT SCI1 Smart card interface 1 SCI1, smart card H'FF85 RDR1 H'FF86 H'FF88 SCMR1 SMR2 -- C/A GM -- CHR BLK -- PE PE -- O/E O/E SDIR STOP BCP1 SINV MP BCP0 -- CKS1 CKS1 SMIF CKS0 CKS0 interface 1 SCI2 Smart card interface 2 SCI2, smart card 8 H'FF89 BRR2 H'FF8A H'FF8B H'FF8C SCR2 TDR2 SSR2 SSR2 TIE RIE TE RE MPIE TEIE CKE1 CKE0 interface 2 TDRE TDRE RDRF RDRF ORER ORER FER ERS PER PER TEND TEND MPB MPB MPBT MPBT SCI2 Smart card interface 2 SCI2, smart card H'FF8D RDR2 H'FF8E SCMR2 -- -- -- -- SDIR SINV -- SMIF interface 2 839 Address H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF95 H'FF96 H'FF97 H'FF98 H'FF99 H'FFA2 (Write) H'FFA3 (Read) H'FFA8 H'FFA9 H'FFAA H'FFAB H'FFAC H'FFB0 H'FFB3 H'FFB8 H'FFB9 H'FFBA H'FFBB H'FFBC H'FFBD H'FFBE Register Name ADDRA Bit 7 AD9 AD1 Bit 6 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE TRGS0 WT/IT Bit 5 AD7 -- AD7 -- AD7 -- AD7 -- ADST -- TME Bit 4 AD6 -- AD6 -- AD6 -- AD6 -- SCAN -- PSS Bit 3 AD5 -- AD5 -- AD5 -- AD5 -- CH3 CKS1 RST/NMI Bit 2 AD4 -- AD4 -- AD4 -- AD4 -- CH2 CKS0 CKS2 Bit 1 AD3 -- AD3 -- AD3 -- AD3 -- CH1 -- CKS1 Bit 0 AD2 -- AD2 -- AD2 -- AD2 -- CH0 -- CKS0 Module Name A/D converter Data Bus Width 16 ADDRB AD9 AD1 ADDRC AD9 AD1 ADDRD AD9 AD1 ADCSR ADCR TCSR1*6 TCNT1* 6 ADF TRGS1 OVF WDT1 16 TCNT1*6 FLMCR1*3 FWE FLMCR2* EBR1*3 EBR2* 3 3 SWE1 -- EB6 -- -- P16 P46 P96 -- PB6 PC6 PD6 PE6 PF6 ESU1 -- EB5 -- -- P15 P45 P95 PA5 PB5 PC5 PD5 PE5 PF5 PSU1 -- EB4 -- -- P14 P44 P94 PA4 PB4 PC4 PD4 PE4 PF4 EV1 -- EB3 EB11 -- P13 P43 P93 PA3 PB3 PC3 PD3 PE3 PF3 PV1 -- EB2 EB10 -- P12 P42 P92 PA2 PB2 PC2 PD2 PE2 PF2 E1 -- EB1 EB9 -- P11 P41 P91 PA1 PB1 PC1 PD1 PE1 PF1 P1 -- EB0 EB8 -- P10 P40 P90 PA0 PB0 PC0 PD0 PE0 PF0 ROM 8 FLER EB7 -- PDWND P17 P47 P97 -- PB7 PC7 PD7 PE7 PF7 FLPWCR PORT1 PORT4 PORT9 PORTA PORTB PORTC PORTD PORTE PORTF I/O port 8 Notes: *1 Located in on-chip RAM. The bus width is 32 bits when the DTC accesses this area as register information, and 16 bits otherwise. *2 The address depends on the output trigger setting. *3 These registers are present in the F-ZTAT version, but not in the mask ROM version. An undefined value will be returned if these registers are read in the mask ROM version. *4 Valid only in the H8S/2626 Series; reserved bits in the H8S/2623 Series. For the handling of these bits in register writes, see the individual register descriptions the respective sections. *5 Valid only in the H8S/2623 Series; reserved bits in the H8S/2626 Series. For the handling of these bits in register writes, see the individual register descriptions the respective sections. *6 These registers are not available, and must not be accessed, in the H8S/2623 Series. 840 B.2 Functions Register name Address to which the register is mapped Name of on-chip supporting module Register acronym SBYCR--Standby Control Register H'FDE4 Power-Down Modes Bit numbers Bit : 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 OPE 1 R/W 2 -- 0 -- 1 -- 0 -- 0 -- 0 R/W Initial bit values Initial value : Read/Write : Names of the bits. Dashes (--) indicate reserved bits. Output port enable Possible types of access R W Read only Write only 0 In software standby mode, address bus and bus control signals are high-impedance 1 In software standby mode, address bus and bus control signals retain their output state Standby timer select 0 0 1 1 0 1 0 Standby time = 8192 states 1 Standby time = 16384 states 0 Standby time = 32768 states 1 Standby time = 65536 states 0 Standby time = 131072 states 1 Standby time = 262144 states 0 Reserved 1 Standby time = 16 states Software standby 0 Transition to sleep mode after execution of SLEEP instruction 1 Transition to software standby mode after execution of SLEEP instruction Full name of bit R/W Read and write Descriptions of bit settings 841 MRA--DTC Mode Register A Bit : 7 SM1 Initial value : Read/Write : -- 6 SM0 -- 5 DM1 -- 4 DM0 -- H'EBC0-H'EFBF 3 MD1 -- 2 MD0 -- 1 DTS -- 0 DTC Sz -- Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined DTC data transfer size 0 Byte-size transfer 1 Word-size transfer DTC transfer mode select 0 Destination side is repeat area or block area 1 Source side is repeat area or block area DTC mode 0 1 0 Normal mode 1 Repeat mode 0 Block transfer mode 1-- Destination address mode 0 -- DAR is fixed 1 0 DAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) 1 DAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) Source address mode 0 -- SAR is fixed 1 0 SAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) 1 SAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) 842 MRB--DTC Mode Register B Bit : 7 CHNE Initial value : Read/Write : -- 6 DISEL -- 5 -- -- 4 -- -- H'EBC0-H'EFBF 3 -- -- 2 -- -- 1 -- -- 0 DTC -- -- Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined DTC interrupt select 0 After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is 0 1 After a data transfer ends, the CPU interrupt is enabled DTC chain transfer enable 0 End of DTC data transfer 1 DTC chain transfer SAR--DTC Source Address Register Bit : 23 22 21 20 19 Initial value : Read/Write : Unde- Unde- Unde- Unde- Undefined fined fined fined fined H'EBC0-H'EFBF ------4 3 2 1 DTC 0 Unde- Unde- Unde- Unde- Undefined fined fined fined fined -- -- -- -- -- -- -- -- -- -- Specifies DTC transfer data source address DAR--DTC Destination Address Register Bit : 23 22 21 20 19 Initial value : Read/Write : Unde- Unde- Unde- Unde- Undefined fined fined fined fined H'EBC0-H'EFBF ------4 3 2 1 DTC 0 Unde- Unde- Unde- Unde- Undefined fined fined fined fined -- -- -- -- -- -- -- -- -- -- Specifies DTC transfer data destination address 843 CRA--DTC Transfer Count Register A Bit : 15 14 13 12 11 10 9 8 H'EBC0-H'EFBF 7 6 5 4 3 2 1 DTC 0 Initial value : Read/Write : Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CRAH CRAL Specifies the number of DTC data transfers CRB--DTC Transfer Count Register B Bit : 15 14 13 12 11 10 9 8 H'EBC0-H'EFBF 7 6 5 4 3 2 1 DTC 0 Initial value : Read/Write : Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Specifies the number of DTC block data transfers 844 MCR--Master Control Register MCR Bit : 7 MCR7 Initial value : Read/Write : 0 R/W 6 -- 0 R 5 MCR5 0 R/W 4 -- 0 R H'F800 HCAN 3 -- 0 R 2 MCR2 0 R/W 1 MCR1 0 R/W 0 MCR0 1 R/W Reset request 0 Normal operating mode (MCR0 = 0 and GSR3 = 0) [Setting condition] When 0 is written after an HCAN reset 1 HCAN reset mode transition request Halt request 0 HCAN normal operating mode 1 HCAN halt mode transition request Message transmission method 0 Transmission order determined by message identifier priority 1 Transmission order determined by mailbox (buffer) number priority (TXPR1 > TXPR15) HCAN sleep mode 0 HCAN sleep mode released 1 Transition to HCAN sleep mode enabled HCAN sleep mode release 0 HCAN sleep mode release by CAN bus operation disabled 1 HCAN sleep mode release by CAN bus operation enabled 845 GSR--General Status Register GSR Bit : 7 -- Initial value : Read/Write : 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R H'F801 HCAN 3 GSR3 1 R 2 GSR2 1 R 1 GSR1 0 R 0 GSR0 0 R Bus off flag 0 [Reset condition] Recovery from bus off state 1 When TEC 256 (bus off state) Transmit/receive warning flag 0 [Reset condition] When TEC < 96 and REC < 96 or TEC 256 1 When TEC 96 or REC 96 Message transmission status flag 0 Message transmission period 1 [Reset condition] Idle period Reset status bit 0 Normal operating state [Setting condition] After an HCAN internal reset 1 Configuration mode [Reset condition] MCR0 reset mode and sleep mode 846 BCR--Bit Configuration Register BCR Bit : 15 BCR7 Initial value : Read/Write : 0 R/W 14 BCR6 0 R/W 13 BCR5 0 R/W 12 BCR4 0 R/W H'F802 HCAN 11 BCR3 0 R/W 10 BCR2 0 R/W 9 BCR1 0 R/W 8 BCR0 0 R/W Baud rate prescale 0 0 0 : 1 Resynchronization jump width 0 1 0 Max. bit synchronization width = 1 time quantum 1 Max. bit synchronization width = 2 time quanta 0 Max. bit synchronization width = 3 time quanta 1 Max. bit synchronization width = 4 time quanta 0 0 0 : 1 0 0 0 : 1 0 0 0 : 1 0 0 1 : 1 0 1 0 : 1 2 x system clock 4 x system clock 6 x system clock : 128 x system clock 847 BCR Bit : 7 BCR15 Initial value : Read/Write : 0 R/W 6 BCR14 0 R/W 5 BCR13 0 R/W 4 BCR12 0 R/W 3 BCR11 0 R/W 2 BCR10 0 R/W 1 BCR9 0 R/W 0 BCR8 0 R/W Time segment 1 0 0 0 0 0 : 1 Time segment 2 0 0 1 1 0 1 0 Setting prohibited 1 TSEG2 = 2 time quanta 0 TSEG2 = 3 time quanta 1 TSEG2 = 4 time quanta 0 TSEG2 = 5 time quanta 1 TSEG2 = 6 time quanta 0 TSEG2 = 7 time quanta 1 TSEG2 = 8 time quanta Bit sample point 0 Bit sampling at one point (end of time segment 1 (TSEG1)) 1 Bit sampling at three points (end of time segment 1 (TSEG1), and 1 time quantum before and after) Note: For details, see section 15.2.3, Bit Configuration Register (BCR). 0 0 0 0 1 : 1 0 0 1 1 0 : 1 0 Setting prohibited 1 Setting prohibited 0 Setting prohibited 1 TSEG1 = 4 time quanta 0 TSEG1 = 5 time quanta : : 1 TSEG1 = 16 time quanta 848 MBCR--Mailbox Configuration Register MBCR Bit : 15 MBCR7 Initial value : Read/Write : Bit : 0 R/W 7 0 R/W 14 MBCR6 0 R/W 6 0 R/W 13 MBCR5 0 R/W 5 0 R/W 12 H'F804 HCAN 11 MBCR3 0 R/W 3 0 R/W 10 MBCR2 0 R/W 2 0 R/W 9 MBCR1 0 R/W 1 0 R/W 8 -- 1 R 0 MBCR8 0 R/W MBCR4 0 R/W 4 0 R/W MBCR15 MBCR14 MBCR13 MBCR12 MBCR11 MBCR10 MBCR9 Initial value : Read/Write : Mailbox setting register 0 Corresponding mailbox is set for transmission 1 Corresponding mailbox is set for reception TXPR--Transmit Wait Register TXPR Bit : 15 TXPR7 Initial value : Read/Write : Bit : 0 R/W 7 0 R/W 14 TXPR6 0 R/W 6 0 R/W 13 TXPR5 0 R/W 5 0 R/W 12 H'F806 HCAN 11 TXPR3 0 R/W 3 0 R/W 10 TXPR2 0 R/W 2 0 R/W 9 TXPR1 0 R/W 1 TXPR9 0 R/W 8 -- 0 R 0 TXPR8 0 R/W TXPR4 0 R/W 4 0 R/W TXPR15 TXPR14 TXPR13 TXPR12 TXPR11 TXPR10 Initial value : Read/Write : Transmit wait register 0 Transmit message idle state in corresponding mailbox [Clearing condition] Message transmission completion and cancellation completion 1 Transmit wait for transmit message in corresponding mailbox (CAN bus arbitration) 849 TXCR--Transmit Wait Cancel Register TXCR Bit : 15 TXCR7 Initial value : Read/Write : Bit : 0 R/W 7 0 R/W 14 TXCR6 0 R/W 6 0 R/W 13 TXCR5 0 R/W 5 0 R/W 12 H'F808 HCAN 11 TXCR3 0 R/W 3 0 R/W 10 TXCR2 0 R/W 2 0 R/W 9 TXCR1 0 R/W 1 0 R/W 8 -- 0 R 0 TXCR8 0 R/W TXCR4 0 R/W 4 0 R/W TXCR15 TXCR14 TXCR13 TXCR12 TXCR11 TXCR10 TXCR9 Initial value : Read/Write : Transmit wait cancel register 0 Transmit message cancellation idle state in corresponding mailbox [Clearing condition] Completion of TXPR clearing (when transmit message is canceled normally) 1 TXPR cleared for corresponding mailbox (transmit message cancellation) 850 TXACK--Transmit Acknowledge Register TXACK Bit : 15 0 R/(W)* 7 0 R/(W)* 14 0 R/(W)* 6 0 R/(W)* 13 0 R/(W)* 5 0 R/(W)* 12 0 H'F80A HCAN 11 0 R/(W)* 3 0 R/(W)* 10 0 R/(W)* 2 0 R/(W)* 9 0 R/(W)* 1 0 R/(W)* 8 -- 0 R 0 0 R/(W)* TXACK7 TXACK6 TXACK5 TXACK4 TXACK3 TXACK2 TXACK1 Initial value : Read/Write : Bit : R/(W)* 4 0 R/(W)* TXACK15 TXACK14 TXACK13 TXACK12 TXACK11 TXACK10 TXACK9 TXACK8 Initial value : Read/Write : Transmit acknowledge register 0 [Clearing condition] Writing 1 1 Completion of message transmission for corresponding mailbox Note: * Can only be written with 1 for flag clearing. ABACK--Abort Acknowledge Register ABACK Bit : 15 0 R/(W)* 7 0 R/(W)* 14 0 R/(W)* 6 0 R/(W)* 13 0 R/(W)* 5 0 R/(W)* 12 0 H'F80C HCAN 11 0 R/(W)* 3 0 R/(W)* 10 0 R/(W)* 2 0 R/(W)* 9 0 R/(W)* 1 0 R/(W)* 8 -- 0 R 0 0 R/(W)* ABACK7 ABACK6 ABACK5 ABACK4 ABACK3 ABACK2 ABACK1 Initial value : Read/Write : Bit : R/(W)* 4 0 R/(W)* ABACK15 ABACK14 ABACK13 ABACK12 ABACK11 ABACK10 ABACK9 ABACK8 Initial value : Read/Write : Abort acknowledge register 0 [Clearing condition] Writing 1 1 Completion of transmit message cancellation for corresponding mailbox Note: * Can only be written with 1 for flag clearing. 851 RXPR--Receive Complete Register RXPR Bit : 15 RXPR7 Initial value : Read/Write : Bit : 0 R/(W)* 7 0 R/(W)* 14 RXPR6 0 R/(W)* 6 0 R/(W)* 13 RXPR5 0 R/(W)* 5 0 R/(W)* 12 H'F80E HCAN 11 RXPR3 0 R/(W)* 3 0 R/(W)* 10 RXPR2 0 R/(W)* 2 0 R/(W)* 9 RXPR1 0 R/(W)* 1 0 R/(W)* 8 RXPR0 0 R/(W)* 0 RXPR8 0 R/(W)* RXPR4 0 R/(W)* 4 0 R/(W)* RXPR15 RXPR14 RXPR13 RXPR12 RXPR11 RXPR10 RXPR9 Initial value : Read/Write : Receive complete register 0 [Clearing condition] Writing 1 1 Completion of message (data frame or remote frame) reception in corresponding mailbox Note: * Can only be written with 1 for flag clearing. RFPR--Remote Request Register RFPR Bit : 15 RFPR7 Initial value : Read/Write : Bit : 0 R/(W)* 7 0 R/(W)* 14 RFPR6 0 R/(W)* 6 0 R/(W)* 13 RFPR5 0 R/(W)* 5 0 R/(W)* 12 H'F810 HCAN 11 RFPR3 0 R/(W)* 3 0 R/(W)* 10 RFPR2 0 R/(W)* 2 0 R/(W)* 9 RFPR1 0 R/(W)* 1 0 R/(W)* 8 RFPR0 0 R/(W)* 0 RFPR8 0 R/(W)* RFPR4 0 R/(W)* 4 0 R/(W)* RFPR15 RFPR14 RFPR13 RFPR12 RFPR11 RFPR10 RFPR9 Initial value : Read/Write : Remote request wait register 0 [Clearing condition] Writing 1 1 Completion of remote frame reception in corresponding mailbox Note: * Can only be written with 1 for flag clearing. 852 IRR--Interrupt Register IRR Bit : 15 IRR7 Initial value : Read/Write : 0 R/(W)* 14 IRR6 0 R/(W)* 13 IRR5 0 R/(W)* 12 IRR4 0 H'F812 HCAN 11 IRR3 0 R/(W)* 10 IRR2 0 R 9 IRR1 0 R 8 IRR0 0 R/(W)* R/(W)* Reset interrupt flag 0 [Clearing condition] Writing 1 1 Hardware reset (HCAN module stop, software standby) [Setting condition] When reset processing is completed after a hardware reset (HCAN module stop, software standby) Receive message interrupt flag 0 [Clearing condition] Clearing of all bits in RXPR (receive complete register) of mailbox for which receive interrupt requests are enabled MBIMR 1 Data frame or remote frame received and stored in mailbox [Setting conditions] When data frame or remote frame reception is completed When corresponding MBIMR = 0 Bus off interrupt flag 0 [Clearing condition] Writing 1 1 Bus off state caused by transmit error [Setting condition] When TEC 256 Remote frame request interrupt flag 0 [Clearing condition] Clearing of all bits in RFPR (remote request wait register) of mailbox for which receive interrupt requests are enabled MBIMR 1 Remote frame received and stored in mailbox [Setting conditions] When remote frame reception is completed When corresponding MBIMR = 0 Transmit overload warning interrupt flag 0 [Clearing condition] Writing 1 1 Error warning state caused by transmit error [Setting condition] When TEC 96 Overload frame/bus off recovery interrupt flag 0 [Clearing condition] Writing 1 1 Overload frame transmission or recovery from bus off state [Setting conditions] * Error active/passive state -- When overload frame is transmitted * Bus off state -- When 11 recessive bits are received 128 times (REC 128) Receive overload warning interrupt flag 0 [Clearing condition] Writing 1 1 Error warning state caused by receive error [Setting condition] When REC 96 Error passive interrupt flag 0 [Clearing condition] Writing 1 1 Error passive state caused by transmit/receive error [Setting condition] When TEC 128 or REC 128 Note: * Can only be written with 1 for flag clearing. 853 IRR Bit : 7 -- Initial value : Read/Write : 0 -- 6 -- 0 -- 5 -- 0 -- 4 IRR12 0 R/(W)* 3 -- 0 -- 2 -- 0 -- 1 IRR9 0 R 0 IRR8 0 R/(W)* Mailbox empty interrupt flag 0 [Clearing condition] Writing 1 1 Transmit message has been transmitted or aborted, and new message can be stored [Setting condition] When TXPR (transmit wait register) is cleared by completion of transmission or completion of transmission abort Unread interrupt flag 0 [Clearing condition] Clearing of all bits in UMSR (unread message status register) 1 Unread message overwrite [Setting condition] When UMSR (unread message status register) is set Bus operation interrupt flag 0 CAN bus idle state [Clearing condition] Writing 1 CAN bus operation in HCAN sleep mode [Setting condition] Bus operation (dominant bit detection) in HCAN sleep mode 1 Note: * Can only be written with 1 for flag clearing. 854 MBIMR--Mailbox Interrupt Mask Register MBIMR Bit : 15 1 R/W 7 1 R/W 14 1 R/W 6 1 R/W 13 1 R/W 5 1 R/W 12 1 R/W 4 1 R/W H'F814 HCAN 11 1 R/W 3 1 R/W 10 1 R/W 2 1 R/W 9 1 R/W 1 1 R/W 8 1 R/W 0 1 R/W MBIMR7 MBIMR6 MBIMR5 MBIMR4 MBIMR3 MBIMR2 MBIMR1 MBIMR0 Initial value : Read/Write : Bit : MBIMR15 MBIMR14 MBIMR13 MBIMR12 MBIMR11 MBIMR10 MBIMR9 MBIMR8 Initial value : Read/Write : Mailbox interrupt mask 0 [Transmitting] Interrupt request to CPU due to TXPR clearing [Receiving] Interrupt request to CPU due to RXPR setting 1 Interrupt requests to CPU disabled 855 IMR--Interrupt Mask Register IMR Bit : 15 IMR7 Initial value : Read/Write : 1 R/W 14 IMR6 1 R/W 13 IMR5 1 R/W 12 IMR4 1 R/W H'F816 HCAN 11 IMR3 1 R/W 10 IMR2 1 R/W 9 IMR1 1 R/W 8 -- 0 R Receive message interrupt mask 0 Message reception interrupt request (RM1) to CPU by IRR1 enabled 1 Message reception interrupt request (RM1) to CPU by IRR1 disabled Remote frame request interrupt mask 0 Remote frame reception interrupt request (OVR0) to CPU by IRR2 enabled 1 Remote frame reception interrupt request (OVR0) to CPU by IRR2 disabled Transmit overload warning interrupt mask 0 TEC error warning interrupt request (OVR0) to CPU by IRR3 enabled 1 TEC error warning interrupt request (OVR0) to CPU by IRR3 disabled Receive overload warning interrupt mask 0 REC error warning interrupt request (OVR0) to CPU by IRR4 enabled 1 REC error warning interrupt request (OVR0) to CPU by IRR4 disabled Error passive interrupt mask 0 Error passive interrupt request to (ERS0) CPU by IRR5 enabled 1 Error passive interrupt request to (ERS0) CPU by IRR5 disabled Bus off interrupt mask 0 Bus off interrupt request (ERS0) to CPU by IRR6 enabled 1 Bus off interrupt request (ERS0) to CPU by IRR6 disabled Overload frame/bus off recovery interrupt mask 0 Overload frame/bus off recovery interrupt request (OVR0) to CPU by IRR7 enabled 1 Overload frame/bus off recovery interrupt request (OVR0) to CPU by IRR7 disabled 856 IMR Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 -- 1 -- 4 IMR12 1 R/W 3 -- 1 -- 2 -- 1 -- 1 IMR9 1 R/W 0 IMR8 1 R/W Mailbox empty interrupt mask 0 Mailbox empty interrupt request (SLE0) to CPU by IRR8 enabled 1 Mailbox empty interrupt request (SLE0) to CPU by IRR8 disabled Unread interrupt mask 0 Unread message overwrite interrupt request (OVR0) to CPU by IRR9 enabled 1 Unread message overwrite interrupt request (OVR0) to CPU by IRR9 disabled Bus operation interrupt mask 0 Bus operation interrupt request (OVR0) to CPU by IRR12 enabled 1 Bus operation interrupt request (OVR0) to CPU by IRR12 disabled 857 REC--Receive Error Counter REC Bit : 7 0 R 6 0 R 5 0 R 4 0 R H'F818 HCAN 3 0 R 2 0 R 1 0 R 0 0 R Initial value : Read/Write : TEC--Transmit Error Counter TEC Bit : 7 0 R 6 0 R 5 0 R 4 0 R H'F819 HCAN 3 0 R 2 0 R 1 0 R 0 0 R Initial value : Read/Write : UMSR--Unread Message Status Register UMSR Bit : 15 UMSR7 Initial value : Read/Write : Bit : 0 R/(W)* 7 0 R/(W)* 14 UMSR6 0 R/(W)* 6 0 R/(W)* 13 UMSR5 0 R/(W)* 5 0 R/(W)* 12 H'F81A HCAN 11 UMSR3 0 R/(W)* 3 0 R/(W)* 10 UMSR2 0 R/(W)* 2 0 R/(W)* 9 UMSR1 0 R/(W)* 1 0 R/(W)* 8 UMSR0 0 R/(W)* 0 UMSR8 0 R/(W)* UMSR4 0 R/(W)* 4 0 R/(W)* UMSR15 UMSR14 UMSR13 UMSR12 UMSR11 UMSR10 UMSR9 Initial value : Read/Write : Unread message status flags 0 [Clearing condition] Writing 1 1 Unread receive message is overwritten by a new message [Setting condition] When a new message is received before RXPR is cleared Note: * Can only be written with 1 for flag clearing. 858 LAFML--Local Acceptance Filter Mask LAFMH--Local Acceptance Filter Mask LAFML Bit : 15 LAFML7 Initial value : Read/Write : Bit : 0 R/W 7 0 R/W 14 LAFML6 0 R/W 6 0 R/W 13 LAFML5 0 R/W 5 0 R/W 12 H'F81C H'F81E HCAN HCAN 11 LAFML3 0 R/W 3 0 R/W 10 LAFML2 0 R/W 2 0 R/W 9 LAFML1 0 R/W 1 0 R/W 8 LAFML0 0 R/W 0 LAFML8 0 R/W LAFML4 0 R/W 4 0 R/W LAFML15 LAFML14 LAFML13 LAFML12 LAFML11 LAFML10 LAFML9 Initial value : Read/Write : LAFMH Bit : 15 0 R/W 7 0 R/W 14 0 R/W 6 0 R/W 13 0 R/W 5 0 R/W 12 -- 0 R 4 0 R/W 11 -- 0 R 3 0 R/W 10 -- 0 R 2 0 R/W 9 0 R/W 1 0 R/W 8 0 R/W 0 0 R/W LAFMH7 LAFMH6 LAFMH5 Initial value : Read/Write : Bit : LAFMH1 LAFMH0 LAFMH15 LAFMH14 LAFMH13 LAFMH12 LAFMH11 LAFMH10 LAFMH9 LAFMH8 Initial value : Read/Write : LAFMH Bits 7 to 0 and 15 to 13--11-bit identifier filter 0 Stored in MC0, MD0 (receive-only mailbox) depending on bit match between MC0 message identifier and receive message identifier (Care) 1 Stored in MC0, MD0 (receive-only mailbox) regardless of bit match between MC0 message identifier and receive message identifier (Don't Care) LAFMH bits 9 and 8, LAFML Bits 15 to 0--18-bit identifier filter 0 Stored in MC0 (receive-only mailbox) depending on bit match between MC0 message identifier and receive message identifier (Care) 1 Stored in MC0 (receive-only mailbox) regardless of bit match between MC0 message identifier and receive message identifier (Don't Care) 859 MC0--Message Control MCx[1] Bit : Initial value : Read/Write : 7 -- Undefined R/W 6 -- Undefined R/W 5 -- Undefined R/W 4 -- Undefined R/W H'F820 3 DLC3 Undefined R/W 2 DLC2 Undefined R/W 1 DLC1 Undefined R/W 0 DLC0 Undefined R/W HCAN Data length code 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0/1 0/1 0/1 MCx[2] Bit : Initial value : Read/Write : MCx[3] Bit : Initial value : Read/Write : MCx[4] Bit : Initial value : Read/Write : MCx[5] Bit : Initial value : Read/Write : 7 -- Undefined R/W 7 -- Undefined R/W 7 -- Undefined R/W 7 STD_ID2 Undefined R/W 6 -- Undefined R/W 6 -- Undefined R/W 6 -- Undefined R/W 6 STD_ID1 Undefined R/W 5 -- Undefined R/W 5 -- Undefined R/W 5 -- Undefined R/W 5 STD_ID0 Undefined R/W 4 -- Undefined R/W 4 -- Undefined R/W 4 -- Undefined R/W 4 RTR Undefined R/W 3 -- Undefined R/W 3 -- Undefined R/W 3 -- Undefined R/W 3 IDE Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes Data length = 8 bytes 1 -- Undefined R/W 1 -- Undefined R/W 1 -- Undefined R/W 1 EXD_ID17 Undefined R/W 0 -- Undefined R/W 0 -- Undefined R/W 0 -- Undefined R/W 0 EXD_ID16 Undefined R/W Identifier extension 0 Standard format 1 Extended format Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[6] Bit : Initial value : Read/Write : 7 STD_ID10 Undefined R/W 6 STD_ID9 Undefined R/W Remote transmission request 0 Data frame 1 Remote frame 4 STD_ID7 Undefined R/W 3 STD_ID6 Undefined R/W 2 STD_ID5 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames 5 STD_ID8 Undefined R/W 1 STD_ID4 Undefined R/W 0 STD_ID3 Undefined R/W Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[7] Bit : Initial value : Read/Write : MCx[8] Bit : Initial value : Read/Write : 7 EXD_ID7 Undefined R/W 7 EXD_ID15 Undefined R/W 6 EXD_ID6 Undefined R/W 6 EXD_ID14 Undefined R/W 5 EXD_ID5 Undefined R/W 5 EXD_ID13 Undefined R/W 4 EXD_ID4 Undefined R/W 4 EXD_ID12 Undefined R/W 3 EXD_ID3 Undefined R/W 3 EXD_ID11 Undefined R/W 2 EXD_ID2 Undefined R/W 2 EXD_ID10 Undefined R/W 1 EXD_ID1 Undefined R/W 1 EXD_ID9 Undefined R/W 0 EXD_ID0 Undefined R/W 0 EXD_ID8 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames x=0 860 MC1--Message Control MCx[1] Bit : Initial value : Read/Write : 7 -- Undefined R/W 6 -- Undefined R/W 5 -- Undefined R/W 4 -- Undefined R/W H'F828 3 DLC3 Undefined R/W 2 DLC2 Undefined R/W 1 DLC1 Undefined R/W 0 DLC0 Undefined R/W HCAN Data length code 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0/1 0/1 0/1 MCx[2] Bit : Initial value : Read/Write : MCx[3] Bit : Initial value : Read/Write : MCx[4] Bit : Initial value : Read/Write : MCx[5] Bit : Initial value : Read/Write : 7 -- Undefined R/W 7 -- Undefined R/W 7 -- Undefined R/W 7 STD_ID2 Undefined R/W 6 -- Undefined R/W 6 -- Undefined R/W 6 -- Undefined R/W 6 STD_ID1 Undefined R/W 5 -- Undefined R/W 5 -- Undefined R/W 5 -- Undefined R/W 5 STD_ID0 Undefined R/W 4 -- Undefined R/W 4 -- Undefined R/W 4 -- Undefined R/W 4 RTR Undefined R/W 3 -- Undefined R/W 3 -- Undefined R/W 3 -- Undefined R/W 3 IDE Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes Data length = 8 bytes 1 -- Undefined R/W 1 -- Undefined R/W 1 -- Undefined R/W 1 EXD_ID17 Undefined R/W 0 -- Undefined R/W 0 -- Undefined R/W 0 -- Undefined R/W 0 EXD_ID16 Undefined R/W Identifier extension 0 Standard format 1 Extended format Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[6] Bit : Initial value : Read/Write : 7 STD_ID10 Undefined R/W 6 STD_ID9 Undefined R/W Remote transmission request 0 Data frame 1 Remote frame 4 STD_ID7 Undefined R/W 3 STD_ID6 Undefined R/W 2 STD_ID5 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames 5 STD_ID8 Undefined R/W 1 STD_ID4 Undefined R/W 0 STD_ID3 Undefined R/W Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[7] Bit : Initial value : Read/Write : MCx[8] Bit : Initial value : Read/Write : 7 EXD_ID7 Undefined R/W 7 EXD_ID15 Undefined R/W 6 EXD_ID6 Undefined R/W 6 EXD_ID14 Undefined R/W 5 EXD_ID5 Undefined R/W 5 EXD_ID13 Undefined R/W 4 EXD_ID4 Undefined R/W 4 EXD_ID12 Undefined R/W 3 EXD_ID3 Undefined R/W 3 EXD_ID11 Undefined R/W 2 EXD_ID2 Undefined R/W 2 EXD_ID10 Undefined R/W 1 EXD_ID1 Undefined R/W 1 EXD_ID9 Undefined R/W 0 EXD_ID0 Undefined R/W 0 EXD_ID8 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames x=1 861 MC2--Message Control MCx[1] Bit : Initial value : Read/Write : 7 -- Undefined R/W 6 -- Undefined R/W 5 -- Undefined R/W 4 -- Undefined R/W H'F830 3 DLC3 Undefined R/W 2 DLC2 Undefined R/W 1 DLC1 Undefined R/W 0 DLC0 Undefined R/W HCAN Data length code 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0/1 0/1 0/1 MCx[2] Bit : Initial value : Read/Write : MCx[3] Bit : Initial value : Read/Write : MCx[4] Bit : Initial value : Read/Write : MCx[5] Bit : Initial value : Read/Write : 7 -- Undefined R/W 7 -- Undefined R/W 7 -- Undefined R/W 7 STD_ID2 Undefined R/W 6 -- Undefined R/W 6 -- Undefined R/W 6 -- Undefined R/W 6 STD_ID1 Undefined R/W 5 -- Undefined R/W 5 -- Undefined R/W 5 -- Undefined R/W 5 STD_ID0 Undefined R/W 4 -- Undefined R/W 4 -- Undefined R/W 4 -- Undefined R/W 4 RTR Undefined R/W 3 -- Undefined R/W 3 -- Undefined R/W 3 -- Undefined R/W 3 IDE Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes Data length = 8 bytes 1 -- Undefined R/W 1 -- Undefined R/W 1 -- Undefined R/W 1 EXD_ID17 Undefined R/W 0 -- Undefined R/W 0 -- Undefined R/W 0 -- Undefined R/W 0 EXD_ID16 Undefined R/W Identifier extension 0 Standard format 1 Extended format Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[6] Bit : Initial value : Read/Write : 7 STD_ID10 Undefined R/W 6 STD_ID9 Undefined R/W Remote transmission request 0 Data frame 1 Remote frame 4 STD_ID7 Undefined R/W 3 STD_ID6 Undefined R/W 2 STD_ID5 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames 5 STD_ID8 Undefined R/W 1 STD_ID4 Undefined R/W 0 STD_ID3 Undefined R/W Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[7] Bit : Initial value : Read/Write : MCx[8] Bit : Initial value : Read/Write : 7 EXD_ID7 Undefined R/W 7 EXD_ID15 Undefined R/W 6 EXD_ID6 Undefined R/W 6 EXD_ID14 Undefined R/W 5 EXD_ID5 Undefined R/W 5 EXD_ID13 Undefined R/W 4 EXD_ID4 Undefined R/W 4 EXD_ID12 Undefined R/W 3 EXD_ID3 Undefined R/W 3 EXD_ID11 Undefined R/W 2 EXD_ID2 Undefined R/W 2 EXD_ID10 Undefined R/W 1 EXD_ID1 Undefined R/W 1 EXD_ID9 Undefined R/W 0 EXD_ID0 Undefined R/W 0 EXD_ID8 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames x=2 862 MC3--Message Control MCx[1] Bit : Initial value : Read/Write : 7 -- Undefined R/W 6 -- Undefined R/W 5 -- Undefined R/W 4 -- Undefined R/W H'F838 3 DLC3 Undefined R/W 2 DLC2 Undefined R/W 1 DLC1 Undefined R/W 0 DLC0 Undefined R/W HCAN Data length code 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0/1 0/1 0/1 MCx[2] Bit : Initial value : Read/Write : MCx[3] Bit : Initial value : Read/Write : MCx[4] Bit : Initial value : Read/Write : MCx[5] Bit : Initial value : Read/Write : 7 -- Undefined R/W 7 -- Undefined R/W 7 -- Undefined R/W 7 STD_ID2 Undefined R/W 6 -- Undefined R/W 6 -- Undefined R/W 6 -- Undefined R/W 6 STD_ID1 Undefined R/W 5 -- Undefined R/W 5 -- Undefined R/W 5 -- Undefined R/W 5 STD_ID0 Undefined R/W 4 -- Undefined R/W 4 -- Undefined R/W 4 -- Undefined R/W 4 RTR Undefined R/W 3 -- Undefined R/W 3 -- Undefined R/W 3 -- Undefined R/W 3 IDE Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes Data length = 8 bytes 1 -- Undefined R/W 1 -- Undefined R/W 1 -- Undefined R/W 1 EXD_ID17 Undefined R/W 0 -- Undefined R/W 0 -- Undefined R/W 0 -- Undefined R/W 0 EXD_ID16 Undefined R/W Identifier extension 0 Standard format 1 Extended format Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[6] Bit : Initial value : Read/Write : 7 STD_ID10 Undefined R/W 6 STD_ID9 Undefined R/W Remote transmission request 0 Data frame 1 Remote frame 4 STD_ID7 Undefined R/W 3 STD_ID6 Undefined R/W 2 STD_ID5 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames 5 STD_ID8 Undefined R/W 1 STD_ID4 Undefined R/W 0 STD_ID3 Undefined R/W Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[7] Bit : Initial value : Read/Write : MCx[8] Bit : Initial value : Read/Write : 7 EXD_ID7 Undefined R/W 7 EXD_ID15 Undefined R/W 6 EXD_ID6 Undefined R/W 6 EXD_ID14 Undefined R/W 5 EXD_ID5 Undefined R/W 5 EXD_ID13 Undefined R/W 4 EXD_ID4 Undefined R/W 4 EXD_ID12 Undefined R/W 3 EXD_ID3 Undefined R/W 3 EXD_ID11 Undefined R/W 2 EXD_ID2 Undefined R/W 2 EXD_ID10 Undefined R/W 1 EXD_ID1 Undefined R/W 1 EXD_ID9 Undefined R/W 0 EXD_ID0 Undefined R/W 0 EXD_ID8 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames x=3 863 MC4--Message Control MCx[1] Bit : Initial value : Read/Write : 7 -- Undefined R/W 6 -- Undefined R/W 5 -- Undefined R/W 4 -- Undefined R/W H'F840 3 DLC3 Undefined R/W 2 DLC2 Undefined R/W 1 DLC1 Undefined R/W 0 DLC0 Undefined R/W HCAN Data length code 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0/1 0/1 0/1 MCx[2] Bit : Initial value : Read/Write : MCx[3] Bit : Initial value : Read/Write : MCx[4] Bit : Initial value : Read/Write : MCx[5] Bit : Initial value : Read/Write : 7 -- Undefined R/W 7 -- Undefined R/W 7 -- Undefined R/W 7 STD_ID2 Undefined R/W 6 -- Undefined R/W 6 -- Undefined R/W 6 -- Undefined R/W 6 STD_ID1 Undefined R/W 5 -- Undefined R/W 5 -- Undefined R/W 5 -- Undefined R/W 5 STD_ID0 Undefined R/W 4 -- Undefined R/W 4 -- Undefined R/W 4 -- Undefined R/W 4 RTR Undefined R/W 3 -- Undefined R/W 3 -- Undefined R/W 3 -- Undefined R/W 3 IDE Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes Data length = 8 bytes 1 -- Undefined R/W 1 -- Undefined R/W 1 -- Undefined R/W 1 EXD_ID17 Undefined R/W 0 -- Undefined R/W 0 -- Undefined R/W 0 -- Undefined R/W 0 EXD_ID16 Undefined R/W Identifier extension 0 Standard format 1 Extended format Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[6] Bit : Initial value : Read/Write : 7 STD_ID10 Undefined R/W 6 STD_ID9 Undefined R/W Remote transmission request 0 Data frame 1 Remote frame 4 STD_ID7 Undefined R/W 3 STD_ID6 Undefined R/W 2 STD_ID5 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames 5 STD_ID8 Undefined R/W 1 STD_ID4 Undefined R/W 0 STD_ID3 Undefined R/W Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[7] Bit : Initial value : Read/Write : MCx[8] Bit : Initial value : Read/Write : 7 EXD_ID7 Undefined R/W 7 EXD_ID15 Undefined R/W 6 EXD_ID6 Undefined R/W 6 EXD_ID14 Undefined R/W 5 EXD_ID5 Undefined R/W 5 EXD_ID13 Undefined R/W 4 EXD_ID4 Undefined R/W 4 EXD_ID12 Undefined R/W 3 EXD_ID3 Undefined R/W 3 EXD_ID11 Undefined R/W 2 EXD_ID2 Undefined R/W 2 EXD_ID10 Undefined R/W 1 EXD_ID1 Undefined R/W 1 EXD_ID9 Undefined R/W 0 EXD_ID0 Undefined R/W 0 EXD_ID8 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames x=4 864 MC5--Message Control MCx[1] Bit : Initial value : Read/Write : 7 -- Undefined R/W 6 -- Undefined R/W 5 -- Undefined R/W 4 -- Undefined R/W H'F848 3 DLC3 Undefined R/W 2 DLC2 Undefined R/W 1 DLC1 Undefined R/W 0 DLC0 Undefined R/W HCAN Data length code 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0/1 0/1 0/1 MCx[2] Bit : Initial value : Read/Write : MCx[3] Bit : Initial value : Read/Write : MCx[4] Bit : Initial value : Read/Write : MCx[5] Bit : Initial value : Read/Write : 7 -- Undefined R/W 7 -- Undefined R/W 7 -- Undefined R/W 7 STD_ID2 Undefined R/W 6 -- Undefined R/W 6 -- Undefined R/W 6 -- Undefined R/W 6 STD_ID1 Undefined R/W 5 -- Undefined R/W 5 -- Undefined R/W 5 -- Undefined R/W 5 STD_ID0 Undefined R/W 4 -- Undefined R/W 4 -- Undefined R/W 4 -- Undefined R/W 4 RTR Undefined R/W 3 -- Undefined R/W 3 -- Undefined R/W 3 -- Undefined R/W 3 IDE Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes Data length = 8 bytes 1 -- Undefined R/W 1 -- Undefined R/W 1 -- Undefined R/W 1 EXD_ID17 Undefined R/W 0 -- Undefined R/W 0 -- Undefined R/W 0 -- Undefined R/W 0 EXD_ID16 Undefined R/W Identifier extension 0 Standard format 1 Extended format Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[6] Bit : Initial value : Read/Write : 7 STD_ID10 Undefined R/W 6 STD_ID9 Undefined R/W Remote transmission request 0 Data frame 1 Remote frame 4 STD_ID7 Undefined R/W 3 STD_ID6 Undefined R/W 2 STD_ID5 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames 5 STD_ID8 Undefined R/W 1 STD_ID4 Undefined R/W 0 STD_ID3 Undefined R/W Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[7] Bit : Initial value : Read/Write : MCx[8] Bit : Initial value : Read/Write : 7 EXD_ID7 Undefined R/W 7 EXD_ID15 Undefined R/W 6 EXD_ID6 Undefined R/W 6 EXD_ID14 Undefined R/W 5 EXD_ID5 Undefined R/W 5 EXD_ID13 Undefined R/W 4 EXD_ID4 Undefined R/W 4 EXD_ID12 Undefined R/W 3 EXD_ID3 Undefined R/W 3 EXD_ID11 Undefined R/W 2 EXD_ID2 Undefined R/W 2 EXD_ID10 Undefined R/W 1 EXD_ID1 Undefined R/W 1 EXD_ID9 Undefined R/W 0 EXD_ID0 Undefined R/W 0 EXD_ID8 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames x=5 865 MC6--Message Control MCx[1] Bit : Initial value : Read/Write : 7 -- Undefined R/W 6 -- Undefined R/W 5 -- Undefined R/W 4 -- Undefined R/W H'F850 3 DLC3 Undefined R/W 2 DLC2 Undefined R/W 1 DLC1 Undefined R/W 0 DLC0 Undefined R/W HCAN Data length code 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0/1 0/1 0/1 MCx[2] Bit : Initial value : Read/Write : MCx[3] Bit : Initial value : Read/Write : MCx[4] Bit : Initial value : Read/Write : MCx[5] Bit : Initial value : Read/Write : 7 -- Undefined R/W 7 -- Undefined R/W 7 -- Undefined R/W 7 STD_ID2 Undefined R/W 6 -- Undefined R/W 6 -- Undefined R/W 6 -- Undefined R/W 6 STD_ID1 Undefined R/W 5 -- Undefined R/W 5 -- Undefined R/W 5 -- Undefined R/W 5 STD_ID0 Undefined R/W 4 -- Undefined R/W 4 -- Undefined R/W 4 -- Undefined R/W 4 RTR Undefined R/W 3 -- Undefined R/W 3 -- Undefined R/W 3 -- Undefined R/W 3 IDE Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes Data length = 8 bytes 1 -- Undefined R/W 1 -- Undefined R/W 1 -- Undefined R/W 1 EXD_ID17 Undefined R/W 0 -- Undefined R/W 0 -- Undefined R/W 0 -- Undefined R/W 0 EXD_ID16 Undefined R/W Identifier extension 0 Standard format 1 Extended format Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[6] Bit : Initial value : Read/Write : 7 STD_ID10 Undefined R/W 6 STD_ID9 Undefined R/W Remote transmission request 0 Data frame 1 Remote frame 4 STD_ID7 Undefined R/W 3 STD_ID6 Undefined R/W 2 STD_ID5 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames 5 STD_ID8 Undefined R/W 1 STD_ID4 Undefined R/W 0 STD_ID3 Undefined R/W Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[7] Bit : Initial value : Read/Write : MCx[8] Bit : Initial value : Read/Write : 7 EXD_ID7 Undefined R/W 7 EXD_ID15 Undefined R/W 6 EXD_ID6 Undefined R/W 6 EXD_ID14 Undefined R/W 5 EXD_ID5 Undefined R/W 5 EXD_ID13 Undefined R/W 4 EXD_ID4 Undefined R/W 4 EXD_ID12 Undefined R/W 3 EXD_ID3 Undefined R/W 3 EXD_ID11 Undefined R/W 2 EXD_ID2 Undefined R/W 2 EXD_ID10 Undefined R/W 1 EXD_ID1 Undefined R/W 1 EXD_ID9 Undefined R/W 0 EXD_ID0 Undefined R/W 0 EXD_ID8 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames x=6 866 MC7--Message Control MCx[1] Bit : Initial value : Read/Write : 7 -- Undefined R/W 6 -- Undefined R/W 5 -- Undefined R/W 4 -- Undefined R/W H'F858 3 DLC3 Undefined R/W 2 DLC2 Undefined R/W 1 DLC1 Undefined R/W 0 DLC0 Undefined R/W HCAN Data length code 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0/1 0/1 0/1 MCx[2] Bit : Initial value : Read/Write : MCx[3] Bit : Initial value : Read/Write : MCx[4] Bit : Initial value : Read/Write : MCx[5] Bit : Initial value : Read/Write : 7 -- Undefined R/W 7 -- Undefined R/W 7 -- Undefined R/W 7 STD_ID2 Undefined R/W 6 -- Undefined R/W 6 -- Undefined R/W 6 -- Undefined R/W 6 STD_ID1 Undefined R/W 5 -- Undefined R/W 5 -- Undefined R/W 5 -- Undefined R/W 5 STD_ID0 Undefined R/W 4 -- Undefined R/W 4 -- Undefined R/W 4 -- Undefined R/W 4 RTR Undefined R/W 3 -- Undefined R/W 3 -- Undefined R/W 3 -- Undefined R/W 3 IDE Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes Data length = 8 bytes 1 -- Undefined R/W 1 -- Undefined R/W 1 -- Undefined R/W 1 EXD_ID17 Undefined R/W 0 -- Undefined R/W 0 -- Undefined R/W 0 -- Undefined R/W 0 EXD_ID16 Undefined R/W Identifier extension 0 Standard format 1 Extended format Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[6] Bit : Initial value : Read/Write : 7 STD_ID10 Undefined R/W 6 STD_ID9 Undefined R/W Remote transmission request 0 Data frame 1 Remote frame 4 STD_ID7 Undefined R/W 3 STD_ID6 Undefined R/W 2 STD_ID5 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames 5 STD_ID8 Undefined R/W 1 STD_ID4 Undefined R/W 0 STD_ID3 Undefined R/W Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[7] Bit : Initial value : Read/Write : MCx[8] Bit : Initial value : Read/Write : 7 EXD_ID7 Undefined R/W 7 EXD_ID15 Undefined R/W 6 EXD_ID6 Undefined R/W 6 EXD_ID14 Undefined R/W 5 EXD_ID5 Undefined R/W 5 EXD_ID13 Undefined R/W 4 EXD_ID4 Undefined R/W 4 EXD_ID12 Undefined R/W 3 EXD_ID3 Undefined R/W 3 EXD_ID11 Undefined R/W 2 EXD_ID2 Undefined R/W 2 EXD_ID10 Undefined R/W 1 EXD_ID1 Undefined R/W 1 EXD_ID9 Undefined R/W 0 EXD_ID0 Undefined R/W 0 EXD_ID8 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames x=7 867 MC8--Message Control MCx[1] Bit : Initial value : Read/Write : 7 -- Undefined R/W 6 -- Undefined R/W 5 -- Undefined R/W 4 -- Undefined R/W H'F860 3 DLC3 Undefined R/W 2 DLC2 Undefined R/W 1 DLC1 Undefined R/W 0 DLC0 Undefined R/W HCAN Data length code 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0/1 0/1 0/1 MCx[2] Bit : Initial value : Read/Write : MCx[3] Bit : Initial value : Read/Write : MCx[4] Bit : Initial value : Read/Write : MCx[5] Bit : Initial value : Read/Write : 7 -- Undefined R/W 7 -- Undefined R/W 7 -- Undefined R/W 7 STD_ID2 Undefined R/W 6 -- Undefined R/W 6 -- Undefined R/W 6 -- Undefined R/W 6 STD_ID1 Undefined R/W 5 -- Undefined R/W 5 -- Undefined R/W 5 -- Undefined R/W 5 STD_ID0 Undefined R/W 4 -- Undefined R/W 4 -- Undefined R/W 4 -- Undefined R/W 4 RTR Undefined R/W 3 -- Undefined R/W 3 -- Undefined R/W 3 -- Undefined R/W 3 IDE Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes Data length = 8 bytes 1 -- Undefined R/W 1 -- Undefined R/W 1 -- Undefined R/W 1 EXD_ID17 Undefined R/W 0 -- Undefined R/W 0 -- Undefined R/W 0 -- Undefined R/W 0 EXD_ID16 Undefined R/W Identifier extension 0 Standard format 1 Extended format Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[6] Bit : Initial value : Read/Write : 7 STD_ID10 Undefined R/W 6 STD_ID9 Undefined R/W Remote transmission request 0 Data frame 1 Remote frame 4 STD_ID7 Undefined R/W 3 STD_ID6 Undefined R/W 2 STD_ID5 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames 5 STD_ID8 Undefined R/W 1 STD_ID4 Undefined R/W 0 STD_ID3 Undefined R/W Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[7] Bit : Initial value : Read/Write : MCx[8] Bit : Initial value : Read/Write : 7 EXD_ID7 Undefined R/W 7 EXD_ID15 Undefined R/W 6 EXD_ID6 Undefined R/W 6 EXD_ID14 Undefined R/W 5 EXD_ID5 Undefined R/W 5 EXD_ID13 Undefined R/W 4 EXD_ID4 Undefined R/W 4 EXD_ID12 Undefined R/W 3 EXD_ID3 Undefined R/W 3 EXD_ID11 Undefined R/W 2 EXD_ID2 Undefined R/W 2 EXD_ID10 Undefined R/W 1 EXD_ID1 Undefined R/W 1 EXD_ID9 Undefined R/W 0 EXD_ID0 Undefined R/W 0 EXD_ID8 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames x=8 868 MC9--Message Control MCx[1] Bit : Initial value : Read/Write : 7 -- Undefined R/W 6 -- Undefined R/W 5 -- Undefined R/W 4 -- Undefined R/W H'F868 3 DLC3 Undefined R/W 2 DLC2 Undefined R/W 1 DLC1 Undefined R/W 0 DLC0 Undefined R/W HCAN Data length code 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0/1 0/1 0/1 MCx[2] Bit : Initial value : Read/Write : MCx[3] Bit : Initial value : Read/Write : MCx[4] Bit : Initial value : Read/Write : MCx[5] Bit : Initial value : Read/Write : 7 -- Undefined R/W 7 -- Undefined R/W 7 -- Undefined R/W 7 STD_ID2 Undefined R/W 6 -- Undefined R/W 6 -- Undefined R/W 6 -- Undefined R/W 6 STD_ID1 Undefined R/W 5 -- Undefined R/W 5 -- Undefined R/W 5 -- Undefined R/W 5 STD_ID0 Undefined R/W 4 -- Undefined R/W 4 -- Undefined R/W 4 -- Undefined R/W 4 RTR Undefined R/W 3 -- Undefined R/W 3 -- Undefined R/W 3 -- Undefined R/W 3 IDE Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes Data length = 8 bytes 1 -- Undefined R/W 1 -- Undefined R/W 1 -- Undefined R/W 1 EXD_ID17 Undefined R/W 0 -- Undefined R/W 0 -- Undefined R/W 0 -- Undefined R/W 0 EXD_ID16 Undefined R/W Identifier extension 0 Standard format 1 Extended format Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[6] Bit : Initial value : Read/Write : 7 STD_ID10 Undefined R/W 6 STD_ID9 Undefined R/W Remote transmission request 0 Data frame 1 Remote frame 4 STD_ID7 Undefined R/W 3 STD_ID6 Undefined R/W 2 STD_ID5 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames 5 STD_ID8 Undefined R/W 1 STD_ID4 Undefined R/W 0 STD_ID3 Undefined R/W Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[7] Bit : Initial value : Read/Write : MCx[8] Bit : Initial value : Read/Write : 7 EXD_ID7 Undefined R/W 7 EXD_ID15 Undefined R/W 6 EXD_ID6 Undefined R/W 6 EXD_ID14 Undefined R/W 5 EXD_ID5 Undefined R/W 5 EXD_ID13 Undefined R/W 4 EXD_ID4 Undefined R/W 4 EXD_ID12 Undefined R/W 3 EXD_ID3 Undefined R/W 3 EXD_ID11 Undefined R/W 2 EXD_ID2 Undefined R/W 2 EXD_ID10 Undefined R/W 1 EXD_ID1 Undefined R/W 1 EXD_ID9 Undefined R/W 0 EXD_ID0 Undefined R/W 0 EXD_ID8 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames x=9 869 MC10--Message Control MCx[1] Bit : Initial value : Read/Write : 7 -- Undefined R/W 6 -- Undefined R/W 5 -- Undefined R/W 4 -- Undefined R/W H'F870 3 DLC3 Undefined R/W 2 DLC2 Undefined R/W 1 DLC1 Undefined R/W 0 DLC0 Undefined R/W HCAN Data length code 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0/1 0/1 0/1 MCx[2] Bit : Initial value : Read/Write : MCx[3] Bit : Initial value : Read/Write : MCx[4] Bit : Initial value : Read/Write : MCx[5] Bit : Initial value : Read/Write : 7 -- Undefined R/W 7 -- Undefined R/W 7 -- Undefined R/W 7 STD_ID2 Undefined R/W 6 -- Undefined R/W 6 -- Undefined R/W 6 -- Undefined R/W 6 STD_ID1 Undefined R/W 5 -- Undefined R/W 5 -- Undefined R/W 5 -- Undefined R/W 5 STD_ID0 Undefined R/W 4 -- Undefined R/W 4 -- Undefined R/W 4 -- Undefined R/W 4 RTR Undefined R/W 3 -- Undefined R/W 3 -- Undefined R/W 3 -- Undefined R/W 3 IDE Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes Data length = 8 bytes 1 -- Undefined R/W 1 -- Undefined R/W 1 -- Undefined R/W 1 EXD_ID17 Undefined R/W 0 -- Undefined R/W 0 -- Undefined R/W 0 -- Undefined R/W 0 EXD_ID16 Undefined R/W Identifier extension 0 Standard format 1 Extended format Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[6] Bit : Initial value : Read/Write : 7 STD_ID10 Undefined R/W 6 STD_ID9 Undefined R/W Remote transmission request 0 Data frame 1 Remote frame 4 STD_ID7 Undefined R/W 3 STD_ID6 Undefined R/W 2 STD_ID5 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames 5 STD_ID8 Undefined R/W 1 STD_ID4 Undefined R/W 0 STD_ID3 Undefined R/W Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[7] Bit : Initial value : Read/Write : MCx[8] Bit : Initial value : Read/Write : 7 EXD_ID7 Undefined R/W 7 EXD_ID15 Undefined R/W 6 EXD_ID6 Undefined R/W 6 EXD_ID14 Undefined R/W 5 EXD_ID5 Undefined R/W 5 EXD_ID13 Undefined R/W 4 EXD_ID4 Undefined R/W 4 EXD_ID12 Undefined R/W 3 EXD_ID3 Undefined R/W 3 EXD_ID11 Undefined R/W 2 EXD_ID2 Undefined R/W 2 EXD_ID10 Undefined R/W 1 EXD_ID1 Undefined R/W 1 EXD_ID9 Undefined R/W 0 EXD_ID0 Undefined R/W 0 EXD_ID8 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames x = 10 870 MC11--Message Control MCx[1] Bit : Initial value : Read/Write : 7 -- Undefined R/W 6 -- Undefined R/W 5 -- Undefined R/W 4 -- Undefined R/W H'F878 3 DLC3 Undefined R/W 2 DLC2 Undefined R/W 1 DLC1 Undefined R/W 0 DLC0 Undefined R/W HCAN Data length code 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0/1 0/1 0/1 MCx[2] Bit : Initial value : Read/Write : MCx[3] Bit : Initial value : Read/Write : MCx[4] Bit : Initial value : Read/Write : MCx[5] Bit : Initial value : Read/Write : 7 -- Undefined R/W 7 -- Undefined R/W 7 -- Undefined R/W 7 STD_ID2 Undefined R/W 6 -- Undefined R/W 6 -- Undefined R/W 6 -- Undefined R/W 6 STD_ID1 Undefined R/W 5 -- Undefined R/W 5 -- Undefined R/W 5 -- Undefined R/W 5 STD_ID0 Undefined R/W 4 -- Undefined R/W 4 -- Undefined R/W 4 -- Undefined R/W 4 RTR Undefined R/W 3 -- Undefined R/W 3 -- Undefined R/W 3 -- Undefined R/W 3 IDE Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes Data length = 8 bytes 1 -- Undefined R/W 1 -- Undefined R/W 1 -- Undefined R/W 1 EXD_ID17 Undefined R/W 0 -- Undefined R/W 0 -- Undefined R/W 0 -- Undefined R/W 0 EXD_ID16 Undefined R/W Identifier extension 0 Standard format 1 Extended format Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[6] Bit : Initial value : Read/Write : 7 STD_ID10 Undefined R/W 6 STD_ID9 Undefined R/W Remote transmission request 0 Data frame 1 Remote frame 4 STD_ID7 Undefined R/W 3 STD_ID6 Undefined R/W 2 STD_ID5 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames 5 STD_ID8 Undefined R/W 1 STD_ID4 Undefined R/W 0 STD_ID3 Undefined R/W Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[7] Bit : Initial value : Read/Write : MCx[8] Bit : Initial value : Read/Write : 7 EXD_ID7 Undefined R/W 7 EXD_ID15 Undefined R/W 6 EXD_ID6 Undefined R/W 6 EXD_ID14 Undefined R/W 5 EXD_ID5 Undefined R/W 5 EXD_ID13 Undefined R/W 4 EXD_ID4 Undefined R/W 4 EXD_ID12 Undefined R/W 3 EXD_ID3 Undefined R/W 3 EXD_ID11 Undefined R/W 2 EXD_ID2 Undefined R/W 2 EXD_ID10 Undefined R/W 1 EXD_ID1 Undefined R/W 1 EXD_ID9 Undefined R/W 0 EXD_ID0 Undefined R/W 0 EXD_ID8 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames x = 11 871 MC12--Message Control MCx[1] Bit : Initial value : Read/Write : 7 -- Undefined R/W 6 -- Undefined R/W 5 -- Undefined R/W 4 -- Undefined R/W H'F880 3 DLC3 Undefined R/W 2 DLC2 Undefined R/W 1 DLC1 Undefined R/W 0 DLC0 Undefined R/W HCAN Data length code 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0/1 0/1 0/1 MCx[2] Bit : Initial value : Read/Write : MCx[3] Bit : Initial value : Read/Write : MCx[4] Bit : Initial value : Read/Write : MCx[5] Bit : Initial value : Read/Write : 7 -- Undefined R/W 7 -- Undefined R/W 7 -- Undefined R/W 7 STD_ID2 Undefined R/W 6 -- Undefined R/W 6 -- Undefined R/W 6 -- Undefined R/W 6 STD_ID1 Undefined R/W 5 -- Undefined R/W 5 -- Undefined R/W 5 -- Undefined R/W 5 STD_ID0 Undefined R/W 4 -- Undefined R/W 4 -- Undefined R/W 4 -- Undefined R/W 4 RTR Undefined R/W 3 -- Undefined R/W 3 -- Undefined R/W 3 -- Undefined R/W 3 IDE Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes Data length = 8 bytes 1 -- Undefined R/W 1 -- Undefined R/W 1 -- Undefined R/W 1 EXD_ID17 Undefined R/W 0 -- Undefined R/W 0 -- Undefined R/W 0 -- Undefined R/W 0 EXD_ID16 Undefined R/W Identifier extension 0 Standard format 1 Extended format Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[6] Bit : Initial value : Read/Write : 7 STD_ID10 Undefined R/W 6 STD_ID9 Undefined R/W Remote transmission request 0 Data frame 1 Remote frame 4 STD_ID7 Undefined R/W 3 STD_ID6 Undefined R/W 2 STD_ID5 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames 5 STD_ID8 Undefined R/W 1 STD_ID4 Undefined R/W 0 STD_ID3 Undefined R/W Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[7] Bit : Initial value : Read/Write : MCx[8] Bit : Initial value : Read/Write : 7 EXD_ID7 Undefined R/W 7 EXD_ID15 Undefined R/W 6 EXD_ID6 Undefined R/W 6 EXD_ID14 Undefined R/W 5 EXD_ID5 Undefined R/W 5 EXD_ID13 Undefined R/W 4 EXD_ID4 Undefined R/W 4 EXD_ID12 Undefined R/W 3 EXD_ID3 Undefined R/W 3 EXD_ID11 Undefined R/W 2 EXD_ID2 Undefined R/W 2 EXD_ID10 Undefined R/W 1 EXD_ID1 Undefined R/W 1 EXD_ID9 Undefined R/W 0 EXD_ID0 Undefined R/W 0 EXD_ID8 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames x = 12 872 MC13--Message Control MCx[1] Bit : Initial value : Read/Write : 7 -- Undefined R/W 6 -- Undefined R/W 5 -- Undefined R/W 4 -- Undefined R/W H'F888 3 DLC3 Undefined R/W 2 DLC2 Undefined R/W 1 DLC1 Undefined R/W 0 DLC0 Undefined R/W HCAN Data length code 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0/1 0/1 0/1 MCx[2] Bit : Initial value : Read/Write : MCx[3] Bit : Initial value : Read/Write : MCx[4] Bit : Initial value : Read/Write : MCx[5] Bit : Initial value : Read/Write : 7 -- Undefined R/W 7 -- Undefined R/W 7 -- Undefined R/W 7 STD_ID2 Undefined R/W 6 -- Undefined R/W 6 -- Undefined R/W 6 -- Undefined R/W 6 STD_ID1 Undefined R/W 5 -- Undefined R/W 5 -- Undefined R/W 5 -- Undefined R/W 5 STD_ID0 Undefined R/W 4 -- Undefined R/W 4 -- Undefined R/W 4 -- Undefined R/W 4 RTR Undefined R/W 3 -- Undefined R/W 3 -- Undefined R/W 3 -- Undefined R/W 3 IDE Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes Data length = 8 bytes 1 -- Undefined R/W 1 -- Undefined R/W 1 -- Undefined R/W 1 EXD_ID17 Undefined R/W 0 -- Undefined R/W 0 -- Undefined R/W 0 -- Undefined R/W 0 EXD_ID16 Undefined R/W Identifier extension 0 Standard format 1 Extended format Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[6] Bit : Initial value : Read/Write : 7 STD_ID10 Undefined R/W 6 STD_ID9 Undefined R/W Remote transmission request 0 Data frame 1 Remote frame 4 STD_ID7 Undefined R/W 3 STD_ID6 Undefined R/W 2 STD_ID5 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames 5 STD_ID8 Undefined R/W 1 STD_ID4 Undefined R/W 0 STD_ID3 Undefined R/W Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[7] Bit : Initial value : Read/Write : MCx[8] Bit : Initial value : Read/Write : 7 EXD_ID7 Undefined R/W 7 EXD_ID15 Undefined R/W 6 EXD_ID6 Undefined R/W 6 EXD_ID14 Undefined R/W 5 EXD_ID5 Undefined R/W 5 EXD_ID13 Undefined R/W 4 EXD_ID4 Undefined R/W 4 EXD_ID12 Undefined R/W 3 EXD_ID3 Undefined R/W 3 EXD_ID11 Undefined R/W 2 EXD_ID2 Undefined R/W 2 EXD_ID10 Undefined R/W 1 EXD_ID1 Undefined R/W 1 EXD_ID9 Undefined R/W 0 EXD_ID0 Undefined R/W 0 EXD_ID8 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames x = 13 873 MC14--Message Control MCx[1] Bit : Initial value : Read/Write : 7 -- Undefined R/W 6 -- Undefined R/W 5 -- Undefined R/W 4 -- Undefined R/W H'F890 3 DLC3 Undefined R/W 2 DLC2 Undefined R/W 1 DLC1 Undefined R/W 0 DLC0 Undefined R/W HCAN Data length code 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0/1 0/1 0/1 MCx[2] Bit : Initial value : Read/Write : MCx[3] Bit : Initial value : Read/Write : MCx[4] Bit : Initial value : Read/Write : MCx[5] Bit : Initial value : Read/Write : 7 -- Undefined R/W 7 -- Undefined R/W 7 -- Undefined R/W 7 STD_ID2 Undefined R/W 6 -- Undefined R/W 6 -- Undefined R/W 6 -- Undefined R/W 6 STD_ID1 Undefined R/W 5 -- Undefined R/W 5 -- Undefined R/W 5 -- Undefined R/W 5 STD_ID0 Undefined R/W 4 -- Undefined R/W 4 -- Undefined R/W 4 -- Undefined R/W 4 RTR Undefined R/W 3 -- Undefined R/W 3 -- Undefined R/W 3 -- Undefined R/W 3 IDE Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes Data length = 8 bytes 1 -- Undefined R/W 1 -- Undefined R/W 1 -- Undefined R/W 1 EXD_ID17 Undefined R/W 0 -- Undefined R/W 0 -- Undefined R/W 0 -- Undefined R/W 0 EXD_ID16 Undefined R/W Identifier extension 0 Standard format 1 Extended format Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[6] Bit : Initial value : Read/Write : 7 STD_ID10 Undefined R/W 6 STD_ID9 Undefined R/W Remote transmission request 0 Data frame 1 Remote frame 4 STD_ID7 Undefined R/W 3 STD_ID6 Undefined R/W 2 STD_ID5 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames 5 STD_ID8 Undefined R/W 1 STD_ID4 Undefined R/W 0 STD_ID3 Undefined R/W Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[7] Bit : Initial value : Read/Write : MCx[8] Bit : Initial value : Read/Write : 7 EXD_ID7 Undefined R/W 7 EXD_ID15 Undefined R/W 6 EXD_ID6 Undefined R/W 6 EXD_ID14 Undefined R/W 5 EXD_ID5 Undefined R/W 5 EXD_ID13 Undefined R/W 4 EXD_ID4 Undefined R/W 4 EXD_ID12 Undefined R/W 3 EXD_ID3 Undefined R/W 3 EXD_ID11 Undefined R/W 2 EXD_ID2 Undefined R/W 2 EXD_ID10 Undefined R/W 1 EXD_ID1 Undefined R/W 1 EXD_ID9 Undefined R/W 0 EXD_ID0 Undefined R/W 0 EXD_ID8 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames x = 14 874 MC15--Message Control MCx[1] Bit : Initial value : Read/Write : 7 -- Undefined R/W 6 -- Undefined R/W 5 -- Undefined R/W 4 -- Undefined R/W H'F898 3 DLC3 Undefined R/W 2 DLC2 Undefined R/W 1 DLC1 Undefined R/W 0 DLC0 Undefined R/W HCAN Data length code 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0/1 0/1 0/1 MCx[2] Bit : Initial value : Read/Write : MCx[3] Bit : Initial value : Read/Write : MCx[4] Bit : Initial value : Read/Write : MCx[5] Bit : Initial value : Read/Write : 7 -- Undefined R/W 7 -- Undefined R/W 7 -- Undefined R/W 7 STD_ID2 Undefined R/W 6 -- Undefined R/W 6 -- Undefined R/W 6 -- Undefined R/W 6 STD_ID1 Undefined R/W 5 -- Undefined R/W 5 -- Undefined R/W 5 -- Undefined R/W 5 STD_ID0 Undefined R/W 4 -- Undefined R/W 4 -- Undefined R/W 4 -- Undefined R/W 4 RTR Undefined R/W 3 -- Undefined R/W 3 -- Undefined R/W 3 -- Undefined R/W 3 IDE Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W 2 -- Undefined R/W Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes Data length = 8 bytes 1 -- Undefined R/W 1 -- Undefined R/W 1 -- Undefined R/W 1 EXD_ID17 Undefined R/W 0 -- Undefined R/W 0 -- Undefined R/W 0 -- Undefined R/W 0 EXD_ID16 Undefined R/W Identifier extension 0 Standard format 1 Extended format Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[6] Bit : Initial value : Read/Write : 7 STD_ID10 Undefined R/W 6 STD_ID9 Undefined R/W Remote transmission request 0 Data frame 1 Remote frame 4 STD_ID7 Undefined R/W 3 STD_ID6 Undefined R/W 2 STD_ID5 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames 5 STD_ID8 Undefined R/W 1 STD_ID4 Undefined R/W 0 STD_ID3 Undefined R/W Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[7] Bit : Initial value : Read/Write : MCx[8] Bit : Initial value : Read/Write : 7 EXD_ID7 Undefined R/W 7 EXD_ID15 Undefined R/W 6 EXD_ID6 Undefined R/W 6 EXD_ID14 Undefined R/W 5 EXD_ID5 Undefined R/W 5 EXD_ID13 Undefined R/W 4 EXD_ID4 Undefined R/W 4 EXD_ID12 Undefined R/W 3 EXD_ID3 Undefined R/W 3 EXD_ID11 Undefined R/W 2 EXD_ID2 Undefined R/W 2 EXD_ID10 Undefined R/W 1 EXD_ID1 Undefined R/W 1 EXD_ID9 Undefined R/W 0 EXD_ID0 Undefined R/W 0 EXD_ID8 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames x = 15 875 MD0--Message Data MD1--Message Data MD2--Message Data MD3--Message Data MD4--Message Data MD5--Message Data MD6--Message Data MD7--Message Data MD8--Message Data MD9--Message Data MD10--Message Data MD11--Message Data MD12--Message Data MD13--Message Data MD14--Message Data MD15--Message Data MDx [1] Bit: 7 6 5 H'F8B0 H'F8B8 H'F8C0 H'F8C8 H'F8D0 H'F8D8 H'F8E0 H'F8E8 H'F8F0 H'F8F8 H'F900 H'F908 H'F910 H'F918 H'F920 H'F928 HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN 4 3 2 1 0 Initial value: Read/Write: MDx [2] Bit: * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W 7 6 5 4 3 2 1 0 Initial value: Read/Write: MDx [3] Bit: * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W 7 6 5 4 3 2 1 0 Initial value: Read/Write: * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W 876 MDx [4] Bit: 7 6 5 4 3 2 1 0 Initial value: Read/Write: MDx [5] Bit: * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W 7 6 5 4 3 2 1 0 Initial value: Read/Write: MDx [6] Bit: * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W 7 6 5 4 3 2 1 0 Initial value: Read/Write: MDx [7] Bit: * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W 7 6 5 4 3 2 1 0 Initial value: Read/Write: MDx [8] Bit: * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W 7 6 5 4 3 2 1 0 Initial value: Read/Write: * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W *:Undefined x = 0 to 15 877 DADR2--D/A Data Register 2 DADR3--D/A Data Register 3 Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FDAC H'FDAD 3 0 R/W 2 0 R/W 1 0 R/W D/A2 D/A3 0 0 R/W Initial value : Read/Write : DACR23--D/A Control Register 23 Bit : 7 DAOE1 Initial value : Read/Write : 0 R/W 6 DAOE0 0 R/W 5 DAE 0 R/W 4 -- 1 -- H'FDAE 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- D/A2, 3 0 -- 1 -- D/A enable DAOE1 DAOE0 0 0 1 DAE * 0 1 1 0 0 1 1 D/A output enable 0 0 Disables analog output DA2 1 Enables channel 2 D/A conversion. Also enables analog output DA2 D/A output enable 1 0 Disables analog output DA3 1 Enables channel 3 D/A conversion. Also enables analog output DA3 * Description Disables channel 2, 3 D/A conversion Enables channel 2 D/A conversion Disables channel 3 D/A conversion Enables channel 2, 3 D/A conversion Disables channel 2 D/A conversion Enables channel 3 D/A conversion Enables channel 2, 3 D/A conversion Enables channel 2, 3 D/A conversion *: Don't care 878 SCRX--Serial Control Register X Bit : 7 -- Initial value : Read/Write : 0 R/W 6 -- 0 R/W 5 -- 0 R/W 4 -- 0 R/W H'FDB4 3 FLSHE 0 R/W 2 -- 0 R/W 1 -- 0 R/W ROM 0 -- 0 R/W Flash memory control register enable 0 Area H'FFFFA8 to H'FFFFAC flash control registers are not selected 1 Area H'FFFFA8 to H'FFFFAC flash control registers are selected SBYCR--Standby Control Register Bit : 7 SSBY Initial value : Read/Write : 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W H'FDE4 3 OPE 1 R/W 2 -- 0 -- Power-Down Modes 1 -- 0 -- 0 -- 0 -- Output port enable 0 In software standby mode, address bus and bus control signals are high-impedance 1 In software standby mode, address bus and bus control signals retain their output state Standby timer select 0 0 1 1 0 1 0 Standby time = 8192 states 1 Standby time = 16384 states 0 Standby time = 32768 states 1 Standby time = 65536 states 0 Standby time = 131072 states 1 Standby time = 262144 states 0 Reserved 1 Standby time = 16 states Software standby 0 Transition to sleep mode after execution of SLEEP instruction 1 Transition to software standby mode after execution of SLEEP instruction 879 SYSCR--System Control Register Bit : 7 MACS Initial value : Read/Write : 0 R/W 6 -- 0 -- 5 INTM1 0 R/W 4 INTM0 0 R/W H'FDE5 3 NMIEG 0 R/W 2 -- 0 R/W RAM enable 1 -- 0 -- 0 MCU RAME 1 R/W 0 On-chip RAM is disabled 1 On-chip RAM is enabled Note: When the DTC is used, the RAME bit must be set to 1. NMI interrupt input edge select 0 Falling edge 1 Rising edge Interrupt control mode select 0 1 0 Interrupt control mode 0 1 Setting prohibited 0 Interrupt control mode 2 1 Setting prohibited Note: For details, see section 5.4.1 Interrupt Control Modes and Interrupt Operation. Mac saturation 0 Non-saturating calculation for MAC instruction 1 Saturating calculation for MAC instruction 880 SCKCR--System Clock Control Register Bit : 7 PSTOP Initial value : Read/Write : 0 R/W 6 -- 0 -- 5 -- 0 -- H'FDE6 4 -- 0 -- Clock Pulse Generator, Power-Down 3 STCS 0 R/W 2 SCK2 0 R/W 1 SCK1 0 R/W 0 SCK0 0 R/W Bus master clock select 0 0 1 1 0 0 Bus master is in high-speed mode 1 Medium-speed clock is o/2 0 Medium-speed clock is o/4 1 Medium-speed clock is o/8 1 Medium-speed clock is o/16 1 Medium-speed clock is o/32 1 ---- Frequency multiplication factor switching mode select 0 Specified multiplication factor is valid after transition to software standby mode 1 Specified multiplication factor is valid immediately after STC bits are rewritten o clock output control High-Speed Mode, Sleep Mode, PSTOP Medium-Speed Mode, Sub-Sleep Mode* Sub-Active Mode* 0 1 o output Fixed high o output Fixed high Software Standby Mode, Watch Mode*, Direct Transition* Fixed high Fixed high Hardware Standby Mode High impedance High impedance Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) and direct transition are not available in the H8S/2623 Series, but are available in the H8S/2626 Series. 881 MDCR--Mode Control Register Bit : 7 -- Initial value : Read/Write : 1 R/W 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- H'FDE7 3 -- 0 -- 2 MDS2 --* R 1 MDS1 --* R 0 MCU MDS0 --* R Current mode pin operating mode Note: * Determined by pins MD2 to MD0. 882 MSTPCRA--Module Stop Control Register MSTPCRB--Module Stop Control Register MSTPCRC--Module Stop Control Register MSTPCRA Bit : 7 0 R/W 6 0 R/W 5 1 R/W 4 1 R/W 3 1 R/W H'FDE8 H'FDE9 H'FDEA Power-Down Modes Power-Down Modes Power-Down Modes 2 1 R/W 1 1 R/W 0 1 R/W MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value : Read/Write : MSTPCRB Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0 Initial value : Read/Write : MSTPCRC Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 Initial value : Read/Write : Module stop mode specification 0 Module stop mode is cleared (initial value of MSTPA7 and MSTPA6) 1 Module stop mode is set (initial value of MSTPA5-0, MSTPB7-0, and MSTPC7-0) MSTP bits and corresponding on-chip supporting modules Register MSTPCRA Bit MSTPA7* MSTPA6 MSTPA5 MSTPA4* MSTPA3 MSTPA2* MSTPA1 MSTPA0* MSTPCRB MSTPB7 MSTPB6 MSTPB5 MSTPB4* MSTPB3* MSTPB2* MSTPB1* MSTPB0* MSTPCRC MSTPC7* MSTPC6* MSTPC5 MSTPC4 MSTPC3 MSTPC2* MSTPC1* MSTPC0* Notes: * -- Data transfer controller (DTC) 16-bit timer pulse unit (TPU) -- Programmable pulse generator (PPG) -- A/D converter -- Serial communication interface 0 (SCI0) Serial communication interface 1 (SCI1) Serial communication interface 2 (SCI2) -- -- -- -- -- -- -- D/A converter (channels 2, 3) PC break controller (PBC) HCAN -- -- -- Module MSTPA7 is a readable/writable bit with an initial value of 0. MSTPA4, MSTPA2, MSTPA0, MSTPB4 to MSTPB0, MSTPC7 to MSTPC4, and MSTPC2 to MSTPC0 are readable/writable bits with an initial value of 1 and should always be written with 1. 883 PFCR--Pin Function Control Register Bit : 7 -- Initial value : Read/Write : 0 R/W 6 -- 0 R/W 5 BUZZE 0*2 R/W 4 -- 0 R/W H'FDEB 3 AE3 1/0*1 R/W 2 AE2 1/0*1 R/W MCU, Bus Controller 1 AE1 0 R/W 0 AE0 1/0*1 R/W Address output enable 0 0 0 1 1 0 1 1 0 0 1 1 0 1 0 A8-A23 address output disabled 1 A8 address output enabled; A9-A23 address output disabled 0 A8, A9 address output enabled; A10-A23 address output disabled 1 A8-A10 address output enabled; A11-A23 address output disabled 0 A8-A11 address output enabled; A12-A23 address output disabled 1 A8-A12 address output enabled; A13-A23 address output disabled 0 A8-A13 address output enabled; A14-A23 address output disabled 1 A8-A14 address output enabled; A15-A23 address output disabled 0 A8-A15 address output enabled; A16-A23 address output disabled 1 A8-A16 address output enabled; A17-A23 address output disabled 0 A8-A17 address output enabled; A18-A23 address output disabled 1 A8-A18 address output enabled; A19-A23 address output disabled 0 A8-A19 address output enabled; A20-A23 address output disabled 1 A8-A20 address output enabled; A21-A23 address output disabled 0 A8-A21 address output enabled; A22, A23 address output disabled 1 A8-A23 address output enabled BUZZ output enable 0 Functions as PF1 I/O pin 1 Functions as BUZZ output pin Notes: *1 In expanded mode with ROM, bits AE3 to AE0 are initialized to B'0000. In ROMless expanded mode, bits AE3 to AE0 are initialized to B'1101. Address pins A0 to A7 are made address outputs by setting the corresponding DDR bits to 1. *2 This bit is valid only in the H8S/2626 Series; in the H8S/2623 Series, 0 must be written to this bit. 884 LPWRCR--Low-Power Control Register Bit : 7 DTON Initial value : Read/Write : 0 R/W 6 LSON 0 R/W 5 0 R/W 4 0 R/W H'FDEC 3 0 R/W 2 -- 0 R/W STC1 0 1 Clock Pulse Generator 1 STC1 0 R/W STC0 0 1 0 1 x 1 (initial value) x2 x4 Do not set 0 STC0 0 R/W NESEL SUBSTP RFCUT Frequency multiplier Note: A system clock frequency multiplied by the multiplication factor (STC1 and STC0) should not exceed the maximum operating frequency defined in section 22 Electrical Characteristics. Oscillator circuit feedback resistor control bit 0 Feedback resistor ON when main clock operating; OFF when not operation 1 Feedback resistor OFF Subclock enable 0 Subclock generation enabled 1 Subclock generation disabled Note: This bit is valid only in the H8S/2626 Series; in the H8S/2623 Series, 0 must be written to this bit. Noise elimination sampling frequency select 0 Sampling uses o/32 clock 1 Sampling uses o/4 clock Note: This bit is valid only in the H8S/2626 Series; in the H8S/2623 Series, 0 must be written to this bit. Low-speed ON flag 0 * When the SLEEP command is executed in high-speed mode or medium-speed mode, operation transfers to sleep mode, software standby mode, or watch mode* * When the SLEEP command is executed in sub-active mode, operation transfers to watch mode, or directly to high-speed mode * Operation transfers to high-speed mode after watch mode is canceled 1 * When the SLEEP command is executed in high-speed mode, operation transfers to watch mode or sub-active mode * When the SLEEP command is executed in sub-active mode, operation transfers to sub-sleep mode or watch mode * Operation transfers to sub-active mode immediately watch mode is canceled Notes: This bit is valid only in the H8S/2626 Series; in the H8S/2623 Series, 0 must be written to this bit. * Always select high-speed mode when transferring to watch mode or sub-active mode. Direct transfer ON flag 0 * When the SLEEP command is executed in high-speed mode or medium-speed mode, operation transfers to sleep mode, software standby mode, or watch mode* * When the SLEEP command is executed in sub-active mode, operation transfers to sub-sleep mode or watch mode 1 * When the SLEEP command is executed in high-speed mode or medium-speed mode, operation transfers directly to sub-active mode, or transfers to sleep mode or software standby mode * When the SLEEP command is executed in sub-active mode, operation transfers directly to highspeed mode or transfers to sub-sleep mode Notes: This bit is valid only in the H8S/2626 Series; in the H8S/2623 Series, 0 must be written to this bit. * Always select high-speed mode when transferring to watch mode or sub-active mode. 885 BARA--Break Address Register A BARB--Break Address Register B Bit : 31 -- ... ... 24 23 22 21 20 19 18 17 H'FE00 H'FE04 16 ... ... ... ... 7 6 5 4 3 2 1 PBC PBC 0 BAA BAA BAA BAA BAA BAA BAA BAA -- 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 BAA BAA BAA BAA BAA BAA BAA BAA 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Initial value : Unde- ... Unde- 0 fined fined Read/Write : -- ... -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Break address specification 886 BCRA--Break Control Register A BCRB--Break Control Register B Bit : 7 CMFA Initial value : Read/Write : 0 R/(W)* 6 CDA 0 R/W 5 0 R/W 4 0 R/W H'FE08 H'FE09 3 0 R/W 2 0 R/W 1 0 R/W 0 PBC PBC BAMRA2 BAMRA1 BAMRA0 CSELA1 CSELA0 BIEA 0 R/W Break interrupt enable 0 PC break interrupts are disabled 1 PC break interrupts are enabled Break condition select 0 1 0 Instruction fetch is used as break condition 1 Data read cycle is used as break condition 0 Data write cycle is used as break condition 1 Data read/write cycle is used as break condition Break address mask register 0 0 0 All BARA bits are unmasked and included in break conditions 1 BAA0 (lowest bit) is masked, and not included in break conditions 1 0 BAA1-0 (lower 2 bits) are masked, and not included in break conditions 1 BAA2-0 (lower 3 bits) are masked, and not included in break conditions 1 0 0 BAA3-0 (lower 4 bits) are masked, and not included in break conditions 1 BAA7-0 (lower 8 bits) are masked, and not included in break conditions 1 0 BAA11-0 (lower 12 bits) are masked, and not included in break conditions 1 BAA15-0 (lower 16 bits) are masked, and not included in break conditions CPU cycle/DTC cycle select A 0 PC break is performed when CPU is bus master 1 PC break is performed when CPU or DTC is bus master Condition match flag 0 [Clearing condition] When 0 is written to CMFA after reading CMFA = 1 1 [Setting condition] When a condition set for channel A is satisfied Notes: The bit configuration of BCRB is the same as that of BCRA, except that BCRB performs break control for channel B. * Can only be written with 0 for flag clearing. 887 ISCRH--IRQ Sense Control Register H ISCRL--IRQ Sense Control Register L ISCRH Bit : 15 -- Initial value : Read/Write : 0 R/W 14 -- 0 R/W 13 -- 0 R/W 12 -- 0 R/W H'FE12 H'FE13 Interrupt Controller Interrupt Controller 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA IRQ5 and IRQ4 sense control ISCRL Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial value : Read/Write : IRQ3 to IRQ0 sense control IRQnSCB IRQnSCA 0 1 0 1 0 1 Interrupt Request Generation Low level of IRQn input Falling edge of IRQn input Rising edge of IRQn input Rising and falling edges of IRQn input (n = 5 to 0) IER--IRQ Enable Register Bit : 7 -- Initial value : Read/Write : 0 R/W 6 -- 0 R/W 5 IRQ5E 0 R/W 4 H'FE14 3 IRQ3E 0 R/W 2 IRQ2E 0 R/W Interrupt Controller 1 IRQ1E 0 R/W 0 IRQ0E 0 R/W IRQ4E 0 R/W IRQn enable 0 IRQn interrupt is disabled 1 IRQn interrupt is enabled (n = 5 to 0) 888 ISR--IRQ Status Register Bit : 7 -- Initial value : Read/Write : 0 R/(W)* 6 -- 0 R/(W)* 5 IRQ5F 0 R/(W)* 4 IRQ4F 0 H'FE15 3 IRQ3F 0 R/(W)* 2 IRQ2F 0 R/(W)* Interrupt Controller 1 IRQ1F 0 R/(W)* 0 IRQ0F 0 R/(W)* R/(W)* IRQ5 to IRQ0 interrupt request status indication 0 [Clearing conditions] * Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag * When interrupt exception handling is executed when low-level detection is set (IRQnSCB = IRQnSCA = 0) and IRQn input is high * When IRQn interrupt exception handling is executed when falling, rising, or both-edge detection is set (IRQnSCB = 1 or IRQnSCA = 1) * When the DTC is activated by an IRQn interrupt, and the DISEL bit in MRB of the DTC is cleared to 0 1 [Setting conditions] * When IRQn input goes low when low-level detection is set (IRQnSCB = IRQnSCA = 0) * When a falling edge occurs in IRQn input when falling edge detection is set (IRQnSCB = 0, IRQnSCA = 1) * When a rising edge occurs in IRQn input when rising edge detection is set (IRQnSCB = 1, IRQnSCA = 0) * When a falling or rising edge occurs in IRQn input when bothedge detection is set (IRQnSCB = IRQnSCA = 1) (n = 5 to 0) Note: * Can only be written with 0 for flag clearing. 889 DTCER--DTC Enable Register Bit : 7 DTCE7 Initial value : Read/Write : 0 R/W 6 DTCE6 0 R/W 5 DTCE5 0 R/W 4 H'FE16 to H'FE1C 3 DTCE3 0 R/W 2 DTCE2 0 R/W 1 DTCE1 0 R/W 0 DTC DTCE4 0 R/W DTCE0 0 R/W DTC activation enable 0 DTC activation by interrupt is disabled [Clearing conditions] * When data transfer ends while the DISEL bit is 1 * When the specified number of transfers are completed 1 DTC activation by interrupt is enabled [Maintenance condition] When the DISEL bit is 0 and the specified number of transfers have not been completed Interrupt Sources and DTCER Bits Register DTCERA DTCERB DTCERD DTCERE DTCERF DTCERG Bit 7 IRQ0 -- -- -- RXI2 -- 6 IRQ1 ADI TGI2B -- -- TXI2 -- 5 IRQ2 TGI0A TGI3A TGI5A -- -- RM0 4 IRQ3 3 IRQ4 2 IRQ5 1 -- TGI1A TGI4A -- RXI1 -- -- 0 -- TGI1B TGI4B -- TXI1 -- -- TGI0B TGI0C TGI0D TGI3B TGI3C TGI3D TGI5B -- -- -- -- RXI0 -- -- -- TXI0 -- -- DTCERC TGI2A 890 DTVECR--DTC Vector Register Bit : 7 0 R/(W)*1 6 0 R/(W)*2 5 0 R/(W)*2 4 0 H'FE1F 3 0 R/(W)*2 2 0 R/(W)*2 1 0 R/(W)*2 DTC 0 0 R/(W)*2 SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 Initial value : Read/Write : R/(W)*2 Sets vector number for DTC software activation DTC software activation enable 0 DTC software activation is disabled [Clearing conditions] * When the DISEL bit is 0 and the specified number of transfers have not been completed * When 0 is written after a software-activated data transfer interrupt (SWDTEND) request has been sent to the CPU 1 DTC software activation is enabled [Maintenance conditions] * When data transfer ends while the DISEL bit is 1 * When the specified number of transfers are completed * During data transfer activated by software Notes: *1 Only 1 can be written to the SWDTE bit. *2 Bits DTVEC6 to DTVEC0 can be written to when SWDTE = 0. 891 PCR--PPG Output Control Register Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FE26 3 1 R/W 2 1 R/W 1 1 R/W 0 1 PPG G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value : Read/Write : R/W Group 0 compare match select 0 1 0 Compare match in TPU channel 0 1 Compare match in TPU channel 1 0 Compare match in TPU channel 2 1 Compare match in TPU channel 3 Group 1 compare match select 0 1 0 Compare match in TPU channel 0 1 Compare match in TPU channel 1 0 Compare match in TPU channel 2 1 Compare match in TPU channel 3 Group 2 compare match select 0 1 0 Compare match in TPU channel 0 1 Compare match in TPU channel 1 0 Compare match in TPU channel 2 1 Compare match in TPU channel 3 Group 3 compare match select 0 1 0 Compare match in TPU channel 0 1 Compare match in TPU channel 1 0 Compare match in TPU channel 2 1 Compare match in TPU channel 3 892 PMR--PPG Output Mode Register Bit : 7 G3INV Initial value : Read/Write : 1 R/W 6 G2INV 1 R/W 5 G1INV 1 R/W 4 G0INV 1 R/W H'FE27 3 G3NOV 0 R/W 2 G2NOV 0 R/W 1 G1NOV 0 R/W 0 PPG G0NOV 0 R/W Group 0 non-overlap 0 Normal operation in pulse output group 0 (output values updated at compare match A in the selected TPU channel) 1 Non-overlapping operation in pulse output group 0 (1 output and 0 output can be performed independently at compare match A and B in the selected TPU channel) Group 1 non-overlap 0 Normal operation in pulse output group 1 (output values updated at compare match A in the selected TPU channel) 1 Non-overlapping operation in pulse output group 1 (1 output and 0 output can be performed independently at compare match A and B in the selected TPU channel) Group 2 non-overlap 0 Normal operation in pulse output group 2 (output values updated at compare match A in the selected TPU channel) 1 Non-overlapping operation in pulse output group 2 (1 output and 0 output can be performed independently at compare match A and B in the selected TPU channel) Group 3 non-overlap 0 Normal operation in pulse output group 3 (output values updated at compare match A in the selected TPU channel) 1 Non-overlapping operation in pulse output group 3 (1 output and 0 output can be performed independently at compare match A and B in the selected TPU channel) Group 0 invert 0 Inverted output for pulse output group 0 (low-level output at pin for a 1 in PODRL) 1 Direct output for pulse output group 0 (high-level output at pin for a 1 in PODRL) Group 1 invert 0 Inverted output for pulse output group 1 (low-level output at pin for a 1 in PODRL) 1 Direct output for pulse output group 1 (high-level output at pin for a 1 in PODRL) Group 2 invert 0 Inverted output for pulse output group 2 (low-level output at pin for a 1 in PODRH) 1 Direct output for pulse output group 2 (high-level output at pin for a 1 in PODRH) Group 3 invert 0 Inverted output for pulse output group 3 (low-level output at pin for a 1 in PODRH) 1 Direct output for pulse output group 3 (high-level output at pin for a 1 in PODRH) 893 NDERH--Next Data Enable Register H Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FE28 3 0 R/W 2 0 R/W 1 0 R/W 0 PPG NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 Initial value : Read/Write : NDER8 0 R/W Next data enable 0 Pulse outputs PO15 to PO8 are disabled (transfer from NDR15-NDR8 to POD15-POD8 is disabled) 1 Pulse outputs PO15 to PO8 are enabled (transfer from NDR15-NDR8 to POD15-POD8 is enabled) NDERL--Next Data Enable Register L Bit : 7 NDER7 Initial value : Read/Write : 0 R/W 6 NDER6 0 R/W 5 NDER5 0 R/W 4 H'FE29 3 NDER3 0 R/W 2 NDER2 0 R/W 1 NDER1 0 R/W 0 PPG NDER4 0 R/W NDER0 0 R/W Next data enable 0 Pulse outputs PO7 to PO0 are disabled (transfer from NDR7-NDR0 to POD7-POD0 is disabled) 1 Pulse outputs PO7 to PO0 are enabled (transfer from NDR7-NDR0 to POD7-POD0 is enabled) 894 PODRH--Output Data Register H Bit : 7 POD15 Initial value : Read/Write : 0 R/(W)* 6 POD14 0 R/(W)* 5 POD13 0 R/(W)* 4 H'FE2A 3 POD11 0 R/(W)* 2 POD10 0 R/(W)* 1 POD9 0 R/(W)* 0 PPG POD12 0 R/(W)* POD8 0 R/(W)* Note: * A bit that has been set for pulse output by NDER is read-only. PODRL--Output Data Register L Bit : 7 POD7 Initial value : Read/Write : 0 R/(W)* 6 POD6 0 R/(W)* 5 POD5 0 R/(W)* 4 POD4 0 H'FE2B 3 POD3 0 R/(W)* 2 POD2 0 R/(W)* 1 POD1 0 R/(W)* 0 PPG POD0 0 R/(W)* R/(W)* Note: * A bit that has been set for pulse output by NDER is read-only. 895 NDRH--Next Data Register H NDRH--Next Data Register H When pulse output group output triggers are the same H'FE2C Bit : 7 NDR15 Initial value : Read/Write : H'FE2E Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 H'FE2C H'FE2E PPG PPG 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W NDR12 0 R/W 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- When pulse output group output triggers are different H'FE2C Bit : 7 NDR15 Initial value : Read/Write : H'FE2E Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Note: For details see section 11.2.4, Notes on NDR Access. 896 NDRL--Next Data Register L NDRL--Next Data Register L When pulse output group output triggers are the same H'FE2D Bit : 7 NDR7 Initial value : Read/Write : H'FE2F Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W H'FE2D H'FE2F PPG PPG 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- When pulse output group output triggers are different H'FE2D Bit : 7 NDR7 Initial value : Read/Write : H'FE2F Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Note: For details see section 11.2.4, Notes on NDR Access. 897 P1DDR--Port 1 Data Direction Register Bit : 7 0 W 6 0 W 5 0 W 4 0 W H'FE30 3 0 W 2 0 W 1 0 W 0 0 PPG P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value : Read/Write : W Bit-by-bit specification of input or output for port 1 pins PADDR--Port A Data Direction Register Bit : 7 -- Initial value : Read/Write : -- 6 -- -- 5 0 W H'FE39 Port A 4 3 2 1 0 * PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR * PA5DDR 0 W 0 W 0 W 0 W 0 W Undefined Undefined Specification of input or output for port A pins Note: * Reserved bits in the H8S/2626 Series. PBDDR--Port B Data Direction Register Bit : 7 0 W 6 0 W 5 0 W 4 0 W H'FE3A 3 0 W 2 0 W 1 0 W Port B 0 0 W PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Initial value : Read/Write : Specification of input or output for port B pins PCDDR--Port C Data Direction Register Bit : 7 0 W 6 0 W 5 0 W 4 0 W H'FE3B 3 0 W 2 0 W 1 0 W Port C 0 0 W PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR Initial value : Read/Write : Specification of input or output for port C pins 898 PDDDR--Port D Data Direction Register Bit : 7 0 W 6 0 W 5 0 W 4 0 W H'FE3C 3 0 W 2 0 W 1 0 W Port D 0 0 W PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR Initial value : Read/Write : Specification of input or output for port D pins PEDDR--Port E Data Direction Register Bit : 7 0 W 6 0 W 5 0 W 4 0 W H'FE3D 3 0 W 2 0 W 1 0 W Port E 0 0 W PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR Initial value : Read/Write : Specification of input or output for port E pins PFDDR--Port F Data Direction Register Bit : 7 6 5 4 H'FE3E 3 2 1 Port F 0 PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR Modes 4 to 6 Initial value : Read/Write : Mode 7 Initial value : Read/Write : 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 1 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Specification of input or output for port F pins 899 PAPCR--Port A MOS Pull-Up Control Register Bit : 7 -- Initial value : Read/Write : -- 6 -- -- 5 0 R/W H'FE40 Port A 4 3 2 1 0 * PA4PCR* PA3PCR PA2PCR PA1PCR PA0PCR PA5PCR 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Undefined Undefined Bit-by-bit control of port A MOS input pull-ups Note: * Reserved bits in the H8S/2626 Series. PBPCR--Port B MOS Pull-Up Control Register Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FE41 3 0 R/W 2 0 R/W 1 0 R/W Port B 0 0 R/W PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR Initial value : Read/Write : Bit-by-bit control of port B MOS input pull-ups PCPCR--Port C MOS Pull-Up Control Register Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FE42 3 0 R/W 2 0 R/W 1 0 R/W Port C 0 0 R/W PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR Initial value : Read/Write : Bit-by-bit control of port C MOS input pull-ups PDPCR--Port D MOS Pull-Up Control Register Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FE43 3 0 R/W 2 0 R/W 1 0 R/W Port D 0 0 R/W PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR Initial value : Read/Write : Bit-by-bit control of port D MOS input pull-ups 900 PEPCR--Port E MOS Pull-Up Control Register Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FE44 3 0 R/W 2 0 R/W 1 0 R/W Port E 0 0 R/W PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR Initial value : Read/Write : Bit-by-bit control of port E MOS input pull-ups PAODR--Port A Open Drain Control Register Bit : 7 -- Initial value : Read/Write : -- 6 -- -- H'FE47 Port A 5 4 3 2 1 0 * * PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Undefined Undefined PMOS on/off control for port A pins (PA5 to PA0) Note: * Reserved bits in the H8S/2626 Series. PBODR--Port B Open Drain Control Register Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FE48 3 0 R/W 2 0 R/W 1 0 R/W Port B 0 0 R/W PB7ODR PB6ODR PB5ODR PB4ODR PB3ODR PB2ODR PB1ODR PB0ODR Initial value : Read/Write : PMOS on/off control for port B pins (PB7 to PB0) PCODR--Port C Open Drain Control Register Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FE49 3 0 R/W 2 0 R/W 1 0 R/W Port C 0 0 R/W PC7ODR PC6ODR PC5ODR PC4ODR PC3ODR PC2ODR PC1ODR PC0ODR Initial value : Read/Write : PMOS on/off control for port C pins (PC7 to PC0) 901 TCR3--Timer Control Register 3 Bit : 7 CCLR2 Initial value : Read/Write : 0 R/W 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 CKEG1 0 R/W H'FE80 3 CKEG0 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W TPU3 0 TPSC0 0 R/W Timer prescaler 0 0 1 1 0 1 0 Internal clock: counts on o/1 1 Internal clock: counts on o/4 0 Internal clock: counts on o/16 1 Internal clock: counts on o/64 0 External clock: counts on TCLKA pin input 1 Internal clock: counts on o/1024 0 Internal clock: counts on o/256 1 Internal clock: counts on o/4096 Input clock edge select 0 0 Count at rising edge 1 Count at falling edge 1 -- Count at both edges Note: Internal clock edge selection is valid when the input clock is o/4 or slower. This setting is ignored if is o/1 is selected as the input clock. Counter clear 0 0 1 0 TCNT clearing disabled 1 TCNT cleared by TGRA compare match/input capture 0 TCNT cleared by TGRB compare match/input capture 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*1 1 0 1 0 TCNT clearing disabled 1 TCNT cleared by TGRC compare match/input capture*2 0 TCNT cleared by TGRD compare match/input capture*2 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*1 Notes: *1 Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. *2 When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. 902 TMDR3--Timer Mode Register 3 Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 BFB 0 R/W 4 BFA 0 R/W H'FE81 3 MD3 0 R/W Mode 0 0 0 1 1 0 1 1 * * 0 Normal operation 1 Reserved 0 PWM mode 1 1 PWM mode 2 2 MD2 0 R/W 1 MD1 0 R/W TPU3 0 MD0 0 R/W 0 Phase counting mode 1 1 Phase counting mode 2 0 Phase counting mode 3 1 Phase counting mode 4 *-- *: Don't care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2. Phase counting mode cannot be set for channel 3. In this case, 0 should always be written to MD2. Buffer operation setting A 0 TGRA operates normally 1 TGRA and TGRC used together for buffer operation Buffer operation setting B 0 TGRB operates normally 1 TGRB and TGRD used together for buffer operation 903 TIOR3H--Timer I/O Control Register 3H Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W TGR3A I/O control 0 0 0 0 TGR3A is output 1 compare 0 register 1 1 0 0 1 1 0 1 1 0 0 0 TGR3A is input 1 capture * register * H'FE82 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W 1 IOA1 0 R/W TPU3 0 IOA0 0 R/W Output disabled Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Capture input source is TIOCA3 pin Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT4 count-up/ source is channel count-down 4/count clock *: Don't care 1 1 1 * TGR3B I/O control 0 0 0 0 TGR3B is output 1 compare 0 register 1 1 0 0 1 1 0 1 1 0 0 0 TGR3B is input 1 capture * register * Capture input source is TIOCB3 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT4 count-up/ source is channel count-down*1 4/count clock Output disabled Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 1 * *: Don't care Note: *1 When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and o/1 is used as the TCNT4 count clock, this setting is invalid and input capture is not generated. 904 TIOR3L--Timer I/O Control Register 3L Bit : 7 IOD3 Initial value : Read/Write : 0 R/W 6 IOD2 0 R/W 5 IOD1 0 R/W 4 IOD0 0 R/W H'FE83 3 IOC3 0 R/W 2 IOC2 0 R/W 1 IOC1 0 R/W TPU3 0 IOC0 0 R/W TRG3C I/O control 0 0 0 0 TGR3C is output 1 compare 0 register 1 1 0 0 1 1 0 1 1 0 0 0 TGR3C is input 1 capture * register * Capture input source is TIOCC3 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT4 count-up/ source is channel count-down 4/count clock *: Don't care TGR3D I/O control 0 0 0 0 TGR3D is output 1 compare *2 0 register 1 1 0 0 1 1 0 1 1 0 0 0 TGR3D is input 1 capture *2 * register * Capture input source is TIOCD3 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT4 count-up/ source is channel count-down*1 4/count clock Output disabled Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match Output disabled Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 1 * 1 1 1 * *: Don't care Notes: *1 When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and o/1 is used as the TCNT4 count clock, this setting is invalid and input capture is not generated. *2 When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. 905 TIER3--Timer Interrupt Enable Register 3 Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 -- 1 -- 5 -- 0 -- 4 TCIEV 0 R/W H'FE84 3 TGIED 0 R/W 2 TGIEC 0 R/W 1 TGIEB 0 R/W TPU3 0 TGIEA 0 R/W TGR interrupt enable A 0 Interrupt requests (TGIA) by TGFA bit disabled 1 Interrupt requests (TGIA) by TGFA bit enabled TGR interrupt enable B 0 Interrupt requests (TGIB) by TGFB bit disabled 1 Interrupt requests (TGIB) by TGFB bit enabled TGR interrupt enable C 0 Interrupt requests (TGIC) by TGFC bit disabled 1 Interrupt requests (TGIC) by TGFC bit enabled TGR interrupt enable D 0 Interrupt requests (TGID) by TGFD bit disabled 1 Interrupt requests (TGID) by TGFD bit enabled Overflow interrupt enable 0 Interrupt requests (TCIV) by TCFV disabled 1 Interrupt requests (TCIV) by TCFV enabled A/D conversion start request enable 0 A/D conversion start request generation disabled 1 A/D conversion start request generation enabled 906 TSR3--Timer Status Register 3 Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 -- 0 -- 4 TCFV 0 R/(W)* H'FE85 3 TGFD 0 R/(W)* 2 TGFC 0 R/(W)* 1 TGFB 0 R/(W)* TPU3 0 TGFA 0 R/(W)* TGRA input capture/output compare flag 0 [Clearing conditions] * When DTC is activated by TGIA interrupt, and DISEL bit in DTC's MRB is 0 * When 0 is written to TGFA after reading TGFA = 1 1 [Setting conditions] * When TCNT = TGRA while TGRA is functioning as output compare register * When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register TGRB input capture/output compare flag 0 [Clearing conditions] * When DTC is activated by TGIB interrupt, and DISEL bit in DTC's MRB is 0 * When 0 is written to TGFB after reading TGFB = 1 1 [Setting conditions] * When TCNT = TGRB while TGRB is functioning as output compare register * When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register TGRC input capture/output compare flag 0 [Clearing conditions] * When DTC is activated by TGIC interrupt, and DISEL bit in DTC's MRB is 0 * When 0 is written to TGFC after reading TGFC = 1 1 [Setting conditions] * When TCNT = TGRC while TGRC is functioning as output compare register * When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register TGRD input capture/output compare flag 0 [Clearing conditions] * When DTC is activated by TGID interrupt, and DISEL bit in DTC's MRB is 0 * When 0 is written to TGFD after reading TGFD = 1 1 [Setting conditions] * When TCNT = TGRD while TGRD is functioning as output compare register * When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register Overflow flag 0 [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000) Note: * Can only be written with 0 for flag clearing. 907 TCNT3--Timer Counter 3 Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 H'FE86 7 0 6 0 5 0 4 0 3 0 2 0 1 0 TPU3 0 0 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up-counter TGR3A--Timer General Register 3A TGR3B--Timer General Register 3B TGR3C--Timer General Register 3C TGR3D--Timer General Register 3D Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 H'FE88 H'FE8A H'FE8C H'FE8E 7 1 6 1 5 1 4 1 3 1 2 1 1 1 TPU3 TPU3 TPU3 TPU3 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 908 TCR4--Timer Control Register 4 Bit : 7 -- Initial value : Read/Write : 0 -- 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 CKEG1 0 R/W H'FE90 3 CKEG0 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W TPU4 0 TPSC0 0 R/W Time prescaler 0 0 1 1 0 1 0 Internal clock: counts on o/1 1 Internal clock: counts on o/4 0 Internal clock: counts on o/16 1 Internal clock: counts on o/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKC pin input 0 Internal clock: counts on o/1024 1 Counts on TCNT5 overflow/underflow Note: This setting is invalid when channel 4 is in phase counting mode. Input clock edge select 0 0 Count at rising edge 1 Count at falling edge 1 -- Count at both edges Note: This setting is invalid when channel 4 is in phase counting mode. This setting is ignored if the input clock is o/1, or when overflow/underflow of another channel is selected. Counter clear 0 0 1 0 TCNT clearing disabled 1 TCNT cleared by TGRA compare match/input capture 0 TCNT cleared by TGRB compare match/input capture 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation* Note: * Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 909 TMDR4--Timer Mode Register 4 Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 -- 0 -- 4 -- 0 -- H'FE91 3 MD3 0 R/W Mode 0 0 0 1 1 0 1 1 * * 0 Normal operation 1 Reserved 0 PWM mode 1 1 PWM mode 2 2 MD2 0 R/W 1 MD1 0 R/W TPU4 0 MD0 0 R/W 0 Phase counting mode 1 1 Phase counting mode 2 0 Phase counting mode 3 1 Phase counting mode 4 *-- *: Don't care Note: MD3 is a reserved bit. In a write, it should always be written with 0. 910 TIOR4--Timer I/O Control Register 4 Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W TGR4A I/O control 0 0 0 0 TGR4A is output 1 compare 0 register 1 1 0 0 1 1 0 1 1 0 0 0 TGR4A is input 1 capture * register * H'FE92 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W 1 IOA1 0 R/W TPU4 0 IOA0 0 R/W Output disabled Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Capture input source is TIOCA4 pin Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at generation of source is TGR3A TGR3A compare match/input compare match/ capture input capture *: Don't care 1 1 1 * TGR4B I/O control 0 0 0 0 TGR4B is output 1 compare 0 register 1 1 0 0 1 1 0 1 1 0 0 0 TGR4B is input 1 capture * register * Capture input source is TIOCB4 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at generation of source is TGR3C TGR3C compare match/input compare match/ capture input capture *: Don't care Output disabled Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 1 * 911 TIER4--Timer Interrupt Enable Register 4 Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 -- 1 -- 5 TCIEU 0 R/W 4 TCIEV 0 R/W H'FE94 3 -- 0 -- 2 -- 0 -- 1 TGIEB 0 R/W TPU4 0 TGIEA 0 R/W TGIA interrupt enable 0 Interrupt requests (TGIA) by TGFA bit disabled 1 Interrupt requests (TGIA) by TGFA bit enabled TGIB interrupt enable 0 Interrupt requests (TGIB) by TGFB bit disabled 1 Interrupt requests (TGIB) by TGFB bit enabled Overflow interrupt enable 0 Interrupt requests (TCIV) by TCFV disabled 1 Interrupt requests (TCIV) by TCFV enabled Underflow interrupt enable 0 Interrupt requests (TCIU) by TCFU disabled 1 Interrupt requests (TCIU) by TCFU enabled A/D conversion start request enable 0 A/D conversion start request generation disabled 1 A/D conversion start request generation enabled 912 TSR4--Timer Status Register 4 Bit : 7 TCFD Initial value : Read/Write : 1 R 6 -- 1 -- 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* H'FE95 3 -- 0 -- 2 -- 0 -- 1 TGFB 0 R/(W)* TPU4 0 TGFA 0 R/(W)* TGRA input capture/output compare flag [Clearing conditions] * When DTC is activated by TGIA interrupt, and DISEL bit in DTC's MRB is 0 * When 0 is written to TGFA after reading TGFA = 1 1 [Setting conditions] * When TCNT = TGRA while TGRA is functioning as output compare register * When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register TGRB input capture/output compare flag 0 [Clearing conditions] * When DTC is activated by TGIB interrupt, and DISEL bit in DTC's MRB is 0 * When 0 is written to TGFB after reading TGFB = 1 1 [Setting conditions] * When TCNT = TGRB while TGRB is functioning as output compare register * When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register Overflow flag 0 [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000) Underflow flag 0 [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) Counter direction flag 0 TCNT counts down 1 TCNT counts up Note: * Can only be written with 0 for flag clearing. 0 913 TCNT4--Timer Counter 4 Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 H'FE96 7 0 6 0 5 0 4 0 3 0 2 0 1 0 TPU4 0 0 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter. TGR4A--Timer General Register 4A TGR4B--Timer General Register 4B Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 H'FE98 H'FE9A 7 1 6 1 5 1 4 1 3 1 2 1 1 1 TPU4 TPU4 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 914 TCR5--Timer Control Register 5 Bit : 7 -- Initial value : Read/Write : 0 -- 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 CKEG1 0 R/W H'FEA0 3 CKEG0 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W TPU5 0 TPSC0 0 R/W Time prescaler 0 0 1 1 0 1 0 Internal clock: counts on o/1 1 Internal clock: counts on o/4 0 Internal clock: counts on o/16 1 Internal clock: counts on o/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKC pin input 0 Internal clock: counts on o/256 1 External clock: counts on TCLKD pin input Note: This setting is invalid when channel 5 is in phase counting mode. Input clock edge select 0 0 Count at rising edge 1 Count at falling edge 1 -- Count at both edges Note: This setting is invalid when channel 5 is in phase counting mode, and also when o/1 is selected as the input clock. Counter clear 0 0 1 0 TCNT clearing disabled 1 TCNT cleared by TGRA compare match/input capture 0 TCNT cleared by TGRB compare match/input capture 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation* Note: * Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 915 TMDR5--Timer Mode Register 5 Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 -- 0 -- 4 -- 0 -- H'FEA1 3 MD3 0 R/W Mode 0 0 0 1 1 0 1 1 * * 0 Normal operation 1 Reserved 0 PWM mode 1 1 PWM mode 2 2 MD2 0 R/W 1 MD1 0 R/W TPU5 0 MD0 0 R/W 0 Phase counting mode 1 1 Phase counting mode 2 0 Phase counting mode 3 1 Phase counting mode 4 *-- *: Don't care Note: MD3 is a reserved bit. In a write, it should always be written with 0. 916 TIOR5--Timer I/O Control Register 5 Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W TGR5A I/O control 0 0 0 0 TGR5A is output 1 compare 0 register 1 1 0 0 1 1 0 1 1 * 0 0 TGR5A is input 1 capture * register H'FEA2 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W 1 IOA1 0 R/W TPU5 0 IOA0 0 R/W Output disabled Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Capture input source is TIOCA5 pin Input capture at rising edge Input capture at falling edge Input capture at both edges *: Don't care 1 1 TGR5B I/O control 0 0 0 0 TGR5B is output 1 compare 0 register 1 1 0 0 1 1 0 1 1 * 0 0 TGR5B is input 1 capture * register Output disabled Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Capture input source is TIOCB5 pin Input capture at rising edge Input capture at falling edge Input capture at both edges *: Don't care 1 1 917 TIER5--Timer Interrupt Enable Register 5 Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 -- 1 -- 5 TCIEU 0 R/W 4 TCIEV 0 R/W H'FEA4 3 -- 0 -- 2 -- 0 -- 1 TGIEB 0 R/W TPU5 0 TGIEA 0 R/W TGIA interrupt enable 0 Interrupt requests (TGIA) by TGFA bit disabled 1 Interrupt requests (TGIA) by TGFA bit enabled TGIB interrupt enable 0 Interrupt requests (TGIB) by TGFB bit disabled 1 Interrupt requests (TGIB) by TGFB bit enabled Overflow interrupt enable 0 Interrupt requests (TCIV) by TCFV disabled 1 Interrupt requests (TCIV) by TCFV enabled Underflow interrupt enable 0 Interrupt requests (TCIU) by TCFU disabled 1 Interrupt requests (TCIU) by TCFU enabled A/D conversion start request enable 0 A/D conversion start request generation disabled 1 A/D conversion start request generation enabled 918 TSR5--Timer Status Register 5 Bit : 7 TCFD Initial value : Read/Write : 1 R 6 -- 1 -- 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* H'FEA5 3 -- 0 -- 2 -- 0 -- 1 TGFB 0 R/(W)* 0 TPU5 TGFA 0 R/(W)* TGRA input capture/output compare flag 0 [Clearing conditions] * When DTC is activated by TGIA interrupt, and DISEL bit in DTC's MRB is 0 * When 0 is written to TGFA after reading TGFA = 1 1 [Setting conditions] * When TCNT = TGRA while TGRA is functioning as output compare register * When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register TGRB input capture/output compare flag 0 [Clearing conditions] * When DTC is activated by TGIB interrupt, and DISEL bit in DTC's MRB is 0 * When 0 is written to TGFB after reading TGFB = 1 1 [Setting conditions] * When TCNT = TGRB while TGRB is functioning as output compare register * When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register Overflow flag 0 [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000) Underflow flag 0 [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) Counter direction flag 0 TCNT counts down 1 TCNT counts up Note: * Can only be written with 0 for flag clearing. 919 TCNT5--Timer Counter 5 Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 H'FEA6 7 0 6 0 5 0 4 0 3 0 2 0 1 0 TPU5 0 0 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter. TGR5A--Timer General Register 5A TGR5B--Timer General Register 5B Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 H'FEA8 H'FEAA 7 1 6 1 5 1 4 1 3 1 2 1 1 1 TPU5 TPU5 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TSTR--Timer Start Register Bit : 7 -- Initial value : Read/Write : 0 -- 6 -- 0 -- 5 CST5 0 R/W 4 CST4 0 R/W H'FEB0 3 CST3 0 R/W 2 CST2 0 R/W 1 CST1 0 R/W 0 TPU CST0 0 R/W Counter start 0 TCNTn count operation is stopped 1 TCNTn performs count operation (n = 5 to 0) Note: If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 920 TSYR--Timer Sync Register Bit : 7 -- Initial value : Read/Write : 0 -- 6 -- 0 -- 5 SYNC5 0 R/W 4 SYNC4 0 R/W H'FEB1 3 SYNC3 0 R/W 2 SYNC2 0 R/W 1 SYNC1 0 R/W 0 TPU SYNC0 0 R/W Timer synchronization 0 TCNTn operates independently (TCNT presetting/clearing is unrelated to other channels) 1 TCNTn performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible (n = 5 to 0) Notes: 1. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. 2. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source must also be set by means of bits CCLR2 to CCLR0 in TCR. 921 IPRA--Interrupt Priority Register A IPRB--Interrupt Priority Register B IPRC--Interrupt Priority Register C IPRD--Interrupt Priority Register D IPRE--Interrupt Priority Register E IPRF--Interrupt Priority Register F IPRG--Interrupt Priority Register G IPRH--Interrupt Priority Register H IPRI--Interrupt Priority Register I IPRJ--Interrupt Priority Register J IPRK--Interrupt Priority Register K IPRM--Interrupt Priority Register M Bit : 7 -- Initial value : Read/Write : 0 -- 6 IPR6 1 R/W 5 IPR5 1 R/W 4 IPR4 1 R/W H'FEC0 H'FEC1 H'FEC2 H'FEC3 H'FEC4 H'FEC5 H'FEC6 H'FEC7 H'FEC8 H'FEC9 H'FECA H'FECC 3 -- 0 -- 2 IPR2 1 R/W Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller 1 IPR1 1 R/W 0 IPR0 1 R/W Interrupt Sources and IPR Settings Register IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK IPRM IRQ0 IRQ2 IRQ3 --*1 WDT0 PC break TPU channel 0 TPU channel 2 TPU channel 4 --*1 --*1 SCI channel 1 HCAN Bits 6 to 4 IRQ1 IRQ4 IRQ5 DTC --*1 A/D converter, WDT1*2 TPU channel 1 TPU channel 3 TPU channel 5 --*1 SCI channel 0 SCI channel 2 --*1 2 to 0 Notes: *1 These bits are reserved. They are always read as 1 and cannot be modified. *2 Valid only in the H8S/2626 Series. 922 ABWCR--Bus Width Control Register Bit : 7 ABW7 Modes 5 to 7 Initial value : Read/Write : Mode 4 Initial value : Read/Write : 0 R/W 0 R/W 0 R/W 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 6 ABW6 5 ABW5 4 ABW4 H'FED0 3 ABW3 1 R/W 0 R/W 2 ABW2 1 R/W 0 R/W Bus Controller 1 ABW1 1 R/W 0 R/W 0 ABW0 1 R/W 0 R/W Area 7 to 0 bus width control 0 Area n is designated for 16-bit access 1 Area n is designated for 8-bit access (n = 7 to 0) ASTCR--Access State Control Register Bit : 7 AST7 Initial value : Read/Write : 1 R/W 6 AST6 1 R/W 5 AST5 1 R/W 4 AST4 1 R/W H'FED1 3 AST3 1 R/W 2 AST2 1 R/W Bus Controller 1 AST1 1 R/W 0 AST0 1 R/W Area 7 to 0 access state control 0 Area n is designated for 2-state access Wait state insertion in area n external space access is disabled 1 Area n is designated for 3-state access Wait state insertion in area n external space access is enabled (n = 7 to 0) 923 WCRH--Wait Control Register H Bit : 7 W71 Initial value : Read/Write : 1 R/W 6 W70 1 R/W 5 W61 1 R/W 4 W60 1 R/W H'FED2 3 W51 1 R/W 2 W50 1 R/W 1 Bus Controller 0 W40 1 R/W W41 1 R/W Area 4 wait control 0 1 0 Program wait not inserted 1 1 program wait state inserted 0 2 program wait states inserted 1 3 program wait states inserted Area 5 wait control 0 1 0 Program wait not inserted 1 1 program wait state inserted 0 2 program wait states inserted 1 3 program wait states inserted Area 6 wait control 0 1 0 Program wait not inserted 1 1 program wait state inserted 0 2 program wait states inserted 1 3 program wait states inserted Area 7 wait control 0 1 0 Program wait not inserted 1 1 program wait state inserted 0 2 program wait states inserted 1 3 program wait states inserted 924 WCRL--Wait Control Register L Bit : 7 W31 Initial value : Read/Write : 1 R/W 6 W30 1 R/W 5 W21 1 R/W 4 W20 1 R/W H'FED3 3 W11 1 R/W 2 W10 1 R/W 1 Bus Controller 0 W00 1 R/W W01 1 R/W Area 0 wait control 0 1 0 Program wait not inserted 1 1 program wait state inserted 0 2 program wait states inserted 1 3 program wait states inserted Area 1 wait control 0 1 0 Program wait not inserted 1 1 program wait state inserted 0 2 program wait states inserted 1 3 program wait states inserted Area 2 wait control 0 1 0 Program wait not inserted 1 1 program wait state inserted 0 2 program wait states inserted 1 3 program wait states inserted Area 3 wait control 0 1 0 Program wait not inserted 1 1 program wait state inserted 0 2 program wait states inserted 1 3 program wait states inserted 925 BCRH--Bus Control Register H Bit : 7 ICIS1 Initial value : Read/Write : 1 R/W 6 ICIS0 1 R/W 5 0 R/W 4 1 R/W H'FED4 3 0 R/W 2 -- 0 R/W Bus Controller 1 -- 0 R/W 0 -- 0 R/W BRSTRM BRSTS1 BRSTS0 Burst cycle select 0 0 Max. 4 words in burst access 1 Max. 8 words in burst access Burst cycle select 1 0 Burst cycle comprises 1 state 1 Burst cycle comprises 2 states Area 0 burst ROM enable 0 Basic bus interface 1 Burst ROM interface Idle cycle insert 0 0 Idle cycle not inserted in case of successive external read and external write cycles 1 Idle cycle inserted in case of successive external read and external write cycles Idle cycle insert 1 0 Idle cycle not inserted in case of successive external read cycles in different areas 1 Idle cycle inserted in case of successive external read cycles in different areas 926 BCRL--Bus Control Register L Bit : 7 BRLE Initial value : Read/Write : 0 R/W 6 BREQOE 0 R/W 5 -- 0 -- 4 -- 0 R/W H'FED5 3 -- 1 R/W 2 -- 0 R/W 1 Bus Controller 0 WAITE 0 R/W WDBE 0 R/W WAIT pin enable 0 Wait input by WAIT pin disabled 1 Wait input by WAIT pin enabled Write data buffer enable 0 Write data buffer function not used 1 Write data buffer function used BREQO pin enable 0 BREQO output disabled 1 BREQO output enabled Bus release enable 0 External bus release disabled 1 External bus release enabled 927 RAMER--RAM Emulation Register*1 Bit : 7 -- Initial value : Read/Write : 0 R 6 -- 0 R 5 -- 0 R/W 4 -- 0 R/W H'FEDB 3 RAMS 0 R/W 2 RAM2 0 R/W 1 RAM1 0 R/W ROM 0 RAM0 0 R/W Flash memory area select RAM select 0 Emulation not selected Program/erase-protection of all flash memory blocks is disabled 1 Emulation selected Program/erase-protection of all flash memory blocks is enabled Flash memory area divisions Addresses H'FFD000-H'FFDFFF H'000000-H'000FFF H'001000-H'001FFF H'002000-H'002FFF H'003000-H'003FFF H'004000-H'004FFF H'005000-H'005FFF H'006000-H'006FFF H'007000-H'007FFF Note: Block Name RAM area 4 kbytes EB0 (4 kbytes) EB1 (4 kbytes) EB2 (4 kbytes) EB3 (4 kbytes) EB4 (4 kbytes) EB5 (4 kbytes) EB6 (4 kbytes) EB7 (4 kbytes) RAMS RAM2 RAM1 RAM0 0 1 1 1 1 1 1 1 1 * 0 0 0 0 1 1 1 1 * 0 0 1 1 0 0 1 1 * 0 1 0 1 0 1 0 1 *: Don't care *1 This register is present only in the F-ZTAT version; it is not provided in the mask ROM version. P1DR--Port 1 Data Register Bit : 7 P17DR Initial value : Read/Write : 0 R/W 6 P16DR 0 R/W 5 P15DR 0 R/W 4 H'FF00 3 P13DR 0 R/W 2 P12DR 0 R/W 1 P11DR 0 R/W Port 1 0 P10DR 0 R/W P14DR 0 R/W Stores output data for port 1 pins (P17 to P10) 928 PADR--Port A Data Register Bit : 7 -- Initial value : Read/Write : -- 6 -- -- 5 0 R/W H'FF09 4 3 * PA4DR* PA3DR PA5DR 0 R/W 0 R/W 2 PA2DR 0 R/W 1 PA1DR 0 R/W Port A 0 PA0DR 0 R/W Undefined Undefined Stores output data for port A pins (PA5 to PA0) Note: * Reserved bits in the H8S/2626 Series. PBDR--Port B Data Register Bit : 7 PB7DR Initial value : Read/Write : 0 R/W 6 PB6DR 0 R/W 5 PB5DR 0 R/W 4 H'FF0A 3 PB3DR 0 R/W 2 PB2DR 0 R/W 1 PB1DR 0 R/W Port B 0 PB0DR 0 R/W PB4DR 0 R/W Stores output data for port B pins (PB7 to PB0) PCDR--Port C Data Register Bit : 7 PC7DR Initial value : Read/Write : 0 R/W 6 PC6DR 0 R/W 5 PC5DR 0 R/W 4 H'FF0B 3 PC3DR 0 R/W 2 PC2DR 0 R/W 1 PC1DR 0 R/W Port C 0 PC0DR 0 R/W PC4DR 0 R/W Stores output data for port C pins (PC7 to PC0) PDDR--Port D Data Register Bit : 7 PD7DR Initial value : Read/Write : 0 R/W 6 PD6DR 0 R/W 5 PD5DR 0 R/W 4 H'FF0C 3 PD3DR 0 R/W 2 PD2DR 0 R/W 1 PD1DR 0 R/W Port D 0 PD0DR 0 R/W PD4DR 0 R/W Stores output data for port D pins (PD7 to PD0) 929 PEDR--Port E Data Register Bit : 7 PE7DR Initial value : Read/Write : 0 R/W 6 PE6DR 0 R/W 5 PE5DR 0 R/W 4 H'FF0D 3 PE3DR 0 R/W 2 PE2DR 0 R/W 1 PE1DR 0 R/W Port E 0 PE0DR 0 R/W PE4DR 0 R/W Stores output data for port E pins (PE7 to PE0) PFDR--Port F Data Register Bit : 7 -- Initial value : Read/Write : 0 R/W 6 PF6DR 0 R/W 5 PF5DR 0 R/W 4 H'FF0E 3 PF3DR 0 R/W 2 PF2DR 0 R/W 1 PF1DR 0 R/W Port F 0 PF0DR 0 R/W PF4DR 0 R/W Stores output data for port F pins (PF6 to PF0) 930 TCR0--Timer Control Register 0 Bit : 7 CCLR2 Initial value : Read/Write : 0 R/W 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 CKEG1 0 R/W H'FF10 3 CKEG0 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W TPU0 0 TPSC0 0 R/W Time prescaler 0 0 1 1 0 1 0 Internal clock: counts on o/1 1 Internal clock: counts on o/4 0 Internal clock: counts on o/16 1 Internal clock: counts on o/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 0 External clock: counts on TCLKC pin input 1 External clock: counts on TCLKD pin input Input clock edge select 0 0 Count at rising edge 1 Count at falling edge 1 -- Count at both edges Note: Internal clock edge selection is valid when the input clock is o/4 or slower. This setting is ignored if is o/1 is selected as the input clock. Counter clear 0 0 1 0 TCNT clearing disabled 1 TCNT cleared by TGRA compare match/input capture 0 TCNT cleared by TGRB compare match/input capture 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*1 1 0 1 0 TCNT clearing disabled 1 TCNT cleared by TGRC compare match/input capture*2 0 TCNT cleared by TGRD compare match/input capture*2 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*1 Notes: *1 Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. *2 When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. 931 TMDR0--Timer Mode Register 0 Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 BFB 0 R/W 4 BFA 0 R/W H'FF11 3 MD3 0 R/W Mode 0 0 0 1 1 0 1 1 * * 0 Normal operation 1 Reserved 0 PWM mode 1 1 PWM mode 2 2 MD2 0 R/W 1 MD1 0 R/W TPU0 0 MD0 0 R/W 0 Phase counting mode 1 1 Phase counting mode 2 0 Phase counting mode 3 1 Phase counting mode 4 *-- *: Don't care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2. Phase counting mode cannot be set for channel 0. In this case, 0 should always be written to MD2. Buffer operation setting A 0 TGRA operates normally 1 TGRA and TGRC used together for buffer operation Buffer operation setting B 0 TGRB operates normally 1 TGRB and TGRD used together for buffer operation 932 TIOR0H--Timer I/O Control Register 0H Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W TGR0A I/O control 0 0 0 0 TGR0A is output 1 compare 0 register 1 1 0 0 1 1 0 1 1 0 0 0 TGR0A is input 1 capture * register * H'FF12 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W 1 IOA1 0 R/W TPU0 0 IOA0 0 R/W Output disabled Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Capture input source is TIOCA0 pin Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT1count-up/ source is channel count-down 1/count clock *: Don't care 1 1 1 * TGR0B I/O control 0 0 0 0 TGR0B is output 1 compare 0 register 1 1 0 0 1 1 0 1 1 0 0 0 TGR0B is input 1 capture * register * Capture input source is TIOCB0 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT1 count-up/ source is channel count-down*1 1/count clock *: Don't care Note: *1 When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and o/1 is used as the TCNT1 count clock, this setting is invalid and input capture is not generated. Output disabled Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 1 * 933 TIOR0L--Timer I/O Control Register 0L Bit : 7 IOD3 Initial value : Read/Write : 0 R/W 6 IOD2 0 R/W 5 IOD1 0 R/W 4 IOD0 0 R/W H'FF13 3 IOC3 0 R/W 2 IOC2 0 R/W 1 IOC1 0 R/W TPU0 0 IOC0 0 R/W TGR0C I/O control 0 0 0 0 TGR0C is output 1 compare 0 register 1 1 0 0 1 1 0 1 1 0 0 0 TGR0C is input 1 capture * register * Capture input source is TIOCC0 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT1 count-up/ source is channel count-down 1/count clock *: Don't care TGR0D I/O control 0 0 0 0 TGR0D is output 1 compare 0 register 1 1 0 0 1 1 0 1 1 0 0 0 TGR0D is input 1 capture * register * Capture input source is TIOCD0 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT1 count-up/ source is channel count-down*1 1/count clock Output disabled Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match Output disabled Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 1 * 1 1 1 * *: Don't care Note: *1 When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and o/1 is used as the TCNT1 count clock, this setting is invalid and input capture is not generated. Note: When TGR0C or TGR0D is designated for buffer operation, this setting is invalid and the register operates as a buffer register. 934 TIER0--Timer Interrupt Enable Register 0 Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 -- 1 -- 5 -- 0 -- 4 TCIEV 0 R/W H'FF14 3 TGIED 0 R/W 2 TGIEC 0 R/W 1 TGIEB 0 R/W TPU0 0 TGIEA 0 R/W TGR interrupt enable A 0 Interrupt requests (TGIA) by TGFA bit disabled 1 Interrupt requests (TGIA) by TGFA bit enabled TGR interrupt enable B 0 Interrupt requests (TGIB) by TGFB bit disabled 1 Interrupt requests (TGIB) by TGFB bit enabled TGR interrupt enable C 0 Interrupt requests (TGIC) by TGFC bit disabled 1 Interrupt requests (TGIC) by TGFC bit enabled TGR interrupt enable D 0 Interrupt requests (TGID) by TGFD bit disabled 1 Interrupt requests (TGID) by TGFD bit enabled Overflow interrupt enable 0 Interrupt requests (TCIV) by TCFV disabled 1 Interrupt requests (TCIV) by TCFV enabled A/D conversion start request enable 0 A/D conversion start request generation disabled 1 A/D conversion start request generation enabled 935 TSR0--Timer Status Register 0 Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 -- 0 -- 4 TCFV 0 R/(W)* H'FF15 3 TGFD 0 R/(W)* 2 TGFC 0 R/(W)* 1 TGFB 0 R/(W)* TPU0 0 TGFA 0 R/(W)* TGRA input capture/output compare flag 0 [Clearing conditions] * When DTC is activated by TGIA interrupt, and DISEL bit in DTC's MRB is 0 * When 0 is written to TGFA after reading TGFA = 1 1 [Setting conditions] * When TCNT = TGRA while TGRA is functioning as output compare register * When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register TGRB input capture/output compare flag 0 [Clearing conditions] * When DTC is activated by TGIB interrupt, and DISEL bit in DTC's MRB is 0 * When 0 is written to TGFB after reading TGFB = 1 1 [Setting conditions] * When TCNT = TGRB while TGRB is functioning as output compare register * When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register TGRC input capture/output compare flag 0 [Clearing conditions] * When DTC is activated by TGIC interrupt, and DISEL bit in DTC's MRB is 0 * When 0 is written to TGFC after reading TGFC = 1 1 [Setting conditions] * When TCNT = TGRC while TGRC is functioning as output compare register * When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register TGRD input capture/output compare flag 0 [Clearing conditions] * When DTC is activated by TGID interrupt, and DISEL bit in DTC's MRB is 0 * When 0 is written to TGFD after reading TGFD = 1 1 [Setting conditions] * When TCNT = TGRD while TGRD is functioning as output compare register * When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register Overflow flag 0 [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000) Note: * Can only be written with 0 for flag clearing. 936 TCNT0--Timer Counter 0 Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 H'FF16 7 0 6 0 5 0 4 0 3 0 2 0 1 0 TPU0 0 0 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up-counter TGR0A--Timer General Register 0A TGR0B--Timer General Register 0B TGR0C--Timer General Register 0C TGR0D--Timer General Register 0D Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 H'FF18 H'FF1A H'FF1C H'FF1E 7 1 6 1 5 1 4 1 3 1 2 1 1 1 TPU0 TPU0 TPU0 TPU0 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 937 TCR1--Timer Control Register 1 Bit : 7 -- Initial value : Read/Write : 0 -- 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 CKEG1 0 R/W H'FF20 3 CKEG0 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W TPU1 0 TPSC0 0 R/W Time prescaler 0 0 1 1 0 1 0 Internal clock: counts on o/1 1 Internal clock: counts on o/4 0 Internal clock: counts on o/16 1 Internal clock: counts on o/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 0 Internal clock: counts on o/256 1 Counts on TCNT2 overflow/underflow Note: This setting is invalid when channel 1 is in phase counting mode. Input clock edge select 0 0 Count at rising edge 1 Count at falling edge 1 -- Count at both edges Note: This setting is invalid when channel 1 is in phase counting mode, and also when o/1 or overflow/underflow of another channel is selected as the input clock. Counter clear 0 1 0 TCNT clearing disabled 1 TCNT cleared by TGRA compare match/input capture 0 TCNT cleared by TGRB compare match/input capture 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation* Note: * Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 938 TMDR1--Timer Mode Register 1 Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 -- 0 -- 4 -- 0 -- H'FF21 3 MD3 0 R/W Mode 0 0 0 1 1 0 1 1 * * 0 Normal operation 1 Reserved 0 PWM mode 1 1 PWM mode 2 2 MD2 0 R/W 1 MD1 0 R/W TPU1 0 MD0 0 R/W 0 Phase counting mode 1 1 Phase counting mode 2 0 Phase counting mode 3 1 Phase counting mode 4 *-- *: Don't care Note: MD3 is a reserved bit. In a write, it should always be written with 0. 939 TIOR1--Timer I/O Control Register 1 Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W TGR1A I/O control 0 0 0 0 TGR1A is output 1 compare 0 register 1 1 0 0 1 1 0 1 1 0 0 0 TGR1A is input 1 capture * register * H'FF22 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W 1 IOA1 0 R/W TPU1 0 IOA0 0 R/W Output disabled Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Capture input source is TIOCA1 pin Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at generation of source is TGR0A channel 0/TGR0A compare match/ compare match/ input capture input capture *: Don't care 1 1 1 * TGR1B I/O control 0 0 0 0 TGR1B is output 1 compare 0 register 1 1 0 0 1 1 0 1 1 0 0 0 TGR1B is input 1 capture * register * Capture input source is TIOCB1 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at generation of source is TGR0C TGR0C compare match/input compare match/ capture input capture *: Don't care Output disabled Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 1 * 940 TIER1--Timer Interrupt Enable Register 1 Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 -- 1 -- 5 TCIEU 0 R/W 4 TCIEV 0 R/W H'FF24 3 -- 0 -- 2 -- 0 -- 1 TGIEB 0 R/W TPU1 0 TGIEA 0 R/W TGIA interrupt enable 0 Interrupt requests (TGIA) by TGFA bit disabled 1 Interrupt requests (TGIA) by TGFA bit enabled TGIB interrupt enable 0 Interrupt requests (TGIB) by TGFB bit disabled 1 Interrupt requests (TGIB) by TGFB bit enabled Overflow interrupt enable 0 Interrupt requests (TCIV) by TCFV disabled 1 Interrupt requests (TCIV) by TCFV enabled Underflow interrupt enable 0 Interrupt requests (TCIU) by TCFU disabled 1 Interrupt requests (TCIU) by TCFU enabled A/D conversion start request enable 0 A/D conversion start request generation disabled 1 A/D conversion start request generation enabled 941 TSR1--Timer Status Register 1 Bit : 7 TCFD Initial value : Read/Write : 1 R 6 -- 1 -- 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* H'FF25 3 -- 0 -- 2 -- 0 -- 1 TGFB 0 R/(W)* TPU1 0 TGFA 0 R/(W)* TGRA input capture/output compare flag 0 [Clearing conditions] * When DTC is activated by TGIA interrupt, and DISEL bit in DTC's MRB is 0 * When 0 is written to TGFA after reading TGFA = 1 1 [Setting conditions] * When TCNT = TGRA while TGRA is functioning as output compare register * When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register TGRB input capture/output compare flag 0 [Clearing conditions] * When DTC is activated by TGIB interrupt, and DISEL bit in DTC's MRB is 0 * When 0 is written to TGFB after reading TGFB = 1 1 [Setting conditions] * When TCNT = TGRB while TGRB is functioning as output compare register * When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register Overflow flag 0 [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000) Underflow flag 0 [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) Counter direction flag 0 TCNT counts down 1 TCNT counts up Note: * Can only be written with 0 for flag clearing. 942 TCNT1--Timer Counter 1 Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 H'FF26 7 0 6 0 5 0 4 0 3 0 2 0 1 0 TPU1 0 0 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter. TGR1A--Timer General Register 1A TGR1B--Timer General Register 1B Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 H'FF28 H'FF2A 7 1 6 1 5 1 4 1 3 1 2 1 1 1 TPU1 TPU1 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 943 TCR2--Timer Control Register 2 Bit : 7 -- Initial value : Read/Write : 0 -- 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 CKEG1 0 R/W H'FF30 3 CKEG0 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W TPU2 0 TPSC0 0 R/W Time prescaler 0 0 1 1 0 1 0 Internal clock: counts on o/1 1 Internal clock: counts on o/4 0 Internal clock: counts on o/16 1 Internal clock: counts on o/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 0 External clock: counts on TCLKC pin input 1 Internal clock: counts on o/1024 Note: This setting is invalid when channel 2 is in phase counting mode. Input clock edge select 0 0 Count at rising edge 1 Count at falling edge 1 -- Count at both edges Note: This setting is invalid when channel 2 is in phase counting mode, and also when o/1 is selected as the input clock. Counter clear 0 1 0 TCNT clearing disabled 1 TCNT cleared by TGRA compare match/input capture 0 TCNT cleared by TGRB compare match/input capture 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation* Note: * Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 944 TMDR2--Timer Mode Register 2 Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 -- 0 -- 4 -- 0 -- H'FF31 3 MD3 0 R/W Mode 0 0 0 1 1 0 1 1 * * 0 Normal operation 1 Reserved 0 PWM mode 1 1 PWM mode 2 2 MD2 0 R/W 1 MD1 0 R/W TPU2 0 MD0 0 R/W 0 Phase counting mode 1 1 Phase counting mode 2 0 Phase counting mode 3 1 Phase counting mode 4 *-- *: Don't care Note: MD3 is a reserved bit. In a write, it should always be written with 0. 945 TIOR2--Timer I/O Control Register 2 Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W TGR2A I/O control 0 0 0 0 TGR2A is output 1 compare 0 register 1 1 0 0 1 1 0 1 1 * 0 0 TGR2A is input 1 capture * register H'FF32 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W 1 IOA1 0 R/W TPU2 0 IOA0 0 R/W Output disabled Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Capture input source is TIOCA2 pin Input capture at rising edge Input capture at falling edge Input capture at both edges *: Don't care 1 1 TGR2B I/O control 0 0 0 0 TGR2B is output 1 compare 0 register 1 1 0 0 1 1 0 1 1 * 0 0 TGR2B is input 1 capture * register Output disabled Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Capture input source is TIOCB2 pin Input capture at rising edge Input capture at falling edge Input capture at both edges *: Don't care 1 1 946 TIER2--Timer Interrupt Enable Register 2 Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 -- 1 -- 5 TCIEU 0 R/W 4 TCIEV 0 R/W H'FF34 3 -- 0 -- 2 -- 0 -- 1 TGIEB 0 R/W TPU2 0 TGIEA 0 R/W TGIA interrupt enable 0 Interrupt requests (TGIA) by TGFA bit disabled 1 Interrupt requests (TGIA) by TGFA bit enabled TGIB interrupt enable 0 Interrupt requests (TGIB) by TGFB bit disabled 1 Interrupt requests (TGIB) by TGFB bit enabled Overflow interrupt enable 0 Interrupt requests (TCIV) by TCFV disabled 1 Interrupt requests (TCIV) by TCFV enabled Underflow interrupt enable 0 Interrupt requests (TCIU) by TCFU disabled 1 Interrupt requests (TCIU) by TCFU enabled A/D conversion start request enable 0 A/D conversion start request generation disabled 1 A/D conversion start request generation enabled 947 TSR2--Timer Status Register 2 Bit : 7 TCFD Initial value : Read/Write : 1 R 6 -- 1 -- 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* H'FF35 3 -- 0 -- 2 -- 0 -- 1 TGFB 0 R/(W)* 0 TPU2 TGFA 0 R/(W)* TGRA input capture/output compare flag 0 [Clearing conditions] * When DTC is activated by TGIA interrupt, and DISEL bit in DTC's MRB is 0 * When 0 is written to TGFA after reading TGFA = 1 1 [Setting conditions] * When TCNT = TGRA while TGRA is functioning as output compare register * When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register TGRB input capture/output compare flag 0 [Clearing conditions] * When DTC is activated by TGIB interrupt, and DISEL bit in DTC's MRB is 0 * When 0 is written to TGFB after reading TGFB = 1 1 [Setting conditions] * When TCNT = TGRB while TGRB is functioning as output compare register * When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register Overflow flag 0 [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000) Underflow flag 0 [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) Counter direction flag 0 TCNT counts down 1 TCNT counts up Note: * Can only be written with 0 for flag clearing. 948 TCNT2--Timer Counter 2 Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 H'FF36 7 0 6 0 5 0 4 0 3 0 2 0 1 0 TPU2 0 0 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter. TGR2A--Timer General Register 2A TGR2B--Timer General Register 2B Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 H'FF38 H'FF3A 7 1 6 1 5 1 4 1 3 1 2 1 1 1 TPU2 TPU2 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 949 TCSR0--Timer Control/Status Register 0 Bit : 7 OVF Initial value : Read/Write : 0 R/(W)* 6 WT/IT 0 R/W 5 TME 0 R/W 4 -- 1 -- H'FF74 (W), H'FF74 (R) 3 -- 1 -- 2 CKS2 0 R/W 1 CKS1 0 R/W WDT0 0 CKS0 0 R/W Clock select CKS2 CKS2 CKS2 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Clock Overflow Period* (when o = 20 MHz) 819.2 s 1.6 ms 6.6 ms 26.2 ms 104.9 ms 419.4 ms 1.68 s o/2 (Initial value) 25.6 s o/64 o/128 o/512 o/2048 o/8192 o/32768 o/131072 Note: * The overflow period is the time from when TCNT starts counting up until overflow occurs. Timer enable 0 TCNT is initialized to H'00 and halted 1 TCNT counts Timer mode select 0 Interval timer mode: Sends the CPU an interval timer interrupt request (WOVI) when TCNT overflows 1 Watchdog timer mode: Generates the WDTOVF signal when TCNT overflows* Note: * For details of the case where TCNT overflows in watchdog timer mode, see section 12.2.3, Reset Control/Status Register (RSTCSR). Overflow flag 0 [Clearing conditions] When 0 is written to OVF after reading TCSR when OVF = 1 1 [Setting condition] When TCNT overflows (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset Notes: TCSR is write-protected by a password to prevent accidental overwriting. For details see section 12.2.5, Notes on register access. * Can only be written with 0 for flag clearing. 950 TCNT0--Timer Counter 0 Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FF74 (W), H'FF75 (R) 3 0 R/W 2 0 R/W 1 0 R/W WDT 0 0 R/W Initial value : Read/Write : Note: TCNT is write-protected by a password to prevent accidental overwriting. For details see section 12.2.5, Notes on register access. RSTCSR--Reset Control/Status Register Bit : 7 WOVF Initial value : Read/Write : 0 R/(W)* 6 RSTE 0 R/W 5 RSTS 0 R/W 4 -- 1 -- H'FF76 (W), H'FF77 (R) 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- WDT 0 -- 1 -- Reset select 0 Power-on reset 1 Setting prohibited Reset enable 0 Internal reset is not performed when TCNT overflows* 1 Internal reset is performed when TCNT overflows Note: * The modules within the chip are not reset, but TCNT and TCSR within the WDT are reset. Watchdog overflow flag 0 [Clearing condition] When 0 is written to WOVF after reading TCSR when WOVF = 1 1 [Setting condition] When TCNT overflows (changes from H'FF to H'00) in watchdog timer mode Notes: RSTCSR is write-protected by a password to prevent accidental overwriting. For details see section 12.2.5, Notes on register access. * Can only be written with 0 for flag clearing. 951 SMR0--Serial Mode Register 0 Bit : 7 C/A Initial value : Read/Write : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W H'FF78 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 SCI0 CKS0 0 R/W Clock select 0 1 0 o clock 1 o/4 clock 0 o/16 clock 1 o/64 clock Multiprocessor mode 0 Multiprocessor function disabled 1 Multiprocessor format selected Stop bit length 0 1 stop bit Parity mode 0 Even parity*1 1 Odd parity*2 Notes: *1 When even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. *2 When odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd. 1 2 stop bits Parity enable 0 Parity bit addition and checking disabled 1 Parity bit addition and checking enabled* Note: * When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/E bit. Character length 0 8-bit data 1 7-bit data* Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted. Asynchronous mode/synchronous mode select 0 Asynchronous mode 1 Synchronous mode 952 SMR0--Serial Mode Register 0 Bit : 7 GM Initial value : Read/Write : 0 R/W 6 BLK 0 R/W 5 PE 0 R/W 4 O/E 0 R/W H'FF78 3 BCP1 0 R/W 2 BCP0 0 R/W Smart Card Interface 1 CKS1 0 R/W 0 CKS0 0 R/W Clock select 0 1 Basic clock pulse 0 1 Parity mode 0 Even parity *1 0 o clock 1 o/4 clock 0 o/16 clock 1 o/64 clock 0 32 clock periods 1 64 clock periods 0 372 clock periods 1 256 clock periods 1 Odd parity*2 Notes: *1 When even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. *2 When odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd. Parity enable 0 Parity bit addition and checking disabled 1 Parity bit addition and checking enabled Note: When the smart card interface is used, be sure to make the 1 setting. Block transfer mode 0 Normal smart card interface mode operation * Error signal transmission/detection and automatic data retransmission performed * TXI interrupt generated by TEND flag * TEND flag set 12.5 etu after start of transmission (11.0 etu in GSM mode) 1 Block transfer mode operation * Error signal transmission/detection and automatic data retransmission not performed * TXI interrupt generated by TDRE flag * TEND flag set 11.5 etu after start of transmission (11.0 etu in GSM mode) GSM mode 0 Normal smart card interface mode operation * TEND flag generation 12.5 etu (11.5 etu in block transfer mode) after beginning of start bit * Clock output on/off control only 1 GSM mode smart card interface mode operation * TEND flag generation 11.0 etu after beginning of start bit * High/low fixing control possible in addition to clock output on/off control (set by SCR) Note: etu: Elementary Time Unit (time for transfer of 1 bit) 953 BRR0--Bit Rate Register 0 Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FF79 3 1 R/W SCI0, Smart Card Interface 2 1 R/W 1 1 R/W 0 1 R/W Initial value : Read/Write : Sets the serial transmit/receive bit rate Note: For details see section 13.2.8, Bit Rate Register (BRR). 954 SCR0--Serial Control Register 0 Bit : 7 TIE Initial value : Read/Write : 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W H'FF7A 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 SCI0 CKE0 0 R/W Clock enable 0 Asynchronous Internal clock/SCK pin functions as mode I/O port Synchronous Internal clock/SCK pin functions as mode serial clock output 1 Asynchronous Internal clock/SCK pin functions as mode clock output*1 Synchronous Internal clock/SCK pin functions as mode serial clock output 1 0 Asynchronous External clock/SCK pin functions as mode clock input*2 Synchronous External clock/SCK pin functions as mode serial clock input 1 Asynchronous External clock/SCK pin functions as mode clock input*2 Synchronous External clock/SCK pin functions as mode serial clock input Notes: *1 Outputs a clock of the same frequency as the bit rate. *2 Inputs a clock with a frequency 16 times the bit rate. Transmit end interrupt enable 0 Transmit end interrupt (TEI) request disabled 1 Transmit end interrupt (TEI) request enabled Multiprocessor interrupt enable 0 Multiprocessor interrupts disabled [Clearing conditions] * When the MPIE bit is cleared to 0 * When data with MPB = 1 is received 1 Multiprocessor interrupts enabled Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received Receive enable 0 Reception disabled 1 Reception enabled Transmit enable 0 Transmission disabled 1 Transmission enabled Receive interrupt enable 0 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled Transmit interrupt enable 0 Transmit data empty interrupt (TXI) request disabled 1 Transmit data empty interrupt (TXI) request enabled Note: For details of how to clear interrupt requests, see section 13.2.6, Serial Control Register (SCR). 0 955 SCR0--Serial Control Register 0 Bit : 7 TIE Initial value : Read/Write : 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W H'FF7A 3 MPIE 0 R/W 2 TEIE 0 R/W Smart Card Interface 1 CKE1 0 R/W 0 CKE0 0 R/W Clock enable SCMR SMR SCR Setting SCK Pin Function SMIF C/A, GM CKE1 CKE0 0 See the SCI specification 1 0 0 0 1 1 0 1 1 0 1 Operates as port I/O pin Outputs clock as SCK output pin Operates as SCK output pin, with output fixed low Outputs clock as SCK output pin Operates as SCK output pin, with output fixed high Outputs clock as SCK output pin Transmit end interrupt enable 0 Transmit end interrupt (TEI) request disabled 1 Transmit end interrupt (TEI) request enabled Multiprocessor interrupt enable 0 Multiprocessor interrupts disabled [Clearing conditions] * When the MPIE bit is cleared to 0 * When data with MPB = 1 is received 1 Multiprocessor interrupts enabled Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received Receive enable 0 Reception disabled 1 Reception enabled Transmit enable 0 Transmission disabled 1 Transmission enabled Receive interrupt enable 0 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled Transmit interrupt enable 0 Transmit data empty interrupt (TXI) request disabled 1 Transmit data empty interrupt (TXI) request enabled Note: For details of how to clear interrupt requests, see section 13.2.6, Serial Control Register (SCR). 956 TDR0--Transmit Data Register 0 Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FF7B 3 1 R/W SCI0, Smart Card Interface 2 1 R/W 1 1 R/W 0 1 R/W Initial value : Read/Write : Stores data for serial transmission 957 SSR0--Serial Status Register 0 Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 ERS 0 R/(W)* H'FF7C 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 SCI0 MPBT 0 R/W Multiprocessor bit transfer 0 Data with a 0 multiprocessor bit is transmitted 1 Data with a 1 multiprocessor bit is transmitted Multiprocessor bit 0 [Clearing condition] When data with a 0 multiprocessor bit is received 1 [Setting condition] When data with a 1 multiprocessor bit is received Transmit end 0 [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR 1 [Setting conditions] * When the TE bit in SCR is 0 * When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character Parity error 0 [Clearing condition] When 0 is written to PER after reading PER = 1 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR Framing error 0 [Clearing condition] When 0 is written to FER after reading FER = 1 1 [Setting condition] When the SCI checks whether the stop bit at the end of the receive data is 1 when reception ends, and the stop bit is 0 Overrun error 0 [Clearing condition] When 0 is written to ORER after reading ORER = 1 1 [Setting condition] When the next serial reception is completed while RDRF = 1 Receive data register full 0 [Clearing conditions] * When 0 is written to RDRF after reading RDRF = 1 * When the DTC is activated by an RXI interrupt and reads data from RDR 1 [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR Transmit data register empty 0 [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR 1 [Setting conditions] * When the TE bit in SCR is 0 * When data is transferred from TDR to TSR and data can be written to TDR Notes: For details, see section 13.2.7, Serial Status Register (SSR). * Can only be written with 0 for flag clearing. 958 SSR0--Serial Status Register 0 Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 ERS 0 R/(W)* H'FF7C 3 PER 0 R/(W)* 2 TEND 1 R Smart Card Interface 1 MPB 0 R 0 MPBT 0 R/W Multiprocessor bit transfer 0 Data with a 0 multiprocessor bit is transmitted 1 Data with a 1 multiprocessor bit is transmitted Multiprocessor bit 0 [Clearing condition] When data with a 0 multiprocessor bit is received 1 [Setting condition] When data with a 1 multiprocessor bit is received Transmit end 0 [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR 1 [Setting conditions] * Upon reset, and in standby mode or module stop mode * When the TE bit in SCR is 0 and the ERS bit is also 0 * When TDRE = 1 ERS = 0 (normal transmission) 2.5 etu after transmission of a 1-byte serial character when GM = 0 and BLK = 0 * When TDRE = 1 ERS = 0 (normal transmission) 1.5 etu after transmission of a 1-byte serial character when GM = 0 and BLK = 1 * When TDRE = 1 ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when GM = 1 and BLK = 0 * When TDRE = 1 ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when GM = 1 and BLK = 1 Note: etu: Elementary Time Unit (time for transfer of 1 bit) Parity error 0 [Clearing condition] When 0 is written to PER after reading PER = 1 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR Error signal status 0 [Clearing conditions] * Upon reset, and in standby mode or module stop mode * When 0 is written to ERS after reading ERS = 1 1 [Setting condition] When the low level of the error signal is sampled Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its previous state. Overrun error 0 [Clearing condition] When 0 is written to ORER after reading ORER = 1 1 [Setting condition] When the next serial reception is completed while RDRF = 1 Receive data register full 0 [Clearing conditions] * When 0 is written to RDRF after reading RDRF = 1 * When the DTC is activated by an RXI interrupt and reads data from RDR 1 [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR Transmit data register empty 0 [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR 1 [Setting conditions] * When the TE bit in SCR is 0 * When data is transferred from TDR to TSR and data can be written to TDR Notes: For details, see section 14.2.2, Serial Status Register (SSR). * Can only be written with 0 for flag clearing. 959 RDR0--Receive Data Register 0 Bit : 7 0 R 6 0 R 5 0 R 4 0 R H'FF7D 3 0 R SCI0, Smart Card Interface 2 0 R 1 0 R 0 0 R Initial value : Read/Write : Stores received serial data SCMR0--Smart Card Mode Register 0 Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- H'FF7E 3 SDIR 0 R/W SCI0, Smart Card Interface 2 SINV 0 R/W 1 -- 1 -- 0 SMIF 0 R/W Smart card interface mode select 0 Smart card interface function is disabled 1 Smart card interface function is enabled Smart card data invert 0 TDR contents are transmitted as they are Receive data is stored as it is in RDR 1 TDR contents are inverted before being transmitted Receive data is stored in inverted form in RDR Smart card data transfer direction 0 TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first 1 TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first 960 SMR1--Serial Mode Register 1 Bit : 7 GM Initial value : Read/Write : 0 R/W 6 BLK 0 R/W 5 PE 0 R/W 4 O/E 0 R/W H'FF80 3 BCP1 0 R/W 2 BCP0 0 R/W 1 CKS1 0 R/W 0 SCI1 CKS0 0 R/W Clock select 0 1 Basic clock pulse 0 1 Parity mode 0 Even parity *1 0 o clock 1 o/4 clock 0 o/16 clock 1 o/64 clock 0 32 clock periods 1 64 clock periods 0 372 clock periods 1 256 clock periods 1 Odd parity*2 Notes: *1 When even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. *2 When odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd. Parity enable 0 Parity bit addition and checking disabled 1 Parity bit addition and checking enabled Note: When the smart card interface is used, be sure to make the 1 setting. Block transfer mode 0 Normal smart card interface mode operation * Error signal transmission/detection and automatic data retransmission performed * TXI interrupt generated by TEND flag * TEND flag set 12.5 etu after start of transmission (11.0 etu in GSM mode) 1 Block transfer mode operation * Error signal transmission/detection and automatic data retransmission not performed * TXI interrupt generated by TDRE flag * TEND flag set 11.5 etu after start of transmission (11.0 etu in GSM mode) GSM mode 0 Normal smart card interface mode operation * TEND flag generation 12.5 etu (11.5 etu in block transfer mode) after beginning of start bit * Clock output on/off control only 1 GSM mode smart card interface mode operation * TEND flag generation 11.0 etu after beginning of start bit * High/low fixing control possible in addition to clock output on/off control (set by SCR) Note: etu: Elementary Time Unit (time for transfer of 1 bit) 961 SMR1--Serial Mode Register 1 Bit : 7 GM Initial value : Read/Write : 0 R/W 6 BLK 0 R/W 5 PE 0 R/W 4 O/E 0 R/W H'FF80 3 BCP1 0 R/W 2 BCP0 0 R/W Smart Card Interface 1 CKS1 0 R/W 0 CKS0 0 R/W Clock select 0 1 Basic clock pulse 0 1 Parity mode 0 Even parity *1 0 o clock 1 o/4 clock 0 o/16 clock 1 o/64 clock 0 32 clock periods 1 64 clock periods 0 372 clock periods 1 256 clock periods 1 Odd parity*2 Notes: *1 When even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. *2 When odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd. Parity enable 0 Parity bit addition and checking disabled 1 Parity bit addition and checking enabled Note: When the smart card interface is used, be sure to make the 1 setting. Block transfer mode 0 Normal smart card interface mode operation * Error signal transmission/detection and automatic data retransmission performed * TXI interrupt generated by TEND flag * TEND flag set 12.5 etu after start of transmission (11.0 etu in GSM mode) 1 Block transfer mode operation * Error signal transmission/detection and automatic data retransmission not performed * TXI interrupt generated by TDRE flag * TEND flag set 11.5 etu after start of transmission (11.0 etu in GSM mode) GSM mode 0 Normal smart card interface mode operation * TEND flag generation 12.5 etu (11.5 etu in block transfer mode) after beginning of start bit * Clock output on/off control only 1 GSM mode smart card interface mode operation * TEND flag generation 11.0 etu after beginning of start bit * High/low fixing control possible in addition to clock output on/off control (set by SCR) Note: etu: Elementary Time Unit (time for transfer of 1 bit) 962 BRR1--Bit Rate Register 1 Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FF81 3 1 R/W SCI1, Smart Card Interface 2 1 R/W 1 1 R/W 0 1 R/W Initial value : Read/Write : Sets the serial transmit/receive bit rate Note: For details see section 13.2.8, Bit Rate Register (BRR). 963 SCR1--Serial Control Register 1 Bit : 7 TIE Initial value : Read/Write : 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W H'FF82 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 SCI1 CKE0 0 R/W Clock enable 0 Asynchronous Internal clock/SCK pin functions as mode I/O port Synchronous Internal clock/SCK pin functions as mode serial clock output 1 Asynchronous Internal clock/SCK pin functions as mode clock output*1 Synchronous Internal clock/SCK pin functions as mode serial clock output 1 0 Asynchronous External clock/SCK pin functions as mode clock input*2 Synchronous External clock/SCK pin functions as mode serial clock input 1 Asynchronous External clock/SCK pin functions as mode clock input*2 Synchronous External clock/SCK pin functions as mode serial clock input Notes: *1 Outputs a clock of the same frequency as the bit rate. *2 Inputs a clock with a frequency 16 times the bit rate. Transmit end interrupt enable 0 Transmit end interrupt (TEI) request disabled 1 Transmit end interrupt (TEI) request enabled Multiprocessor interrupt enable 0 Multiprocessor interrupts disabled [Clearing conditions] * When the MPIE bit is cleared to 0 * When data with MPB = 1 is received 1 Multiprocessor interrupts enabled Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received Receive enable 0 Reception disabled 1 Reception enabled Transmit enable 0 Transmission disabled 1 Transmission enabled Receive interrupt enable 0 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled Transmit interrupt enable 0 Transmit data empty interrupt (TXI) request disabled 1 Transmit data empty interrupt (TXI) request enabled Note: For details of how to clear interrupt requests, see section 13.2.6, Serial Control Register (SCR). 0 964 SCR1--Serial Control Register 1 Bit : 7 TIE Initial value : Read/Write : 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W H'FF82 3 MPIE 0 R/W 2 TEIE 0 R/W Smart Card Interface 1 CKE1 0 R/W 0 CKE0 0 R/W Clock enable SCMR SMR SCR Setting SCK Pin Function SMIF C/A, GM CKE1 CKE0 0 See the SCI specification 1 0 0 0 1 1 0 1 1 0 1 Operates as port I/O pin Outputs clock as SCK output pin Operates as SCK output pin, with output fixed low Outputs clock as SCK output pin Operates as SCK output pin, with output fixed high Outputs clock as SCK output pin Transmit end interrupt enable 0 Transmit end interrupt (TEI) request disabled 1 Transmit end interrupt (TEI) request enabled Multiprocessor interrupt enable 0 Multiprocessor interrupts disabled [Clearing conditions] * When the MPIE bit is cleared to 0 * When data with MPB = 1 is received 1 Multiprocessor interrupts enabled Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received Receive enable 0 Reception disabled 1 Reception enabled Transmit enable 0 Transmission disabled 1 Transmission enabled Receive interrupt enable 0 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled Transmit interrupt enable 0 Transmit data empty interrupt (TXI) request disabled 1 Transmit data empty interrupt (TXI) request enabled Note: For details of how to clear interrupt requests, see section 13.2.6, Serial Control Register (SCR). 965 TDR1--Transmit Data Register 1 Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FF83 3 1 R/W SCI1, Smart Card Interface 2 1 R/W 1 1 R/W 0 1 R/W Initial value : Read/Write : Stores data for serial transmission 966 SSR1--Serial Status Register 1 Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* H'FF84 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 SCI MPBT 0 R/W Multiprocessor bit transfer 0 Data with a 0 multiprocessor bit is transmitted 1 Data with a 1 multiprocessor bit is transmitted Multiprocessor bit 0 [Clearing condition] When data with a 0 multiprocessor bit is received 1 [Setting condition] When data with a 1 multiprocessor bit is received Transmit end 0 [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR 1 [Setting conditions] * When the TE bit in SCR is 0 * When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character Parity error 0 [Clearing condition] When 0 is written to PER after reading PER = 1 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR Framing error 0 [Clearing condition] When 0 is written to FER after reading FER = 1 1 [Setting condition] When the SCI checks whether the stop bit at the end of the receive data is 1 when reception ends, and the stop bit is 0 Overrun error 0 [Clearing condition] When 0 is written to ORER after reading ORER = 1 1 [Setting condition] When the next serial reception is completed while RDRF = 1 Receive data register full 0 [Clearing conditions] * When 0 is written to RDRF after reading RDRF = 1 * When the DTC is activated by an RXI interrupt and reads data from RDR 1 [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR Transmit data register empty 0 [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR 1 [Setting conditions] * When the TE bit in SCR is 0 * When data is transferred from TDR to TSR and data can be written to TDR Notes: For details, see section 13.2.7, Serial Status Register (SSR). * Can only be written with 0 for flag clearing. 967 SSR1--Serial Status Register 1 Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 ERS 0 R/(W)* H'FF84 3 PER 0 R/(W)* 2 TEND 1 R Smart Card Interface 1 MPB 0 R 0 MPBT 0 R/W Multiprocessor bit transfer 0 Data with a 0 multiprocessor bit is transmitted 1 Data with a 1 multiprocessor bit is transmitted Multiprocessor bit 0 [Clearing condition] When data with a 0 multiprocessor bit is received 1 [Setting condition] When data with a 1 multiprocessor bit is received Transmit end 0 [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR 1 [Setting conditions] * Upon reset, and in standby mode or module stop mode * When the TE bit in SCR is 0 and the ERS bit is also 0 * When TDRE = 1 ERS = 0 (normal transmission) 2.5 etu after transmission of a 1-byte serial character when GM = 0 and BLK = 0 * When TDRE = 1 ERS = 0 (normal transmission) 1.5 etu after transmission of a 1-byte serial character when GM = 0 and BLK = 1 * When TDRE = 1 ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when GM = 1 and BLK = 0 * When TDRE = 1 ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when GM = 1 and BLK = 1 Note: etu: Elementary Time Unit (time for transfer of 1 bit) Parity error 0 [Clearing condition] When 0 is written to PER after reading PER = 1 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR Error signal status 0 [Clearing conditions] * Upon reset, and in standby mode or module stop mode * When 0 is written to ERS after reading ERS = 1 1 [Setting condition] When the low level of the error signal is sampled Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its previous state. Overrun error 0 [Clearing condition] When 0 is written to ORER after reading ORER = 1 1 [Setting condition] When the next serial reception is completed while RDRF = 1 Receive data register full 0 [Clearing conditions] * When 0 is written to RDRF after reading RDRF = 1 * When the DTC is activated by an RXI interrupt and reads data from RDR 1 [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR Transmit data register empty 0 [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR 1 [Setting conditions] * When the TE bit in SCR is 0 * When data is transferred from TDR to TSR and data can be written to TDR Notes: For details, see section 14.2.2, Serial Status Register (SSR). * Can only be written with 0 for flag clearing. 968 RDR1--Receive Data Register 1 Bit : 7 0 R 6 0 R 5 0 R 4 0 R H'FF85 3 0 R SCI, Smart Card Interface 2 0 R 1 0 R 0 0 R Initial value : Read/Write : Stores received serial data SCMR1--Smart Card Mode Register 1 Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- H'FF86 3 SDIR 0 R/W SCI, Smart Card Interface 2 SINV 0 R/W 1 -- 1 -- 0 SMIF 0 R/W Smart card interface mode select 0 Smart card interface function is disabled 1 Smart card interface function is enabled Smart card data invert 0 TDR contents are transmitted as they are Receive data is stored as it is in RDR 1 TDR contents are inverted before being transmitted Receive data is stored in inverted form in RDR Smart card data transfer direction 0 TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first 1 TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first 969 SMR2--Serial Mode Register 2 Bit : 7 C/A Initial value : Read/Write : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W H'FF88 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 SCI CKS0 0 R/W Clock select 0 1 0 o clock 1 o/4 clock 0 o/16 clock 1 o/64 clock Multiprocessor mode 0 Multiprocessor function disabled 1 Multiprocessor format selected Stop bit length 0 1 stop bit Parity mode 0 Even parity*1 1 Odd parity*2 Notes: *1 When even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. *2 When odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd. 1 2 stop bits Parity enable 0 Parity bit addition and checking disabled 1 Parity bit addition and checking enabled* Note: * When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/E bit. Character length 0 8-bit data 1 7-bit data* Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted. Asynchronous mode/synchronous mode select 0 Asynchronous mode 1 Synchronous mode 970 SMR2--Serial Mode Register 2 Bit : 7 GM Initial value : Read/Write : 0 R/W 6 BLK 0 R/W 5 PE 0 R/W 4 O/E 0 R/W H'FF88 3 BCP1 0 R/W 2 BCP0 0 R/W Smart Card Interface 1 CKS1 0 R/W 0 CKS0 0 R/W Clock select 0 1 Basic clock pulse 0 1 Parity mode 0 Even parity *1 0 o clock 1 o/4 clock 0 o/16 clock 1 o/64 clock 0 32 clock periods 1 64 clock periods 0 372 clock periods 1 256 clock periods 1 Odd parity*2 Notes: *1 When even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. *2 When odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd. Parity enable 0 Parity bit addition and checking disabled 1 Parity bit addition and checking enabled Note: When the smart card interface is used, be sure to make the 1 setting. Block transfer mode 0 Normal smart card interface mode operation * Error signal transmission/detection and automatic data retransmission performed * TXI interrupt generated by TEND flag * TEND flag set 12.5 etu after start of transmission (11.0 etu in GSM mode) 1 Block transfer mode operation * Error signal transmission/detection and automatic data retransmission not performed * TXI interrupt generated by TDRE flag * TEND flag set 11.5 etu after start of transmission (11.0 etu in GSM mode) GSM mode 0 Normal smart card interface mode operation * TEND flag generation 12.5 etu (11.5 etu in block transfer mode) after beginning of start bit * Clock output on/off control only 1 GSM mode smart card interface mode operation * TEND flag generation 11.0 etu after beginning of start bit * High/low fixing control possible in addition to clock output on/off control (set by SCR) Note: etu: Elementary Time Unit (time for transfer of 1 bit) 971 BRR2--Bit Rate Register 2 Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FF89 3 1 R/W SCI, Smart Card Interface 2 1 R/W 1 1 R/W 0 1 R/W Initial value : Read/Write : Sets the serial transmit/receive bit rate Note: For details see section 13.2.8, Bit Rate Register (BRR). 972 SCR2--Serial Control Register 2 Bit : 7 TIE Initial value : Read/Write : 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W H'FF8A 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 SCI CKE0 0 R/W Clock enable 0 Asynchronous Internal clock/SCK pin functions as mode I/O port Synchronous Internal clock/SCK pin functions as mode serial clock output 1 Asynchronous Internal clock/SCK pin functions as mode clock output*1 Synchronous Internal clock/SCK pin functions as mode serial clock output 1 0 Asynchronous External clock/SCK pin functions as mode clock input*2 Synchronous External clock/SCK pin functions as mode serial clock input 1 Asynchronous External clock/SCK pin functions as mode clock input*2 Synchronous External clock/SCK pin functions as mode serial clock input Notes: *1 Outputs a clock of the same frequency as the bit rate. *2 Inputs a clock with a frequency 16 times the bit rate. Transmit end interrupt enable 0 Transmit end interrupt (TEI) request disabled 1 Transmit end interrupt (TEI) request enabled Multiprocessor interrupt enable 0 Multiprocessor interrupts disabled [Clearing conditions] * When the MPIE bit is cleared to 0 * When data with MPB = 1 is received 1 Multiprocessor interrupts enabled Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received Receive enable 0 Reception disabled 1 Reception enabled Transmit enable 0 Transmission disabled 1 Transmission enabled Receive interrupt enable 0 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled Transmit interrupt enable 0 Transmit data empty interrupt (TXI) request disabled 1 Transmit data empty interrupt (TXI) request enabled Note: For details of how to clear interrupt requests, see section 13.2.6, Serial Control Register (SCR). 0 973 SCR2--Serial Control Register 2 Bit : 7 TIE Initial value : Read/Write : 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W H'FF8A 3 MPIE 0 R/W 2 TEIE 0 R/W Smart Card Interface 1 CKE1 0 R/W 0 CKE0 0 R/W Clock enable SCMR SMR SCR Setting SCK Pin Function SMIF C/A, GM CKE1 CKE0 0 See the SCI specification 1 0 0 0 1 1 0 1 1 0 1 Operates as port I/O pin Outputs clock as SCK output pin Operates as SCK output pin, with output fixed low Outputs clock as SCK output pin Operates as SCK output pin, with output fixed high Outputs clock as SCK output pin Transmit end interrupt enable 0 Transmit end interrupt (TEI) request disabled 1 Transmit end interrupt (TEI) request enabled Multiprocessor interrupt enable 0 Multiprocessor interrupts disabled [Clearing conditions] * When the MPIE bit is cleared to 0 * When data with MPB = 1 is received 1 Multiprocessor interrupts enabled Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received Receive enable 0 Reception disabled 1 Reception enabled Transmit enable 0 Transmission disabled 1 Transmission enabled Receive interrupt enable 0 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled Transmit interrupt enable 0 Transmit data empty interrupt (TXI) request disabled 1 Transmit data empty interrupt (TXI) request enabled Note: For details of how to clear interrupt requests, see section 13.2.6, Serial Control Register (SCR). 974 TDR2--Transmit Data Register 2 Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FF8B 3 1 R/W SCI, Smart Card Interface 2 1 R/W 1 1 R/W 0 1 R/W Initial value : Read/Write : Stores data for serial transmission 975 SSR2--Serial Status Register 2 Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* H'FF8C 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 SCI MPBT 0 R/W Multiprocessor bit transfer 0 Data with a 0 multiprocessor bit is transmitted 1 Data with a 1 multiprocessor bit is transmitted Multiprocessor bit 0 [Clearing condition] When data with a 0 multiprocessor bit is received 1 [Setting condition] When data with a 1 multiprocessor bit is received Transmit end 0 [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR 1 [Setting conditions] * When the TE bit in SCR is 0 * When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character Parity error 0 [Clearing condition] When 0 is written to PER after reading PER = 1 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR Framing error 0 [Clearing condition] When 0 is written to FER after reading FER = 1 1 [Setting condition] When the SCI checks whether the stop bit at the end of the receive data is 1 when reception ends, and the stop bit is 0 Overrun error 0 [Clearing condition] When 0 is written to ORER after reading ORER = 1 1 [Setting condition] When the next serial reception is completed while RDRF = 1 Receive data register full 0 [Clearing conditions] * When 0 is written to RDRF after reading RDRF = 1 * When the DTC is activated by an RXI interrupt and reads data from RDR 1 [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR Transmit data register empty 0 [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR 1 [Setting conditions] * When the TE bit in SCR is 0 * When data is transferred from TDR to TSR and data can be written to TDR Notes: For details, see section 13.2.7, Serial Status Register (SSR). * Can only be written with 0 for flag clearing. 976 SSR2--Serial Status Register 2 Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 ERS 0 R/(W)* H'FF8C 3 PER 0 R/(W)* 2 TEND 1 R Smart Card Interface 1 MPB 0 R 0 MPBT 0 R/W Multiprocessor bit transfer 0 Data with a 0 multiprocessor bit is transmitted 1 Data with a 1 multiprocessor bit is transmitted Multiprocessor bit 0 [Clearing condition] When data with a 0 multiprocessor bit is received 1 [Setting condition] When data with a 1 multiprocessor bit is received Transmit end 0 [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR 1 [Setting conditions] * Upon reset, and in standby mode or module stop mode * When the TE bit in SCR is 0 and the ERS bit is also 0 * When TDRE = 1 ERS = 0 (normal transmission) 2.5 etu after transmission of a 1-byte serial character when GM = 0 and BLK = 0 * When TDRE = 1 ERS = 0 (normal transmission) 1.5 etu after transmission of a 1-byte serial character when GM = 0 and BLK = 1 * When TDRE = 1 ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when GM = 1 and BLK = 0 * When TDRE = 1 ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when GM = 1 and BLK = 1 Note: etu: Elementary Time Unit (time for transfer of 1 bit) Parity error 0 [Clearing condition] When 0 is written to PER after reading PER = 1 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR Error signal status 0 [Clearing conditions] * Upon reset, and in standby mode or module stop mode * When 0 is written to ERS after reading ERS = 1 1 [Setting condition] When the low level of the error signal is sampled Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its previous state. Overrun error 0 [Clearing condition] When 0 is written to ORER after reading ORER = 1 1 [Setting condition] When the next serial reception is completed while RDRF = 1 Receive data register full 0 [Clearing conditions] * When 0 is written to RDRF after reading RDRF = 1 * When the DTC is activated by an RXI interrupt and reads data from RDR 1 [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR Transmit data register empty 0 [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR 1 [Setting conditions] * When the TE bit in SCR is 0 * When data is transferred from TDR to TSR and data can be written to TDR Notes: For details, see section 14.2.2, Serial Status Register (SSR). * Can only be written with 0 for flag clearing. 977 RDR2--Receive Data Register 2 Bit : 7 0 R 6 0 R 5 0 R 4 0 R H'FF8D 3 0 R SCI, Smart Card Interface 2 0 R 1 0 R 0 0 R Initial value : Read/Write : Stores received serial data SCMR2--Smart Card Mode Register 2 Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- H'FF8E 3 SDIR 0 R/W SCI, Smart Card Interface 2 SINV 0 R/W 1 -- 1 -- 0 SMIF 0 R/W Smart card interface mode select 0 Smart card interface function is disabled 1 Smart card interface function is enabled Smart card data invert 0 TDR contents are transmitted as they are Receive data is stored as it is in RDR 1 TDR contents are inverted before being transmitted Receive data is stored in inverted form in RDR Smart card data transfer direction 0 TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first 1 TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first 978 ADDRA--A/D Data Register A ADDRB--A/D Data Register B ADDRC--A/D Data Register C ADDRD--A/D Data Register D Bit : 15 14 13 12 11 10 9 8 H'FF90 H'FF92 H'FF94 H'FF96 7 6 5 -- 0 R 4 -- 0 R 3 -- 0 R A/D Converter A/D Converter A/D Converter A/D Converter 2 -- 0 R 1 -- 0 R 0 -- 0 R AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Initial value : Read/Write : 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Analog input channels and corresponding ADDR registers Analog Input Channel Channel Set 0 (CH3 = 0) Group 0 AN0 AN1 AN2 AN3 Group 1 AN4 AN5 AN6 AN7 Channel Set 1 (CH3 = 1) Group 0 AN8 AN9 AN10 AN11 Group 1 AN12 AN13 AN14 AN15 ADDRA ADDRB ADDRC ADDRD A/D Data Register Note: The upper byte can be read directly, but for the lower byte, data transfer is performed via a temporary register (TEMP). For details see section 16.3, Interface to Bus Master. 979 ADCSR--A/D Control/Status Register Bit : 7 ADF Initial value : Read/Write : 0 R/W* 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W H'FF98 3 CH3 0 R/W 2 CH2 0 R/W A/D Converter 1 CH1 0 R/W 0 CH0 0 R/W Channel select CH3 CH2 CH1 CH0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Channel select 0 AN8 to AN11 are group 0 analog input pins, AN12 to AN15 are group 1 analog input pins 1 AN0 to AN3 are group 0 analog input pins, AN4 to AN7 are group 1 analog input pins Scan mode 0 Single mode 1 Scan mode A/D start 0 A/D conversion stopped 1 * Single mode: A/D conversion is started. Cleared to 0 automatically when conversion on the specified channel ends * Scan mode: A/D conversion is started. Conversion continues consecutively on the selected channels until ADST is cleared to 0 by software, a reset, or a transition to standby mode or module stop mode A/D interrupt enable 0 A/D conversion end interrupt (ADI) request disabled 1 A/D conversion end interrupt (ADI) request enabled A/D end flag 0 [Clearing conditions] * When 0 is written to ADF after reading ADF = 1 * When the DTC is activated by an ADI interrupt and ADDR is read 1 [Setting conditions] * Single mode: When A/D conversion ends * Scan mode: When A/D conversion ends on all specified channels Note: * Can only be written with 0 for flag clearing. 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Single Mode (SCAN = 0) AN0 (Initial value) AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 Scan Mode (SCAN = 1) AN0 AN0, AN1 AN0 to AN2 AN0 to AN3 AN4 AN4, AN5 AN4 to AN6 AN4 to AN7 AN8 AN8, AN9 AN8 to AN10 AN8 to AN11 AN12 AN12, AN13 AN12 to AN14 AN12 to AN15 980 ADCR--A/D Control Register Bit : 7 TRGS1 Initial value : Read/Write : 0 R/W 6 TRGS0 0 R/W 5 -- 1 -- 4 -- 1 -- H'FF99 3 CKS1 0 R/W 2 CKS0 0 R/W 1 A/D Converter 0 -- 1 -- -- 1 -- Clock select 0 1 0 Conversion time = 530 states (max.) 1 Conversion time = 266 states (max.) 0 Conversion time = 134 states (max.) 1 Conversion time = 68 states (max.) Timer trigger select 0 1 0 A/D conversion start by software is enabled 1 A/D conversion start by TPU conversion start trigger is enabled 0 Setting prohibited 1 A/D conversion start by external trigger pin (ADTRG) is enabled 981 TCSR1--Timer Control/Status Register 1*2 Bit Initial value Read/Write 7 OVF 0 R/(W)*1 6 WT/IT 0 R/W 5 TME 0 R/W 4 PSS 0 R/W H'FFA2 3 RST/NMI 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 WDT1 CKS0 0 R/W Clock select 2 to 0 PSS CKS2 CKS1 CKS0 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Clock o/2 o/64 o/128 o/512 o/2048 o/8192 o/32768 o/131072 oSUB/2 oSUB/4 oSUB/8 oSUB/16 oSUB/32 oSUB/64 oSUB/128 oSUB/256 Overflow cycle* (when o = 20 MHz) (when oSUB = 32.768 kHz) 25.6 s 819.2 s 1.6 ms 6.6 ms 26.2 ms 104.9 ms 419.4 ms 1.68 s 15.6 ms 31.3 ms 62.5 ms 125 ms 250 ms 500 ms 1s 2s Note: *The overflow cycle starts when TCNT starts counting from H'00 and ends when an overflow occurs. Reset or NMI 0 1 NMI interrupt request Internal reset request Prescaler select 0 1 Timer enable 0 1 Initializes TCNT to H'00 and disables the counting operation TCNT performs counting operation TCNT counts the divided clock output by the o-based prescaler TCNT counts the divided clock output by the oSUB-based prescaler (PSS) Timer mode select 0 1 Interval timer mode: Interval timer interrupt (WOVI) request sent to CPU when overflow occurs at TCNT Watchdog timer mode: Reset or NMI interrupt request sent to CPU when overflow occurs at TCNT Overflow flag 0 [Clearing] (1) When 0 is written to TME bit; (2) When 0 is written to OVF bit after reading TCSR when OVF=1. 1 [Setting] When TCNT overflows (H'FF H'00). When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset. Notes: TCSR is write-protected by a password to prevent accidental overwriting. For details see section 12.2.5, Notes on Register Access. *1 Only 0 can be written to these bits (to clear these flags). *2 This register is not available, and must not be accessed, in the H8S/2623 Series. 982 TCNT1--Timer Counter 1* Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FFA2 (W), H'FFA3 (R) 3 0 R/W 2 0 R/W 1 0 R/W WDT1 0 0 R/W Initial value : Read/Write : Notes: TCNT1 is write-protected by a password to prevent accidental overwriting. For details see section 12.2.5, Notes on Register Access. * This register is not available, and must not be accessed, in the H8S/2623 Series. 983 FLMCR1--Flash Memory Control Register 1 Bit : 7 FWE Initial value : Read/Write : --* R 6 SWE1 0 R/W 5 ESU1 0 R/W 4 PSU1 0 R/W H'FFA8 3 EV1 0 R/W 2 PV1 0 R/W 1 E1 0 R/W ROM 0 P1 0 R/W Program 1 0 Program mode cleared 1 Transition to program mode [Setting condition] When FWE = 1, SWE1 = 1, and PSU1 = 1 Erase 1 0 Erase mode cleared 1 Transition to erase mode [Setting condition] When FWE = 1, SWE1 = 1, and ESU1 = 1 Program-verify 1 0 Program-verify mode cleared 1 Transition to program-verify mode [Setting condition] When FWE = 1 and SWE1 = 1 Erase-verify 1 0 Erase-verify mode cleared 1 Transition to erase-verify mode [Setting condition] When FWE = 1 and SWE1 = 1 Program setup bit 1 0 Program setup cleared 1 Program setup [Setting condition] When FWE = 1 and SWE1 = 1 Erase setup bit 1 0 Erase setup cleared 1 Erase setup [Setting condition] When FWE = 1 and SWE1 = 1 Software write enable bit 1 0 Writes disabled 1 Writes enabled [Setting condition] When FWE = 1 Flash write enable bit 0 When a low level is input to the FWE pin (hardware-protected state) 1 When a high level is input to the FWE pin Notes: 1. This register is not present in the mask ROM version, and an attempt to read it will return an undefined value. 2. To access this register, set the FLSHE bit to 1 in serial control register X (SCRX). Even if FLSHE = 1, if the chip is in a mode in which the on-chip flash memory is disabled, a read will return H'00 and writes are invalid. Writes to this register are also invalid when the FWE bit in FLMCR1 is not set to 1. Note: * Determined by the state of the FWE pin. 984 FLMCR2--Flash Memory Control Register 2 Bit : 7 FLER Initial value : Read/Write : 0 R 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- H'FFA9 3 -- 0 -- 2 -- 0 -- 1 -- 0 -- ROM 0 -- 0 -- Flash memory error 0 Flash memory is operating normally Flash memory program/erase protection (error protection) is disabled [Clearing condition] Reset or hardware standby mode 1 An error has occurred during flash memory programming/erasing Flash memory program/erase protection (error protection) is enabled [Setting condition] See section 19.8.3, Error Protection Notes: 1. This register is not present in the mask ROM version, and an attempt to read it will return an undefined value. 2. To access this register, set the FLSHE bit to 1 in serial control register X (SCRX). Even if FLSHE = 1, if the chip is in a mode in which the on-chip flash memory is disabled, a read will return H'00 and writes are invalid. Writes to this register are also invalid when the FWE bit in FLMCR1 is not set to 1. EBR1--Erase Block Register 1 Bit : 7 EB7 Initial value : Read/Write : 0 R/W 6 EB6 0 R/W 5 EB5 0 R/W 4 EB4 0 R/W H'FFAA 3 EB3 0 R/W 2 EB2 0 R/W 1 EB1 0 R/W ROM 0 EB0 0 R/W Sets flash memory erase area block by block 985 EBR2--Erase Block Register 2 Bit : 7 -- Initial value : Read/Write : 0 R/W 6 -- 0 R/W 5 -- 0 R/W 4 -- 0 R/W H'FFAB 3 EB11 0 R/W 2 EB10 0 R/W 1 EB9 0 R/W ROM 0 EB8 0 R/W Sets flash memory erase area block by block Flash memory erase blocks Block (Size) EB0 (4 kbytes) EB1 (4 kbytes) EB2 (4 kbytes) EB3 (4 kbytes) EB4 (4 kbytes) EB5 (4 kbytes) EB6 (4 kbytes) EB7 (4 kbytes) EB8 (32 kbytes) EB9 (64 kbytes) EB10 (64 kbytes) EB11 (64 kbytes) Addresses H'000000-H'000FFF H'001000-H'001FFF H'002000-H'002FFF H'003000-H'003FFF H'004000-H'004FFF H'005000-H'005FFF H'006000-H'006FFF H'007000-H'007FFF H'008000-H'00FFFF H'010000-H'01FFFF H'020000-H'02FFFF H'030000-H'03FFFF Notes: 1. This register is not present in the mask ROM version, and an attempt to read it will return an undefined value. 2. To access this register, set the FLSHE bit to 1 in serial control register X (SCRX). Even if FLSHE = 1, if the chip is in a mode in which the on-chip flash memory is disabled, a read will return H'00 and writes are invalid. Writes to this register are also invalid when the FWE bit in FLMCR1 is not set to 1. 986 FLPWCR--Flash Memory Power Control Register Bit : 7 PDWND Initial value : Read/Write : 0 R/W 6 -- 0 R 5 -- 0 R 4 -- 0 R H'FFAC 3 -- 0 R 2 -- 0 R 1 -- 0 R ROM 0 -- 0 R Power-down disable 0 Transition to flash memory power-down mode enabled 1 Transition to flash memory power-down mode disabled PORT1--Port 1 Register Bit : 7 P17 Initial value : Read/Write : --* R 6 P16 --* R 5 P15 --* R 4 P14 --* R H'FFB0 3 P13 --* R 2 P12 --* R 1 P11 --* R Port 1 0 P10 --* R State of port 1 pins Note: * Determined by the state of pins P17 to P10. PORT4--Port 4 Register Bit : 7 P47 Initial value : Read/Write : --* R 6 P46 --* R 5 P45 --* R 4 P44 --* R H'FFB3 3 P43 --* R 2 P42 --* R 1 P41 --* R Port 4 0 P40 --* R State of port 4 pins Note: * Determined by the state of pins P47 to P40. 987 PORT9--Port 9 Register Bit : 7 P97 Initial value : Read/Write : --* R 6 P96 --* R 5 P95 --* R 4 P94 --* R H'FFB8 3 P93 --* R 2 P92 --* R 1 P91 --* R Port 9 0 P90 --* R State of port 9 pins Note: * Determined by the state of pins P97 to P90. PORTA--Port A Register Bit : 7 -- Initial value : Read/Write : -- 6 -- -- 5 PA5*2 --*1 R 4 PA4*2 --*1 R H'FFB9 3 PA3 --*1 R 2 PA2 --*1 R 1 PA1 --*1 R Port A 0 PA0 --*1 R Undefined Undefined State of port A pins Notes: *1 Determined by the state of pins PA5 to PA0. *2 Reserved bits in the H8S/2626 Series. PORTB--Port B Register Bit : 7 PB7 Initial value : Read/Write : --* R 6 PB6 --* R 5 PB5 --* R 4 PB4 --* R H'FFBA 3 PB3 --* R 2 PB2 --* R 1 PB1 --* R Port B 0 PB0 --* R State of port B pins Note: * Determined by the state of pins PB7 to PB0. 988 PORTC--Port C Register Bit : 7 PC7 Initial value : Read/Write : --* R 6 PC6 --* R 5 PC5 --* R 4 PC4 --* R H'FFBB 3 PC3 --* R 2 PC2 --* R 1 PC1 --* R Port C 0 PC0 --* R State of port C pins Note: * Determined by the state of pins PC7 to PC0. PORTD--Port D Register Bit : 7 PD7 Initial value : Read/Write : --* R 6 PD6 --* R 5 PD5 --* R 4 PD4 --* R H'FFBC 3 PD3 --* R 2 PD2 --* R 1 PD1 --* R Port D 0 PD0 --* R State of port D pins Note: * Determined by the state of pins PD7 to PD0. PORTE--Port E Register Bit : 7 PE7 Initial value : Read/Write : --* R 6 PE6 --* R 5 PE5 --* R 4 PE4 --* R H'FFBD 3 PE3 --* R 2 PE2 --* R 1 PE1 --* R Port E 0 PE0 --* R State of port E pins Note: * Determined by the state of pins PE7 to PE0. 989 PORTF--Port F Register Bit : 7 PF7 Initial value : Read/Write : --* R 6 PF6 --* R 5 PF5 --* R 4 PF4 --* R H'FFBE 3 PF3 --* R 2 PF2 --* R 1 PF1 --* R Port F 0 PF0 --* R State of port F pins Note: * Determined by the state of pins PF7 to PF0. 990 Appendix C I/O Port Block Diagrams C.1 Port 1 Block Diagrams Reset Internal data bus R Q D P1nDDR C WDDR1 Reset R Q D P1nDR C P1n * WDR1 Internal address bus System controller Address output enable PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR1 Input capture input RPOR1 Legend WDDR1: WDR1: RDR1: RPOR1: n = 0 or 1 Write to P1DDR Write to P1DR Read P1DR Read port 1 Note: * Priority order: address output > output compare output/PWM output > pulse output > DR output Figure C-1 (a) Port 1 Block Diagram (Pins P10 and P11) 991 Reset Internal address bus System controller Address output enable PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR1 Input capture input External clock input Legend WDDR1: WDR1: RDR1: RPOR1: n = 2 or 3 R Q D P1nDDR C WDDR1 Reset R Q D P1nDR C * WDR1 P1n From internal address bus RPOR1 Write to P1DDR Write to P1DR Read P1DR Read port 1 Note: * Priority order: address output > output compare output/PWM output > pulse output > DR output Figure C-1 (b) Port 1 Block Diagram (Pins P12 and P13) 992 Internal data bus Reset R Q D P14DDR C WDDR1 Reset R Q D P14DR C WDR1 P14 * RDR1 RPOR1 Internal data bus PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output Input capture input Interrupt controller IRQ0 interrupt input Legend WDDR1: WDR1: RDR1: RPOR1: Write to P1DDR Write to P1DR Read P1DR Read port 1 Note: * Priority order: output compare output/PWM output > pulse output > DR output Figure C-1 (c) Port 1 Block Diagram (Pin P14) 993 Reset R Q D P15DDR C WDDR1 Reset R Q D P15DR C WDR1 PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR1 P15 * RPOR1 Internal data bus Input capture input External clock input Legend WDDR1: WDR1: RDR1: RPOR1: Write to P1DDR Write to P1DR Read P1DR Read port 1 Note: * Priority order: output compare output/PWM output > pulse output > DR output Figure C-1 (d) Port 1 Block Diagram (Pin P15) 994 Reset R Q D P16DDR C WDDR1 Reset R Q D P16DR C * WDR1 P16 RDR1 RPOR1 Internal data bus PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output Input capture input Interrupt controller IRQ1 interrupt input Legend WDDR1: WDR1: RDR1: RPOR1: Write to P1DDR Write to P1DR Read P1DR Read port 1 Note: * Priority order: output compare output/PWM output > pulse output > DR output Figure C-1 (e) Port 1 Block Diagram (Pin P16) 995 Reset R Q D P17DDR C WDDR1 Reset R Q D P17DR C * WDR1 P17 RDR1 RPOR1 Internal data bus PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output Input capture input External clock input Legend WDDR1: WDR1: RDR1: RPOR1: Write to P1DDR Write to P1DR Read P1DR Read port 1 Note: * Priority order: output compare output/PWM output > pulse output > DR output Figure C-1 (f) Port 1 Block Diagram (Pin P17) 996 C.2 Port 4 Block Diagram Internal data bus A/D converter module Analog input Internal data bus A/D converter module Analog input RPOR4 P4n Legend RPOR4: Read port 4 n = 0 to 7 Figure C-2 Port 4 Block Diagram (Pins P40 to P47) C.3 Port 9 Block Diagram RPOR9 P9n Legend RPOR9: Read port 9 n = 0 to 7 Figure C-3 Port 9 Block Diagram (Pins P90 to P97) 997 C.4 Port A Block Diagrams Reset Internal address bus R Q D PA0PCR C WPCRA RPCRA Reset R Q D PA0DDR C *1 WDDRA Reset R Q D PA0DR C WDRA Reset R Q D PA0ODR C WODRA RODRA PA0 Modes 4 to 6 Address enable *2 RDRA RPORA Legend WDDRA: WDRA: WODRA: WPCRA: RDRA: RPORA: RODRA: RPCRA: Write to PADDR Write to PADR Write to PAODR Write to PAPCR Read PADR Read port A Read PAODR Read PAPCR Notes: *1 Output enable signal *2 Open drain control signal Figure C-4 (a) Port A Block Diagram (Pin PA0) 998 Internal data bus Reset Internal data bus R Q D PA1PCR C WPCRA RPCRA Internal address bus Smart card mode signal TxD output TxD output enable Reset R Q D PA1DDR C WDDRA *1 Reset R Q D PA1DR C WDRA Reset R Q D PA1ODR C WODRA RODRA PA1 Modes 4 to 6 Address enable *2 RDRA RPORA Legend WDDRA: WDRA: WODRA: WPCRA: RDRA: RPORA: RODRA: RPCRA: Write to PADDR Write to PADR Write to PAODR Write to PAPCR Read PADR Read port A Read PAODR Read PAPCR Notes: *1 Output enable signal *2 Open drain control signal Figure C-4 (b) Port A Block Diagram (Pin PA1) 999 Reset Internal address bus R Q D PA2PCR C WPCRA RPCRA RxD input enable SCK output SCK output enable Reset R Q D PA2DDR C *1 WDDRA Reset R Q D PA2DR C WDRA Reset R Q D PA2ODR C WODRA RODRA PA2 Modes 4 to 6 Address enable *2 RDRA RxD input RPORA Legend WDDRA: WDRA: WODRA: WPCRA: RDRA: RPORA: RODRA: RPCRA: Write to PADDR Write to PADR Write to PAODR Write to PAPCR Read PADR Read port A Read PAODR Read PAPCR Notes: *1 Output enable signal *2 Open drain control signal Figure C-4 (c) Port A Block Diagram (Pin PA2) 1000 Internal data bus Reset Internal address bus R Q D PA3PCR C WPCRA RPCRA SCK input enable SCK output SCK output enable Reset R Q D PA3DDR C *1 WDDRA Reset R Q D PA3DR C WDRA Reset R Q D PA3ODR C WODRA RODRA PA3 Modes 4 to 6 Address enable *2 RDRA SCK input RPORA Legend WDDRA: WDRA: WODRA: WPCRA: RDRA: RPORA: RODRA: RPCRA: Write to PADDR Write to PADR Write to PAODR Write to PAPCR Read PADR Read port A Read PAODR Read PAPCR Notes: *1 Output enable signal *2 Open drain control signal Figure C-4 (d) Port A Block Diagram (Pin PA3) Internal data bus 1001 Reset R Q D PAnPCR C WPCRA RPCRA Reset R Q D PAnDDR C *1 WDDRA Reset PAn R Q D PAnDR C WDRA *2 Reset R Q D PAnODR C WODRA RODRA RDRA RPORA Legend WDDRA: WDRA: WODRA: WPCRA: RDRA: RPORA: RODRA: RPCRA: n = 4 or 5 Write to PADDR Write to PADR Write to PAODR Write to PAPCR Read PADR Read port A Read PAODR Read PAPCR Notes: In the H8S/2626 Series, PA5 and PA4 are OSC2 and OSC1, respectively. *1 Output enable signal *2 Open drain control signal Figure C-4 (e) Port A Block Diagram (Pins PA4 and PA5) 1002 Internal data bus C.5 Port B Block Diagram Reset Internal address bus R Q D PBnPCR C WPCRB RPCRB (Output compare) TPU output TPU output enable Reset R Q D PBnDDR C WDDRB Reset R Q D PBnDR C WDRB Reset R Q D PBnODR C WODRB RODRB *1 PBn Modes 4 to 6 Address enable *2 RDRB TPU input (input capture) RPORB Legend WDDRB: WDRB: WODRB: WPCRB: RDRB: RPORB: RODRB: RPCRB: n = 0 to 7 Write to PBDDR Write to PBDR Write to PBODR Write to PBPCR Read PBDR Read port B Read PBODR Read PBPCR Notes: *1 Output enable signal *2 Open drain control signal Figure C-5 Port B Block Diagram (Pins PB0 to PB7) 1003 Internal data bus C.6 Port C Block Diagrams Reset Internal address bus R Q D PCnPCR C WPCRC RPCRC Smart card mode signal TxD output TxD output enable Reset R Q D PCnDDR C WDDRC Reset R Q D PCnDR C WDRC Reset R Q D PCnODR C WODRC RODRC *1 PCn Modes 4 to 6 Address enable *2 RDRC RPORC Legend WDDRC: WDRC: WODRC: WPCRC: RDRC: RPORC: RODRC: RPCRC: n = 0 or 3 Write to PCDDR Write to PCDR Write to PCODR Write to PCPCR Read PCDR Read port C Read PCODR Read PCPCR Notes: *1 Output enable signal *2 Open drain control signal Figure C-6 (a) Port C Block Diagram (Pins PC0 and PC3) 1004 Internal data bus Reset R Q D PCnPCR C WPCRC RPCRC RxD input enable Reset R Q D PCnDDR C *1 WDDRC Reset R Q D PCnDR C WDRA Reset R Q D PCnODR C WODRC RODRC PCn Modes 4 to 6 Address enable *2 RDRC RxD input RPORC Legend WDDRC: WDRC: WODRC: WPCRC: RDRC: RPORC: RODRC: RPCRC: n = 1 or 4 Write to PCDDR Write to PCDR Write to PCODR Write to PCPCR Read PCDR Read port C Read PCODR Read PCPCR Notes: *1 Output enable signal *2 Open drain control signal Figure C-6 (b) Port C Block Diagram (Pins PC1 and PC4) Internal address bus Internal data bus 1005 Reset R Q D PCnPCR C WPCRC RPCRC SCK input enable SCK output SCK output enable Reset R Q D PCnDDR C WDDRC Reset R Q D PCnDR C WDRC Reset R Q D PCnODR C WODRC RODRC *1 PCn Modes 4 to 6 Address enable *2 RDRC IRQ interrupt input SCK input RPORC Legend WDDRC: WDRC: WODRC: WPCRC: RDRC: RPORC: RODRC: RPCRC: n = 2 or 5 Write to PCDDR Write to PCDR Write to PCODR Write to PCPCR Read PCDR Read port C Read PCODR Read PCPCR Notes: *1 Output enable signal *2 Open drain control signal Figure C-6 (c) Port C Block Diagram (Pins PC2 and PC5) 1006 Internal address bus Internal data bus Reset Internal data bus R Q D PCnPCR C WPCRC RPCRC PWM output PWM output enable Reset R Q D PCnDDR C *1 WDDRA Reset R Q D PCnDR C WDRA *2 Reset R Q D PCnODR C WODRC RODRC Internal address bus PCn Modes 4 to 6 Mode 6 RDRC RPORC Legend WDDRC: WDRC: WODRC: WPCRC: RDRC: RPORC: RODRC: RPCRC: n = 6 or 7 Write to PCDDR Write to PCDR Write to PCODR Write to PCPCR Read PCDR Read port C Read PCODR Read PCPCR Notes: *1 Output enable signal *2 Open drain control signal Figure C-6 (d) Port C Block Diagram (Pins PC6 and PC7) 1007 C.7 Port D Block Diagram Reset R Q D PDnPCR C WPCRD RPCRD Internal upper data bus Reset R Q D PDnDDR C WDDRD Reset R Q D PDnDR C WDRD External address write PDn Mode 7 Modes 4 to 6 External address upper write RDRD RPORD External address upper read Legend WDDRD: WDRD: WPCRD: RDRD: RPORD: RPCRD: n = 0 to 7 Write to PDDDR Write to PDDR Write to PDPCR Read PDDR Read port D Read PDPCR Figure C-7 Port D Block Diagram (Pins PD0 to PD7) 1008 C.8 Port E Block Diagram Reset Internal upper data bus Internal lower data bus R Q D PEnPCR C WPCRE RPCRE Reset R Q D PEnDDR C WDDRE Reset R Q D PEnDR C WDRE External address write PEn Mode 7 Modes 4 to 6 RDRE RPORE External address lower read Legend WDDRE: WDRE: WPCRE: RDRE: RPORE: RPCRE: n = 0 to 7 Write to PEDDR Write to PEDR Write to PEPCR Read PEDR Read port E Read PEPCR Figure C-8 Port E Block Diagram (Pins PE0 to PE7) 1009 C.9 Port F Block Diagrams Internal data bus Bus controller BRLE bit Reset PF0 R Q D PF0DR C WDRF Bus request input IRQ interrupt input Write to PFDDR Write to PFDR Read PFDR Read port F Reset R Q D PF0DDR C WDDRF Modes 4 to 6 RDRF RPORF Legend WDDRF: WDRF: RDRF: RPORF: Figure C-9 (a) Port F Block Diagram (Pin PF0) 1010 Reset Internal data bus Bus controller BRLE output Bus request input acknowledge output RDRF R Q D PF1DDR C WDDRF Reset R Q D PF1DR C WDRF Modes 4 to 6 PF1 RPORF Legend WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C-9 (b) Port F Block Diagram in the H8S/2623 Series (Pin PF1) 1011 Reset Internal data bus Bus controller BRLE output Bus request input acknowledge output RDRF R Q D PF1DDR C WDDRF Reset R Q D PF1DR C WDRF Modes 4 to 6 BUZZ output BUZZ output enable PF1 RPORF Legend WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C-9 (c) Port F Block Diagram in the H8S/2626 Series (Pin PF1) 1012 Reset R Q D PF2DDR C WDDRF Reset Modes 4 to 6 PF2 Modes 4 to 6 R Q D PF2DR C WDRF Modes 4 to 6 Internal data bus Bus controller Wait enable Bus request output enable Bus request output Wait input RDRF RPORF Legend WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C-9 (d) Port F Block Diagram (Pin PF2) 1013 Reset R Q D PF3DDR C WDDRF Reset R Q D PF3DR C WDRF PF3 Modes 4 to 6 Internal data bus Bus controller LWR output ADTRG input IRQ interrupt input RDRF RPORF Legend WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C-9 (e) Port F Block Diagram (Pin PF3) 1014 Reset R Q D PF4DDR C WDDRF Reset R Q D PF4DR C WDRF PF4 Modes 4 to 6 Internal data bus Bus controller HWR output RDRF RPORF Legend WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C-9 (f) Port F Block Diagram (Pin PF4) 1015 Reset R Q D PF5DDR C WDDRF Reset R Q D PF5DR C WDRF PF5 Modes 4 to 6 Internal data bus Bus controller RD output RDRF RPORF Legend WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C-9 (g) Port F Block Diagram (Pin PF5) 1016 Reset R Q D PF6DDR C WDDRF Reset R Q D PF6DR C WDRF PF6 Modes 4 to 6 Internal data bus Bus controller AS output RDRF RPORF Legend WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C-9 (h) Port F Block Diagram (Pin PF6) 1017 Modes 4 to 6 Reset WDDRF PF7 Internal data bus S* R Q D D PF7DDR C RDRF RPORF Legend WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Note: * Set priority Figure C-9 (i) Port F Block Diagram (Pin PF7) 1018 Appendix D Pin States D.1 Port States in Each Mode Table D-1 I/O Port States in Each Processing State Port Name Pin Name Port 1 MCU Operating Mode 4, 5 PowerOn Reset L Hardware Standby Mode T Software Standby Mode [Address output, OPE = 0] T [Address output, OPE = 1] kept [Otherwise] kept 7 Port 4 Port 9 PA5 PA4 PA3/A19 PA2/A18 PA1/A17 PA0/A16 6 T 4, 5 L T [Address output, OPE = 0] T [Address output, OPE = 1] kept [Otherwise] kept 7 Port B 4, 5 T L T T kept [Address output, OPE = 0] T [Address output, OPE = 1] kept [Otherwise] kept 7 T T kept kept I/O port kept [Address output] T [Otherwise] kept I/O port [Address output] A15 to A8 [Otherwise] I/O port [Address output] T [Otherwise] kept [Address output] A19 to A17 [Otherwise] I/O port 4 to 7 4 to 7 4 to 7 T T T T T T T T kept T T kept kept T T kept I/O port Input port Input port I/O port Bus Release State [Address output] T [Otherwise] kept Program Execution State Sleep Mode [Address output] A23 to A20 [Otherwise] I/O port 6 T 6 T 1019 Port Name Pin Name Port C MCU Operating Mode 4, 5 PowerOn Reset L Hardware Standby Mode T Software Standby Mode [OPE = 0] T [OPE = 1] kept Bus Release State T Program Execution State Sleep Mode A7 to A0 6 T T [DDR = 1, OPE = 0] T [DDR = 1, OPE = 1] kept [DDR = 0] kept T [DDR = 1] A7 to A0 [DDR = 0] I/O port 7 Port D 4 to 6 7 Port E 4 to 6 8-bit bus T T T T T T T T T T T kept T kept kept T kept [DDR = 0] T [DDR = 1] H kept T kept kept T kept kept I/O port Data bus I/O port I/O port Data bus I/O port [DDR = 0] T [DDR = 1] Clock output 16-bit T bus 7 PF7/o 4 to 6 7 PF6/AS 4 to 6 T Clock output T H T [OPE = 0] T [OPE = 1] H T AS 7 PF5/RD PF4/HWR PF3/LWR/ ADTRG/IRQ3 7 PF2/WAIT/ BREQO 4 to 6 4 to 6 T H T T kept [OPE = 0] T [OPE = 1] H kept T I/O port RD, HWR, LWR T T T T kept [OPE = 0] T [OPE = 1] kept kept [BREQOE = 1] BREQO [WAITE = 1] T kept I/O port [BREQOE = 1] BREQO [WAITE = 1] WAIT I/O port 7 T T kept 1020 Port Name Pin Name PF1/BACK MCU Operating Mode 4 to 6 PowerOn Reset T Hardware Standby Mode T Software Standby Mode [BRLE = 0] I/O port [BRLE = 1] H Bus Release State [BRLE = 0] I/O port [BRLE = 1] L kept T Program Execution State Sleep Mode [BRLE = 0] I/O port [BRLE = 1] BACK I/O port [BRLE = 0] I/O port [BRLE = 1] BREQ 7 PF0/BREQ/ 4 to 6 IRQ2 T T T T kept [BRLE = 0] kept [BRLE = 1] T 7 HTxD HRxD 4 to 7 4 to 7 T H Input T T T kept H T kept H Input I/O port Output Input Legend: H L T kept DDR OPE WAITE BRLE BREQOE : High level : Low level : High impedance : Input port becomes high-impedance, output port retains state : Data direction register : Output port enable : Wait input enable : Bus release enable : BREQO pin enable 1021 Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Timing of Transition to Hardware Standby Mode (1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low at least 10 states before the STBY signal goes low, as shown below. RES must remain low until STBY signal goes low (delay from STBY low to RES high: 0 ns or more). STBY t110tcyc RES t20ns Figure E-1 Timing of Transition to Hardware Standby Mode (2) To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents do not need to be retained, RES does not have to be driven low as in (1). Timing of Recovery from Hardware Standby Mode Drive the RES signal low and the NMI signal high approximately 100 ns or more before STBY goes high to execute a power-on reset. STBY t100ns RES tOSC tNMIRH NMI Figure E-2 Timing of Recovery from Hardware Standby Mode 1022 Appendix F Product Code Lineup Table F-1 H8S/2626 Series and H8S/2623 Series Product Code Lineup Product Code HD64F2626 HD6432626 HD6432625 HD6432624 F-ZTAT version Mask ROM version H8S/2622 H8S/2621 HD64F2623 HD6432623 HD6432622 HD6432621 Mark Code HD64F2626FA HD6432626FA HD6432625FA HD6432624FA HD64F2623FA HD6432623FA HD6432622FA HD6432621FA Package (Hitachi Package Code) 100-pin QFP (FP-100B) 100-pin QFP (FP-100B) 100-pin QFP (FP-100B) 100-pin QFP (FP-100B) 100-pin QFP (FP-100B) 100-pin QFP (FP-100B) 100-pin QFP (FP-100B) 100-pin QFP (FP-100B) Product Type H8S/2626 F-ZTAT version Mask ROM version H8S/2625 H8S/2624 H8S/2623 1023 Appendix G Package Dimensions Figure G-1 shows the FP-100B package dimensions of the H8S/2626 Series and H8S/2623 Series. Unit: mm 16.0 0.3 14 75 76 51 50 16.0 0.3 100 1 *0.22 0.05 0.20 0.04 25 26 0.5 3.05 Max 2.70 0.08 M 1.0 *0.17 0.05 0.15 0.04 1.0 0 - 8 0.12 +0.13 -0.12 0.10 0.5 0.2 Hitachi Code JEDEC JEITA Mass (reference value) FP-100B - Conforms 1.2 g *Dimension including the plating thickness Base material dimension Figure G-1 FP-100B Package Dimensions 1024 H8S/2626 Series, H8S/2623 Series, H8S/2626F-ZTATTM, H8S/2623F-ZTATTM, Hardware Manual Publication Date: 1st Edition, December 1998 4th Edition, October 2002 Published by: Business Operation Division Semiconductor & Integrated Circuits Hitachi, Ltd. Edited by: Technical Documentation Group Hitachi Kodaira Semiconductor Co., Ltd. Copyright (c) Hitachi, Ltd., 1998. All rights reserved. Printed in Japan. |
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